Migrate the following options to CONFIG_DM:
CONFIG_DM_GPIO
CONFIG_DM_MMC
CONFIG_DM_ETH
CONFIG_DM_SERIAL
CONFIG_DM_USB
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?
That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:
#ifndef cpu_is_sama5d2
#define cpu_is_sama5d2() 0
#endif
That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.
The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:
=> dhcp
ethernet@f8008000: PHY present at 1
ethernet@f8008000: Starting autonegotiation...
ethernet@f8008000: Autonegotiation complete
ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17
Retry time exceeded; starting again
Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!
The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.
Fixes: 245cbc583d ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.
Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]
So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.
Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.
[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html
Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b79106
The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Activate I2C7 on Alt to allow access to the PMIC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.
This reverts commit 0d968ceb1f.
This converts the following to Kconfig:
CONFIG_ENV_SPI_BUS
CONFIG_ENV_SPI_CS
CONFIG_ENV_SPI_MAX_HZ
CONFIG_ENV_SPI_MODE
Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc
pin that the usual toggling of regulator to power the card off and on
is insufficient. When the card is calibrated into UHS SDR104 mode, it
will remain in that mode across the power cycle and subsequent attempt
to communicate with the card will fail.
The test with this card is to insert it into an SDHI slot and perform
"mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail.
Fix this problem by increasing the off-on delay from 0 to 20 mS.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Since commit 27cb7300ff ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.
In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.
As a result, a lot of wrong code have been merged unnoticed.
I am going to revert that commit, and lots of hidden issues have
come to light:
[1] Typos
armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts
use the extension ".dts" instead of ".dtb"
[2] DTB is associated to undefined CONFIG option
For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
associates its device tree to CONFIG_MX6SL, which is undefined.
[3] Lots of entries are missing
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
[trini: add imx6ul pico dtbs]
Signed-off-by: Tom Rini <trini@konsulko.com>
Commit 1416e2d225 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.
Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.
So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Push the Starting kernel print to the end just before the
dm_remove_devices call.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)
Prior to commit 93b283d49f ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.
Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.
Reported-by: Влад Мао <vlaomao@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.
Reported-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Signed-off-by: Stefan Roese <sr@denx.de>
Syscon register is required in dts to select correct
PHY interface.
Fix error below:
Net: Failed to get syscon: -2
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
spba-bus has a few nodes under it including the UART1 and
some ESPI buses. In order to use them in SPL, the
u-boot,dm-spl flag needs to be added to the spba-bus@2000000
container.
Signed-off-by: Adam Ford <aford173@gmail.com>
Currently the CPU frequency is incorrectly reported:
CPU: NXP i.MX8QXP RevB A35 at 147228 MHz
Fix this problem by using a direct call to the SCU firmware to
retrieve the Cortex A35 CPU frequency.
With this change applied the CPU frequency is displayed correctly:
CPU: NXP i.MX8QXP RevB A35 at 1200 MHz
Tested-by: Marcelo Macedo <marcelo.macedo@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Select CONFIG_DM_MMC=y in order to support MMC driver model.
This allows the MMC board related code to be removed.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Just add spaces around '=' sign for clarity.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add startup time to LDO regulators of S2MPS11 PMIC on Odroid XU3/XU4/HC1
family of boards to be sure the voltage is proper before relying on the
regulator.
The datasheet for all the S2MPS1x family is inconsistent here and does
not specify unambiguously the value of ramp delay for LDO. It mentions
30 mV/us in one timing diagram but then omits it completely in LDO
regulator characteristics table (it is specified for bucks).
However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12
mV/us or 24 mV/us.
Without the ramp delay value the consumers do not wait for voltage
settle after changing it. Although the proper value of ramp delay for
LDOs is unknown, it seems safer to use at least some value from
reference kernel than to leave it unset.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The ADC block requires VDD supply to be on so provide one.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
v2019.01 commit cbff9f80ce ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.
Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
- f529bc551b ("ARM: dts: rmobile: Extract USB nodes on M3N")
- 830b94f768 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")
Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
- not needed if no U-boot-specific changes are needed in those nodes.
- potentially dangerous/error-prone, since the duplicated properties
override the properties originally defined in <soc>.dtsi. One
possible consequence is that <soc>.dtsi is getting an update from
Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
the obsolete property values from <soc>-u-boot.dtsi will take
precedence masking some of the <soc>.dtsi updates, potentially
leading to all kind of obscure issues.
Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).
What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.
$> dtdiff before-r8a77965-salvator-x-u-boot.dtb \
after-r8a77965-salvator-x-u-boot.dtb
--- /dev/fd/63 2019-03-09 12:57:40.877963983 +0100
+++ /dev/fd/62 2019-03-09 12:57:40.877963983 +0100
@@ -1471,7 +1471,7 @@
bus-width = <0x4>;
cd-gpios = <0x51 0xc 0x1>;
clocks = <0x6 0x1 0x13a>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
interrupts = <0x0 0xa5 0x4>;
max-frequency = <0xc65d400>;
pinctrl-0 = <0x4d>;
@@ -1492,7 +1492,7 @@
sd@ee120000 {
clocks = <0x6 0x1 0x139>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
interrupts = <0x0 0xa6 0x4>;
max-frequency = <0xbebc200>;
power-domains = <0x1 0x20>;
@@ -1504,7 +1504,7 @@
sd@ee140000 {
bus-width = <0x8>;
clocks = <0x6 0x1 0x138>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
fixed-emmc-driver-type = <0x1>;
interrupts = <0x0 0xa7 0x4>;
max-frequency = <0xbebc200>;
@@ -1526,7 +1526,7 @@
bus-width = <0x4>;
cd-gpios = <0x5a 0xf 0x1>;
clocks = <0x6 0x1 0x137>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
interrupts = <0x0 0xa8 0x4>;
max-frequency = <0xc65d400>;
pinctrl-0 = <0x56>;
@@ -1868,14 +1868,14 @@
usb-phy@ee0a0200 {
#phy-cells = <0x0>;
- clocks = <0x6 0x1 0x2be>;
+ clocks = <0x6 0x1 0x2bf>;
compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy";
phandle = <0x47>;
pinctrl-0 = <0x4c>;
pinctrl-names = "default";
power-domains = <0x1 0x20>;
reg = <0x0 0xee0a0200 0x0 0x700>;
- resets = <0x6 0x2be>;
+ resets = <0x6 0x2bf>;
status = "okay";
};
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until
we can do better using the new SPI NOR framework.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Imply all SoCs supported by a given board. This allows building single
U-Boot binary for boards which can have multiple SoCs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Imply preferred pin control driver per SoC, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.
The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.
This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.
The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a ("armv7: add PL310 support to u-boot")
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef.
But the nyan devices never received that functionality.
Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button.
With this patch keyboard is working by only pressing [power] button.
Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
- Switch to using the omap3-u-boot.dtsi file for needed properties.
- Remove a few SPL features to free up more SRAM space.
- Switch CONFIG_SYS_TEXT_BASE to the normal default, we don't need to
worry about X-Loader at this point anymore.
- A few related updates to SPL options as part of switching to DM SPL.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
With the generic omap3-u-boot.dtsi file available, this patch
increased the memory of the various incarnations of the omap3_logic
board, and points their respective u-boot.dtsi files to the newly
created generic one, and removes the PLATDATA from the board file.
These are all done at once because the're all utilizing the same
omap3logic.c board file.
Signed-off-by: Adam Ford <aford173@gmail.com>
Create generic omap3-u-boot.dtsi file that omap3 based boards
can include to generate device tree in SPL for booting MLO.
Credit should go to Tom Rini.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
This commit converts the brxre1 board to DM,
for this we have todo following things:
- add a devicetree-file for this board
- drop all obsolete settings from board header-file
- use dm_i2c_xxx calls for read/write to the resetcontroller
- request gpios before operate them
Serues-cc: trini@konsulko.com
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface
support.
this changed is to fixed the ls1043ardb compile warning as fallows:
===================== WARNING ======================
This board does not use CONFIG_DM_SCSI. Please update
the storage controller to use CONFIG_DM_SCSI before the
v2019.07 release. Failure to update by the deadline may
result in board removal.See doc/driver-model/MIGRATION.txt
for more info.
====================================================
Signed-off-by: Peng Ma <peng.ma@nxp.com>
[PK: reword the patch subject]
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
LX2160AQDS is a development board that supports LX2160A
family SoCs. This patch add base support for this board.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[PK: Sqaush patch for "secure boot defconfig" & add maintainer]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.
Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
or not? if it is (fsl_serdes_init has already enabled the dpmac), then
don't enable it.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Add code to initial ethernet interface arrays
with corresponding dpmac-id values in serdes_init function
for LX2160A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
As per hardware documentation,
CONFIG_SYS_FSL_PEBUF_BASE for lx2160a is 0x1c00000000
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
The 'dwmac_socfpga' ETH driver can now get the MACs out of reset
via the socfpga reset driver and can set PHY mode via syscon.
This means we can now remove the ad-hoc code to do this from
arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
As the H5 is pin compatible with the H3, vendors tend to upgrade their
existing H3 products with an H5 SoC swap. This is the case with the
Bananapi M2+ H5.
Add the following to support it:
- device tree file: synced from Linux v5.0-rc1,
- defconfig: copy of bananapi_m2_plus_h3_defconfig with only SoC
family and default device tree file name changed
- MAINTAINERS entry
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
As of commit aa8fee415f46 ("ARM: dts: sun8i: h3: Split out
non-SoC-specific parts of Bananapi M2 Plus") in the Linux kernel, the
device tree for the Bananapi M2+ has been split into a common dtsi file,
and an SoC-specific board device tree file that includes both the shared
dtsi file and the soc dtsi file. This was done to support both the H3
and H5 variants of the same board. This is similar to what was done for
the Libre Computer ALL-H3-CC in U-boot commit d7b17f1c24 ("sunxi: Split
out common board design for ALL-H3-CC device tree").
The newly split files are directly synced from Linux tag v5.0-rc1.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This makes get_imx_reset_cause() accessible in SPL, but keeps the SRSR
register content intact so that U-Boot proper can evaluated the
reset_cause again should this be needed.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones
from kernel v4.20 (commit 8fe28cb58bcb2).
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
This allows us to keep the basic dts[i] files up-to-date with
the ones in kernel, but at the same time allowing the u-boot
to add its own properties to the existing nodes.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL,
makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE.
Everything that is not part of the usb storage support in SPL is now
build under SPL_USB_HOST_SUPPORT.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".
Linux commit a13f18f59d26 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.
Linux docs:
Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds reset-on-timeout to FPD WDT which will trigger an
interrupt to PMU when watchdog expiry happens and PMU takes the
necessary action. If this property is not enabled, reason will not be
known when watchdog expiry happens.
This patch also modifies the default timeout to 60 seconds. Reason is
that if u-boot enables WDT, it will set the timeout to 10 seconds and
this is not enough to boot till Linux and start the WDT application in
Linux. 60 seconds is the maximum safest value to boot till Linux and
start the WDT application.
Users need to change this timeout value to fit their needs.
Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Replace the current value of the model property by a more accurate
description of each board (which includes the manufacturer), as some
of the boards had the same value ("Xilinx Zynq")
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Both boards are made by Avnet, Inc. So add an additional
value to the compatible property
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Import liteSOM and liteboard dts files from Linux v4.20. They will
be used after transition to driver model and device-tree based boot.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This patch extends the vf610 DDR memory controller code to support SW
leveling.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
This patch provides the code to calibrate the DDR's
DQS to DQ signals (RDLVL).
It is based on:
VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"
and NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Replace SDHCI controller listing by Kconfig symbol to let SPL know that
this board is using multiple SDHCIs controllers.
Kconfig help message should explain why this is needed.
Origin symbols were used in full u-boot but with moving to distro boot
this was fixed already.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
All platforms have been converted to DM that's why there is no reason to
keep addresses in headers. They are all read from DT now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
CONFIG_PCA953X is not needed because of PCA953X is integrated in gpio
subsystem already. That's why also remove CMD_PCA953X which is only for
this driver.
zcu102/zcu104-revC/zcu106/zcu111 contain links to eeprom which stores MAC address.
DM_I2C is not enabled for the whole SoC because it increase size for
mini configurations and there is no I2C symbol present to setup
dependencies.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
All platforms have been converted to DM that's why there is no reason to
keep addresses in headers. They are all read from DT now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Boards have only one controller enabled that's why move to DM_I2C is
easy.
Add also i2c alias for not to be shown as i2c bus -1 because alias
doesn't exist.
Config file points to MAC stored in eeprom but it is not listed that's
why I have added 24c08 part.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This patch adds new mini target for versal.
This configuration is very minimal in size which runs
from OCM. It contains support for mtest which can be
used for running DDR memory tests.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds mini eMMC configuration which has only
emmc0 and emmc1 functionalities and can run from small
amount of memory. This is required for memory constraint
devices.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds new config option which is used for
reserving a specific memory for MMU Table and in this
case we are using TCM for that purpose.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Commit 81ea00838c ("efi_loader: PSCI reset and shutdown") put the SMCCC
assembly code into the efi specific code section. This is wrong when we
do not have EFI_LOADER enabled, as that strips efi runtime sections from
the output binary
Reported-by: Michal Simek <monstr@monstr.eu>
Reported-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Tested-by: Michal Simek <monstr@monstr.eu>
Fixes: 81ea00838c ("efi_loader: PSCI reset and shutdown")
Signed-off-by: Alexander Graf <agraf@suse.de>
Refactor the switch from supervisor to hypervisor to a new function called
at the beginning of do_bootefi().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
ARMv7-M only supports the Thumb instruction set. Our current crt0 code does
not support it. With the patch we can build all unit tests of the EFI
subsystem that do not require crt0.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
The PCIe slot PERST signal is active low. Fix the gpio signal
description in the dts.
This happened to work because the pcie_dw_mvebu driver sets the reset
gpio level to 1 (high) to release the reset. The following commit will
fix that.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Common sound support
buildman environment support
of-platdata documentation improvements
-----BEGIN PGP SIGNATURE-----
iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlxf7igRHHNqZ0BjaHJv
bWl1bS5vcmcACgkQfxc6PpAIreYKfggApQiL0Gv6NdGAQN+zfpjKY5a2QyjKsAxa
KLm3q8XyXIQXufMWOEPoW1iWm0iixpIFgChy8ff3m/OPDzsx99UXDTyvjitsSxtQ
5tFu8K78nUZT6OOE3HNhhlyW/xK442oKBzGt4MUt3kUZOELsCNuftgbJUWksHuO3
6pPrgt36E0uRGbUA4ioYCU336viJRPOOCdqb8hHViEihFj/IEv5T82RdE5y97YxG
dT7BZxjPkBH5ZN1uD/tdxG1k6IZBagZiYoDAsYp4YqNwmVsm5sLrZ9QVSf7EcH/y
qX8butZesiMd7xm7RROlrIImh7fb36N3zsoRiUWZDo1Al3IRkmZyVA==
=tdut
-----END PGP SIGNATURE-----
Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dm
Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Update the flashmap so that this board can be started over USB A-A. It
is slightly different from snow.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Update the spring settings to use this codec, which is what it actually
shipped with.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Move all exynos boards over to use CONFIG_BLK.
This converts s5p_goni also, but adding dummy functions for pinmux and
peripheral ID. This will not function correctly, but gives the maintainer
more time to convert the board if desired.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Perform some cosmetic cleanup of the ATF image startup function, namely
fixing a spelling mistake, capitalization of a few words, spacing, as
well aligning how errors are printed and as using panic() for cases that
were using a combination of printf() + hang().
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This add the initial support of the broadcom reference
board bcm963158 with a bcm63158 SoC.
This board has 1 GB of ram, 512 MB of flash (nand),
2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN).
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
This add the initial support of the broadcom bcm63158 SoC family,
only the cpu, dram and uart are supported.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
- PLL3P set to 208.8MHz for MCU sub-system
- PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
- PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
- PLL4P set to 99MHz for SDMMC and SPDIFRX
- PLL4Q set to 74.25MHz for EVAL board
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
commit fdce9d35dc ("arm: dts: am33xx: Sync dts with Linux 4.20.0")
did remove the "u-boot,dm-spl" flag from the 'ocp' bus which was
introduced with
commit 19aa4ac09d ("dts: am33xx: add u-boot, dm-spl to ocp bus")
Due to this all boards having CONFIG_SPL_OF_CONTROL enabled are broken
because they cannot bind/probe the boot-media interface during SPL
stage.
This commit introduces the 'am33xx-u-boot.dtsi' which is included with
the auto include mechanism. The am33xx-u-boot-dtsi adds the important
"u-boot,dm-pre-reloc" to the 'ocp bus' (the root bus of almost all
peripherals, at least the bootable ones).
The peripherials (mmc, spi, ...) needed during SPL stage need to be
equipped with the 'u-boot,dm-pre-reloc' in their responsible dts file.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
With the new DM_VIDEO support in the Armada XP LCD driver, this patch
adds the needed DT node for the LCD controller to the theadorable dts
file. This DT property is not added to the Armada XP dtsi files, as this
LCD feature is pretty unusual for this SoC and I personally know of no
other board that uses this controller.
This patch also enables CONFIG_BMP_16BPP/24BPP/32BPP, as the "old" bmp
command supported these BMP files.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this
move, the legacy interface board_video_init() is removed from the
theadorable board code (only user of this video driver). The support
via DT will be added in a separate patch.
This patch also enables DM_VIDEO for the theadorable board, as this is
needed to not break git bisect'ability.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC.
micro-DPU is the single-port FTTdp "distribution point unit" made by Methode Electronics
which offers complete modularity with replaceable SFP modules both for uplink and downlink
(G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable).
On-board features:
- 512 MiB DDR3
- 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC
- USB 2.0 Type-C connector
- 4GB eMMC
- ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type)
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Luis Torres <luis.torres@methode.com>
Cc: Scott Roberts <scott.roberts@telus.com>
Cc: Paul Arola <paul.arola@telus.com>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Now that the PCIe driver supports DM and DT parsing, enable the PCIe DT
nodes that are used by this board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
This patch sync's the PCIe DT nodes with the recent Linux v4.20 version.
This change makes it easier to reference specific PCIe nodes in the
board dts files to e.g. enable a PCIe port as this is now necessary with
the new DM PCI driver for these platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
* support for Chromebook Bob
* full pinctrl driver using DTS properties
* documentation improvements
* I2S support for some Rockchip SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcVG0IAAoJECaAFcEOcohNKVAIAJd3DN/qudcVQdkuvAGK6WIk
Umxkm6rxHwur7oU+wxvK1p1l/0YTFBeCfo15quH1DkSc/WIUnmBlLmDvqpGVmPmh
ydZNE9ZChn0OKRIaM6pKJr+3p155cQDe6Mgg2j/5CnNx28KxT+vu7EqZbZvbQPag
wcZEK6Z6E5jMVHVn2lbLgmsBPmY7ksX168IqpvzTxIj0a4J3n0DcJUnO4RBBS0Q2
PGEvFhTvigVWs6r6GL0gLn3VwnQX30xQlIuKKORPcdhjk97cJcS4+bRxdTENTKD9
j3+pgyl1n04O8sPONZS7pH3fvJwtC6SwnoxTYxGrvjedw1LxbyHG3cqcGDg/TJ8=
=ik3X
-----END PGP SIGNATURE-----
Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip
u-boot-rockchip changes for 2019.04-rc1:
* support for Chromebook Bob
* full pinctrl driver using DTS properties
* documentation improvements
* I2S support for some Rockchip SoCs
With the latest changes to add support for the Chromebook Bob,
initialisation through debug_uart_init() did no longer get called for
other targets.
Fix this, by moving debug_uart_init() out of the Bob-specific
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C
ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports
for both power and external display. It includes a Chrome OS EC
(Cortex-M3) to provide access to the keyboard and battery functions.
Support so far includes only:
- UART
- SDRAM
- MMC, SD card
- Cros EC (but not keyboard)
Not included:
- Keyboard
- Display
- Sound
- USB
- TPM
Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support
for this is not provided in this series.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add some U-Boot-specific settings. These should really go in the
*u-boot.dtsi file, but it seems that rk3399 does not use that yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
At present this enum is only available to rk3288. Move it so that other
rockchip SoCs can access it. It is needed for the SPL GPIO driver for
rk3999 in a later patch.
Also adjust the enum name to lower case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
These board files have inconsistent #include ordering. Fix them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This memory is used on Bob. Add settings for this, taken from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The u-boot,spl-boot-device property only allows MMC at present. Add SPI as
well for boards that boot from SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This file has changed upstream, with some additions and changes. Move the
U-Boot version towards this.
Some USB changes seem to be incompatible with how the bindings work on
rockchip in U-Boot. Testing is needed to make sure that USB still works
correct, and adjust the code (not device tree) if not.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Bring in these files from Linux v4.20.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Like on rk3399-puma we want to continue booting the fill U-Boot from
the same device as the SPL stage.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which do not
have this feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jerry uses a max98090 audio codec and the internal SoC I2S peripheral.
Enable sound support and add the required device-tree pieces.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Although not required, it doesn't hurt to explicitly map the USB ports to
a USB controller. Without this, the port number will be derived from the
binding order of the peripheral devices.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPLY_FS_EXT4 so both
obj-$(CONFIG_$(SPL_)FS_EXT4) and CONFIG_IS_ENABLED(FS_EXT4) can be
used to control the build in both SPL and U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT so
obj-$(CONFIG_$(SPL_)FS_FAT) can be used to control the build in both
SPL and U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This USB port is mainly used for RNDIS and DFU. To be able to use it with
DM_USB and DM_USB_GADGET, we need to provide a dr_mode value in the DTS.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
add u-boot specific am335x-shc-u-boot.dtsi file,
in which we add u-boot specific adaptions.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
add DTS from linux tree commit
"47bfa6d9dc8c060bf56554a465c9031e286d2f80"
change for U-Boot:
switch to SPDX-license identifier.
Signed-off-by: Heiko Schocher <hs@denx.de>
If VIDEO_MESON is enabled, we need to setup the fdt for the framebuffer.
Call meson_vpu_rsv_fb() which reserves the framebuffer memory region for
EFI, and sets up simple-framebuffer nodes if simplefb support is
enabled.
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
There's no reliable way to reuse the hhi entry from the vpu as is done
in the linux kernel, so we duplicate it here.
We will be able to sync against kernel DTS in the future when the VPU
gets based on the clock framework rather than the HHI reg.
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The hdmi_5v regulator must be enabled to provide power to the physical HDMI
PHY and enables the HDMI 5V presence loopback for the monitor.
Fixes: b409f625a6d5 ("ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
[backport of linux commit e1f2163deac059ad39f07aba9e314ebe605d5a7a]
Flag the appropriate nodes with u-boot,dm-pre-reloc
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This adds video output support for Amlogic GXBB/GXL/GXM chips.
The supported ports are CVBS and HDMI (based on DW_HDMI).
When using HDMI, only DMT modes are supported.
There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB)
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed defines alignment in meson_canvas.c]
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.
Also removed DM_MMC enablement in few parts of sunxi
configurations.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Like other Allwinner A64 boards, pinebook also need altering
auto-numbering of mmc2 to mmc1 which is available in common
sunxi dsti file, sunxi-u-boot.dtsi
Pinebook has a separate sun50i-a64-pinebook-u-boot.dtsi which
takes more precedence for u-boot.dtsi inclusion and it eventually
failed to include the sunxi-u-boot.dtsi.
So, this patch add support to include the sunxi-u-boot.dtsi in the
sun50i-a64-pinebook-u-boot.dtsi
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com> # Pinebook
Environment and fastboot mmc devices are configured based on the number
of mmc slots defined on particular board configs, MMC_SUNXI_SLOT_EXTRA.
If MMC_SUNXI_SLOT_EXTRA is more than 1, the default env and fastboot
mmc devices is mmc1 by assuming mmc0 is SD and mmc1 is emmc device.
But with DM_MMC the mmc devices are numbered as per the dts node
enablement. If there is a chance of having enabling all mmc nodes
in dts say mmc0, mmc1, mmc2 then the default env and fastboot devices
will failed to assign proper emmc device since mmc2 is emmc in most
of the Allwinner platforms.
So, we need to alter the auto-numbering by aliasing mmc2 to mmc1 since
aliases take precedence over auto-numbering.
If the dts enables mmc0, mmc1, mmc2, then all the nodes will probe
sequentially and auto-numbered as it is. but when aliases mmc1 with mmc2
the resulting number should be that mmc0 is till mmc0, mmc2 become mmc1
and mmc2 become mmc1
Without aliases of mmc1 = &mmc2;
-------------------------------
MMC: mmc@1c0f000: 0, mmc@1c10000: 1, mmc@1c11000: 2
With aliases of mmc1 = &mmc2;
----------------------------
MMC: Device 'mmc@1c11000': seq 1 is in use by 'mmc@1c10000'
mmc@1c0f000: 0, mmc@1c10000: 2, mmc@1c11000: 1
Loading Environment from FAT... OK
Some platforms like A20 has mmc0...mmc3, but there is no usecases now
for enabling all mmc controllers in any of A20 board dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Update generation of spl binaries
- continue to generate all SPL files in spl sub-directory
- copy in root folder the needed file for user (YOCTO, buildroot):
u-boot-spl.stm32
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
When framebuffer driver init is failed, we should return the err value not 0.
So the video init can exit immediately.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The i.MX6 SOM and development kits have undergone significant
updates and changes over the past few months. This re-sync's
the U-Boot with Logic PD's BSP.
Signed-off-by: Adam Ford <aford173@gmail.com>
This patch sets up an alias for mmc0 to usdhc3.
Before the DM conversion only usdhc3 was enabled and therefore it appeared
as MMC 0 to u-boot. After enabling MMC DM though usdhc3 defaults to MMC 2,
which left unattended would drive changes to existing warp7 bootscripts and
environment variables that rely on mmc 0.
Setup the alias of mmc0 and usdhc3 so that existing warp7 boot code will
work unmodified.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch imports the Linux kernel warp7 dts as at upstream kernel commit
cf76c364a1e1.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
As pointed out by Lucas WDOD1_WDOG_ANY should be WDOG1_WDOG_ANY. Once
corrected we can import the latest kernel DTS unmodified.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reported-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Passover info only for revA.
move get_cpu_rev out of CONFIG_CPU to avoid build failure when using
get_cpu_rev in SPL.
Add a CONFIG_SPL_BUILD for passover usage, no need to execute it again
in normal U-Boot stage. Also if still checking passover info in normal
U-Boot stage, need to make the passover code executed after
arch_cpu_init_dm.
So to make it easy and clean, only execute the code for SPL stage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
According to "Table 5-1. Boot Device Select" (page 335,
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017)
the BOOT_CFG1[3] have following values (regarding EIM booting):
0 - NOR flash and 1 - ONENAND
This commit provides correct identification of the boot medium for IMX6Q
boards booting from NOR memory (MCCMON6 is one of them).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
These nodes are required by CX9020 when build with CONFIG_DM_MMC=y
They are copied from Linux 4.20
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
At default, u-boot reserves the memory from SP - 4KB to DRAM end for
lmb in arch_lmb_reserve. So lmb won't allocate any memory from it.
But we found the 4K gap for SP is not enough now, because some FDT
updating operations are added in our u-boot before jumping to kernel,
which needs larger stack. This causes the lmb allocated memory is overwritten
by stack.
Fix the issue by implementing the board_lmb_reserve to reserve from
SP - 16KB to memory end for lmb.
Signed-off-by: Ye Li <ye.li@nxp.com>
Introduce u-boot dtsi for i.MX8QXP MEK board.
we do not introduce a common dtsi for SoC, because different board
has different requirement on which needs to be enabled in SPL DM.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In preparation of adding CONFIG_DM_MMC support use separate device
trees for raw NAND and eMMC devices.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Like it was done on imx6 in commit 9236269de5 ("imx: mx6: Fix
implementantion reset_misc")
Do not call lcdif_power_down() in the SPL case to fix the following
build error:
LD spl/u-boot-spl
MKIMAGE u-boot.img
arch/arm/mach-imx/built-in.o: In function `reset_misc':
/home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down'
scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).
CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C: ready
DRAM: 256 MiB
NAND: 512 MiB
MMC: FSL_SDHC: 0
In: serial
Out: serial
Err: serial
Net: FEC0
Working:
- Eth0
- i2C
- MMC/SD
- NAND
- UART (1 & 5)
- USB (host & otg)
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
The following NXP application notes and manual recommend to ensure the
IVT DCD pointer is Null prior to calling HAB API authenticate_image()
function:
- AN12263: HABv4 RVT Guidelines and Recommendations
- AN4581: Secure Boot on i.MX50, i.MX53, i.MX 6 and i.MX7 Series using
HABv4
- CST docs: High Assurance Boot Version 4 Application Programming
Interface Reference Manual
Commit ca89df7dd4 ("imx: hab: Convert DCD non-NULL error to warning")
converted DCD non-NULL error to warning due to the lack of documentation
at the time of first patch submission. We have warned U-Boot users since
v2018.03, and it makes sense now to follow the NXP recommendation to
ensure the IVT DCD pointer is Null.
DCD commands should only be present in the initial boot image loaded by
the SoC ROM. Starting in HAB v4.3.7 the HAB code will generate an error
if a DCD pointer is present in an image being authenticated by calling the
HAB RVT API. Older versions of HAB will process and run DCD if it is
present, and this could lead to an incorrect authentication boot flow.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than
CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE. This lets us re-use the
same script for both SPL and TPL. Add logic to scripts/Makefile.spl to
pass in the right value when preprocessing the script.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Per Kever Yang, 32768 is a reasonable max size for TPL on RK3288.
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to
have an non-standard boot address in memory. This may be due
to the device being a high security variant, which place the
Initial SoftWare (ISW) after certificates and secure software.
Allow these devices to set this from Kconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
The symbol CONFIG_SPL_DFU_SUPPORT in SPL build has the same
meaning as CONFIG_DFU in regular U-Boot. Drop the _SUPPORT
to allow for cleaner use in code.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
As Poplar supports running TF-A with OP-TEE as BL32
payload, add op-tee node in DT, which enables usage of
OP-TEE driver (which provides an interface for requesting services
from OP-TEE).
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
We have converted mmc to driver model on Poplar. So let's clean up
board level mmc initialization code.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
It adds missing pinctrl headers, updates clock header and sync up Poplar
device tree with kernel 4.20 release.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Add pinctrl node for TLMM and add mux request for uart node.
* Rename uart to the actual board uart port.
* Fix indentendation of sdhc2 node.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
The TLMM_GPIO_ENABLE bit is actually use to disable
the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Add pinctrl driver for Dragonboard820c, currently with only
one mux func to initialize pins for serial console.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
The PLL for the UART was not set, and relied on previous
initializtion made by LK. add the appropriate initialization.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Deploy u-boot-spl.stm32 binary in u-boot root folder like
the rest of the boards.
This makes it more streamlined when building in Yocto, Buildroot etc..
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Most of the memory is being consumed by device binding code,
more space needed for other data structures.
Z-turn board has already hit the limit, others may follow soon.
Measuring only the memory consumed in device_bind_common, I've got
the following results (in decimal):
root_driver: 108
mod_exp_sw: 108
amba: 120
serial@e0000000 aka uart0: 112
serial@e0001000 aka uart1: 88
spi@e000d000 aka qspi: 120
sdhci@e0100000 aka mmc0: 455
sdhci@e0100000.blk: 208
slcr@f8000000: 96
clkc@100: 72
(total) 1487 = 0x5cf of 0x600
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz.
Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Similar changes was done for Zynq in past and this patch just follow
this pattern to separate cpu code from SoC code.
Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/*
And also fix references to these files.
Based on
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patches renames sd nodes in dts to be in line with
kernel. This patch also modifies the references for the same
in code.
It checks mmc first to have no time penalty for new DT node names based
on left-to-right expression evaluation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version()
but also FPGA code is calling this function which is possible to use
without actual CLK_ZYNQMP firmware driver to be enabled.
This patch enables the case where only fixed-clock CLK setup is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This is a range of stackable network switches. The SoC is Armada-385 and
there are a number of variants with differing network port
configurations. The DP variants are intended for a harsher operating
environment so they use a different i2c mux and fit industrial-temp
parts.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any
attempt to access it from U-Boot leads to an immediate crash.
So let's make the same memory reservation as the vendor device tree.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB
or 1 GiB.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
DTC issues a warning because #address-cells and #size-cells properties
are not set in the mdio node.
Also add ethernet1 alias.
Also add RTC node.
Also fix USB3 regulator startup delay time.
Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the
speed value is not used byt the comphy driver for PCI Express, but
should be 5 GHz nonetheless).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Check if Mox modules are connected in supported mode, then configure
the MDIO addresses of switch modules.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes
not taken are new compatible strings for the uart and nand flash
controller. The nand binding is best updated if/when the mtd/nand
infrastructure is updated.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
CLK and DM_RESET drivers are now available for all of
the Allwinner platforms, so enable them in arch/arm/Kconfig
Enabling CLK will select DM_RESET by default.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Update all A80 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.
arch/arm/boot/dts/sun9i-a80*:
commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date: Tue Mar 27 14:58:00 2018 +0200
Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
include/dt-bindings/*/sun9i-a80-*:
commit 783ab76ae553abc23f80ef7511052d055697531b
Author: Chen-Yu Tsai <wens@csie.org>
Date: Sat Jan 28 20:22:36 2017 +0800
clk: sunxi-ng: Add A80 Display Engine CCU
Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same
dts is not available in Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add common reset driver for all Allwinner SoC's.
Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.
Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add initial clock driver for Allwinner A64.
Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.
- add neutis-devboard target to dtb makefile
- add dtsi file for Neutis N5 needs
- add config file for Neutis N5 Dev board
Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: update proper commit head]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.
This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.
Tested with A64-SOM204 board.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Remove aliases property name warning while compilation:
Warning (alias_paths): /aliases: aliases property name must
include only lowercase and '-'
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The ICIDs for the qdma device are not configured through SCFG but
through some registers found in the actual device register block.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on
rev1.1 there is only 1 for INTx, so the current fixup is inverse
of the fact.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TFABOOT support includes:
- ls2088ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- remove EL3 specific erratas for TFABOOT
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
TFABOOT support includes:
- ls1088ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- MC address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- ifc chip select changes for TFABOOT
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Fixes for TFABOOT framework
- update eMMC bootsrc to SD_MMC
- Increase buffer size for mcinitcmd from 256 to 512
- Fix mcinitcmd and bootcmd for Secure Boot
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This fixes 'arch_lmb_reserve()' for ARM that tries to detect in which
DRAM bank 'sp' is in.
This code failed if a bank was at the end of physical address range
(i.e. size + length overflowed to 0).
To fix this, calculate 'bank_end' as 'size + length - 1' so that such
banks end at 0xffffffff, not 0.
Fixes: 15751403b6 ("ARM: bootm: don't assume sp is in DRAM bank 0")
Reported-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
This adds device tree for OMAP3 IGEP based boards and the DM_MMC driver.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add MMC nodes for HiKey board based on HI6220 SoC. There are three MMC
controllers in this SoC, first one used for eMMC, second one used
for SD card and third one is not used by u-boot.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
It enables DWC2 OTG gadget driver support for Poplar board. As
usb2_phy_init() is being always called from board_init(), we can save
the call from board_usb_init().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The SDMMC reset is missing from DT, so the reset manager cannot unreset
the SDMMC. Add the missing DT reset entry.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
OSC_27M_CLK should return 27MHz and OSC_32K_CLK should return
32768Hz to reflect the reality.
This also keeps the values in sync with the Linux clock tree.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The CPU banner printed is as following:
CPU: CPU: Freescale i.MX8QXP RevB A35 at 147228 MHz
1. Drop the CPU:
2. Change vendor from Freescale to NXP
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The current value CTLUPD_AREF(0) is the reset value of the register,
so there is no need to write a value. If needed, the register can be
written using board specific CR settings.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask
to allow setting PHYDRAM_CK_EN correctly.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter
5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed
for correct operation of DDR. Assume the default DDR pin configuration
which seems to work well on a Colibri VF50.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot.
The root cause is a cache coherence issue. When it happens, the ctrl_req in
gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev)
is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB
controller, any accessing to usb_composite_dev variable will cause the cache line refill, then
when setup transfer is completed, reading the setup data in ctrl_req will gets old value from
cache not from memory.
The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory.
so it still needs cache maintain operations before/after HW accessing. Since the cache flush or
invalidate bases on cache line, so when the allocated memory size is not cache line aligned,
potentially it may meet such issue.
This patch modifies the dma_alloc_coherent API to round the size to cache line aligned.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
There is no code for using partition labels in the Allwinner SPL port.
Even so the name is slightly misleading, CONFIG_SPL_LIBDISK_SUPPORT was
meant to guard partition code for the SPL.
Remove the "imply" line in the Kconfig to make this obvious and avoid
unneeded code inclusions, helping to keep the H6 SPL code small.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Building peach-pi smdk5420 and peach-pit with thumb mode for SPL
ends-up in the following error:
Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0'
Use an intermediate register to be able to use thumb for exynos5 SPL.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch sets VDD_LOG to 950 mV on RK3399-Q7.
This is required to address stability issues on Puma
in heavy-load use-cases.
Reported-by: Assaf Agmon <assaf@r-go.io>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch eliminates the non-standard entries "rockchip,pwm_id"
and "rockchip,pwm_voltage". They are neither documented nor
read out by any driver.
Additionally it introduces the entry regulator-init-microvolt
and sets it to 900 mV, which is the default target value
for VDD_LOG.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
All the source code of sdram_rk3036.c are from Rockchip, update the
copyright to owned by Rockchip.
Because rockchip may use this copy of code both for open source
project and internal project, update the license to use both
GPL2.0+ and BSD-3 Clause.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This is workaround for issue we can't get correct size for 4GB ram
in 32bit system and available before we really need ram space
out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
The size of 4GB is '0x1 00000000', and this value will be truncated
to 0 in 32bit system, and system can not get correct ram size.
Rockchip SoCs reserve a blob of space for peripheral near 4GB,
and we are now setting SDRAM_MAX_SIZE as max available space for
ram in 4GB, so we can use this directly to workaround the issue.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Build flash.bin for i.MX8MQ, it will include signed hdmi firmware,
spl, ddr firmware, fit image(bl31.bin, u-boot-nodtb.bin, dtb).
Burn it to 33KB offset of SD card.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Refactor dram_pll_init to accept args to configure different pll freq.
Introduce dram_enable_bypass and dram_disable_bypass
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Build u-boot-dtb.cfgout before checking files, otherwise
u-boot-dtb.cfgout is generated at late stage and cause final image not
generated.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Current implementation of hab_auth_img command needs ivt_offset to
authenticate the image. But ivt header is placed at the end of image
date after padding.
This leaves the usage of hab_auth_img command to fixed size or static
offset for ivt header. New function "get_image_ivt_offset" is introduced
to find the ivt offset during runtime. The case conditional check in this
function is same as boot_get_kernel in common/bootm.c
With this variable length image e.g. FIT image with any random size can
have IVT at the end and ivt_offset option can be left optional
Can be used as "hab_auth_img $loadaddr $filesize" from u-boot script
Signed-off-by: Parthiban Nallathambi <pn@denx.de>
Reviewed-by: Breno Lima <breno.lima@nxp.com>
This file is in sync with v4.20-next tree:
e4dda4f5a4df "x86/kaslr, ACPI/NUMA: avoid including asm/kaslr.h on arm64"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This node is in sync with v4.20-next tree:
e4dda4f5a4df "x86/kaslr, ACPI/NUMA: avoid including asm/kaslr.h on arm64"
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Introduce two board level callback functions to FIT image loading process, and
a SPL_FIT_FOUND flag to differentiate FIT image or RAW image.
Implement functions in imx common SPL codes to call HAB funtion
to authenticate the FIT image. Generally, we have to sign multiple regions
in FIT image:
1. Sign FIT FDT data (configuration)
2. Sign FIT external data (Sub-images)
Because the CSF supports to sign multiple memory blocks, so that we can use one
signature to cover all regions in FIT image and only authenticate once.
The authentication should be done after the entire FIT image is loaded into
memory including all sub-images.
We use "-p" option to generate FIT image to reserve a space for FIT IVT
and FIT CSF, also this help to fix the offset of the external data (u-boot-nodtb.bin,
ATF, u-boot DTB).
The signed FIT image layout is as below:
--------------------------------------------------
| | | | | | | |
| FIT | FIT | FIT | | U-BOOT | ATF | U-BOOT |
| FDT | IVT | CSF | | nodtb.bin | | DTB |
| | | | | | | |
--------------------------------------------------
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Using ulong is wrong as its size depends on the Host CPU architecture
(32-bit vs. 64-bit) although the Cortex-M4 is always 32-bit.
Without this patch, the stack and PC are obviously wrong and it
generates an abort when used on 64-bit processors such as the i.MX8MQ.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Otherwise can't boot the M4 core as it is impossible to load its
firmware into the TCM memory.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add Kconfig option WATCHDOG_RESET_DISABLE to disable watchdog reset
in imx_watchdog driver, so that the watchdog will not be fed in
u-boot if CONFIG_WATCHDOG_RESET_DISABLE is enabled.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Support watchdog driver for fsl-lsch2. It's disabled in default.
If you want to use it, please enable CONFIG_IMX_WATCHDOG.
Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Currently, the DWC3 USB node is out of sync because the bindings
for the UniPhier DWC3 PHY diverged between Linux and U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Some users might want to modify 'bootcmd' at compile-time by editing
include/configs/uniphier.h, but overwriting it at run-time makes it
impossible.
Instead, set 'bootdev' at run-time, which contains the boot device the
system is booting from, then indirectly reference it from 'bootcmd'.
It is up to users whether to override 'bootcmd'.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch changes mt7629 to use the compatible platform SMP initialization
method of linux kernel.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
For signing the tiboot3.bin image, an optional KEY file can be passed
using CONFIG_SYS_K3_KEY. Right now, Makefile scripts directly takes
the config value and uses it for signing. This is okay if the build
directory is a sub-directory of source tree, otherwise it fails.
Fix it by using the path relative to the source tree.
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
OMAP3_GPIO_x is needed to enable each GPIO bank on the OMAP3
boards. At one point, the #ifdef's were replaced with
if CONFIG_IS_ENABLED but this won't work for people who need
OMAP3_GPIO_x in SPL since the SPL prefix for this option isn't
used in Kconfig. This patch moves the check to #if defined and
also makes Kconfig select the banks if CMD_GPIO is used which
makes the checks in the code less cumbersome.
Fixes: bd8a9c14c9 ("arm: mach-omap2/omap3/clock.c: Enable
all GPIO with CMD_GPIO")
Reported-by: Liam O'Shaughnessy <liam.o.shaughnessy@gumstix.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Migrate omap3_igep00x0.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch allows smaller binaries.
This is needed for and has been tested on Arndale board, as u-boot.bin is
now bigger than the 512K load limit, with GCC8, without thumb mode.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The Marvell DDR3 training code is now part of the U-Boot SPL so the
comment saying it needs porting is no longer correct.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Add a generic mailbox API for FPGA reconfig status which can be
called by others. This new function accepts 2 different mailbox
commands: CONFIG_STATUS or RECONFIG_STATUS.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Under U-boot, the WiFi SDIO Module should be disabled and the
eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
include file specific for U-Boot that will be included by the build system.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Add the initial support for Elgin R1 board, which is based on the
RV1108 SoC and has the following features currently supported in
U-Boot:
- UART
- eMMC
- USB
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This is a sync with kernel mainline dts.
The U-Boot eMMC does not need to care about the power for Rockchip
SoCs, because if the board is using eMMC, the power will default on
(for bootrom), so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
vcc5v0_host and usbhub_enable share gpio4 RK_PA3,
which is a problem during probing (the second probe
will trigger a -EBUSY, when trying to get the gpio handle).
An analysis of the situation shows, that both regulators
are actually describing the same supply.
This patch removes the (currenlty not successful probing)
regulator vcc5v0_host from the DTS and adds the pinctrl-*
setting to usbhub_enable.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Phiilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Commit 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x
driver for Poplar platform, because the platform falls into the
following strategy category made by the commit.
Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Before the commit lands, Poplar platform works by statically declaring
pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set
in the driver. But since Poplar also supports device configuration from
device tree, the commit practically drops the flag for Poplar, and hence
breaks the platform from booting.
This patch changes platform code and device tree to initiate pl011
serial device from device tree rather than static declaration, so that
above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore
the reported boot failure gets fixed.
Reported-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers")
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When DM_USB is used, either the USB controllers are bound when the DTB
is parsed (when OF_CONTROL is enabled) or they are bound using the
U_BOOT_DEVICES() macro.
In the later case, the platform data is passed in a struct ti_musb_platdata
because it cannot be read from the DTB.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable DM for USB peripheral in the musb-new driver.
Also make sure that the driver can be used in the SPL.
This implies that:
* the driver must work with and without the OF_CONTROL option. That
in turn, implies that the platform data can be passed in a struct
ti_musb_platdata or be read from the dtb
* usb.o is linked in the SPL if host support is enabled
Another change is that the driver does not fail to bind (and stop the boot
process) if one of the child driver does not bind. Reporting the error is
enough. This kind of error would appear if the port is configured in the
DTS but the driver is not activated in the config.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
USB1 can be used by the romboot on all am4372 platforms to download a
firmware (SPL in our case).
It makes sense to enable USB1 in the SPL to download u-boot.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This file is used to override the values found in am4372.dtsi
Use it to fix the "compatible" options for the controllers used
to support the USB (parent bus and syscons).
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update snow's device tree and config to use driver model for sound. Also
update the others as best we can.
Spring does not appear to have audio support in the kernel. The smdk5250
and smdk5420 boards use a wolfson codec which I cannot test with. So the
only boards that is tested and known to work are snow, pit and pi.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow setting the i2s pinmux correctly on exyno5420 so that i2c can be
used on that SoC. Also rename EXYNOS_AUDSS to something consistent with
other naming.
Signed-off-by: Simon Glass <sjg@chromium.org>
For snow the codec is at address 0x11 on the i2c bus, in 7-bit format.
The device tree and code are in 8-bit format (i.e. shifted left one bit).
Fix both. Fix pit in a similar way.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no need for an embedded device tree for this board so let the
build process generate a separate u-boot.dtb file instead.
Signed-off-by: Felix Brack <fb@ltec.ch>
Add support for lx2160a SoC
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlwOzFoACgkQ7UVZlNoL
nbQUdQ//SRRBfjUe8RYTbojvTGQav0GTxnMkz4GFSrqu0nvGMW2YSlheOMqq72sg
rK5mQqDvdkItCn+G8AZ5NV2ijkQ7NQWCfqL3EtApzTpv6qjfgv7xvopz8q4NZvzB
Wp+4cFf9YQjNwhJ7kLvWHB7SBiz9AfMYRAj9cscH9xsGL3HxPj62WDfwyK/QXana
KIxRKQ26/1AdOZy272yv70vlFj4IwForxV3ACimsWRuYcb8yre3pE0tD7XpMCSNv
9GOfL7r4LS7U0+QnJoVeYLMhttRvOGJNUYtO2+ImO5NC3u9v8ehYEQ3FjGmM69CB
vuPDQBDQc+Ap+Iu3k18PYSstp+mc9fbe9SQdlx6ARAecQqWTN4EOhf8s3m2bQq3S
B58I0Zvowcdm8V2JKdXw94UqZX862U8PWH0BmcuX+4k+kRDwwU4XQY2nLp+Htz1w
2q6vEdKGj7YUOaomx9fmKRL+9BFGoD+M9mTiHOwzqwxy6Pa9VkruSvMErM7p2l/z
xI/Q+xPJhyk5TXgZRsz4Nat59WpifWruibKEd4PArQ446heHWmzLWjw/MWiFyd/H
agCdpDZVJ8R7h1Krs+Ez8XjR1Qcg0gs+CdNBuvqxzOpMQGGonXA1nwi8YfHykhII
urfoC8pew1yxiLGw7J2JSX808HV/09WCSEsrOOhE3T78rXTDlS4=
=aT7d
-----END PGP SIGNATURE-----
Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq
Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
- init DRAM for RK322x in SPL
- add FAN53555 PMIC/regulator driver
- update MicroCrystal RV3029 driver to Kconfig and sync from Linux
- add bootcount uclass and first DM-driver for bootcount
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcDiw9AAoJECaAFcEOcohNEa8H/RBWLbVQjHPXf6EjchXgVcSs
Gc+g2QmKZbN21XebfzBpCuZj62NROTWUcrPtor17yEBiMM1xPfe1vC7qtbkR6USj
VTt1JHeyGx3XafkkUpeps382YPfuaNqtabjwZaXlmeE4/VLbXQPE7x4tC4fdWus4
9K3OGQgRNFirn+RIZ7dQWtCby82PEC3cHkPc/n82cVHofcDsgKYK9mPpfcCn/gWF
A4Fa9cx4pjeaMrBHKjcByCiFmwYBPc97Hqzz64oHOdQP0g3h04ko+2w5DdwdeHVV
jKNcvkHESF4m1RGjrTbLEhy1f5UuOfcA1ise/cDX4pjXlBdwxHmvqT5vsE0MQzI=
=5sHL
-----END PGP SIGNATURE-----
Merge tag 'for-master-20181210' of git://git.denx.de/u-boot-rockchip
Improvements:
- init DRAM for RK322x in SPL
- add FAN53555 PMIC/regulator driver
- update MicroCrystal RV3029 driver to Kconfig and sync from Linux
- add bootcount uclass and first DM-driver for bootcount
Now that we have FAN53555 support, we can enable the regulators in our
DTS. To make these easier to identify on the U-Boot commandline, we
rename them to the names of the voltage rails they control.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The DRA7 platforms requires that the dtb used in the SPL really matches the
platform to have the best MMC performances.
To detect the board type/version an I2C EEPROM is read. This requires that
DM is initialized before the detection. As a consequence we must reset the
DM after the board detection is a new dtb would better match the platform.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT
when all I2C "clients" have been migrated to use the DM API.
This a step in that direction for the TI based platforms.
Build tested with buildman:
buildman -dle am33xx ti omap3 omap4 omap5 davinci keystone
boot tested with:
am335x_evm, am335x_boneblack, am335x_boneblack_vboot (DM version),
am57xx_evm, dra7xx_evm, k2g_evm, am437x_evm
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
In order to use DM_I2C, we need to move the board detection after the
early SPL initialization.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE
because OF_CONTROL is not used in the SPL.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This allows the driver to be used without OF_CONTROL.
AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
SPL thus requires that the omap I2C can be passed platdata.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Move away from SoC specific headers to handle different register layout.
Instead use driver data to get appropriate register layouts like in the
kernel. While at it, perform some mostly cosmetic alignment/cleanup in
the functions being updated.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Similar to Clearfog rev 2.1, GPIO 19 also used to reset onboard ethernet
PHY.
This patch depend on
net: mvneta: Add GPIO configuration support
[URL: https://patchwork.ozlabs.org/patch/1007736/]
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable SPI flash support under U-Boot and SPL. The ENV size and offset,
ported from U-Boot 2013.01 Marvell version: 2015_T1.0p16
To create U-Boot image for SPI flash, user would need to replace
* CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC with CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
* CONFIG_ENV_IS_IN_MMC with CONFIG_ENV_IS_IN_SPI_FLASH
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable Marvell I2C driver and I2C IO expander. Set default bus to
external I2C bus. Define I2C aliases in device tree so it can be
recognized by the driver.
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
For a small SPL, it should be possible to build without SPI(-flash) drivers
or wihout MMC drivers.
For this to work, we have to change from 'select'ing options to 'imply'ing
them.
With this change, I can have SPL trimmed to my hard-wired starting method
(SPI-NOR or MMC) while still including all drivers in U-Boot.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This is required when DM_USB is used, to bind the USB phys.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not
for device.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
This patch fixes the problem that u-boot will not start unless icache is
enabled early.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch fixes the problem that "main memory domain AXI secure access
protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF)
set by DBSC from the map area.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch fixes the problem that "main memory domain AXI secure
access protection error" occurs when booting Cortex-A53. Exclude
the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch synchronizes the am33xx SoC specific files with those from
Linux 4.20.0. Hence all board maintainers of am33xx based boards are
on the cc list.
The main purpose of this patch is to prevent further diverging of the
dts files from U-Boot and those from Linux. It aims to set the stage
for the synchronization of board specific dts files. Example: I'm the
maintainer of the PDU001 board: once this patch is applied successfully
I will make changes to the board specific dts file in Linux only and
then post a patch with a copy of this exact dts file to U-Boot. This
will make U-Boot and Linux remain in sync.
The stumbling block of https://patchwork.ozlabs.org/patch/943627 was
removed by the patch https://patchwork.ozlabs.org/patch/962428 from
Lokesh Vutla (many thanks!). This omap-serial driver allows using the
Linux am33xx.dtsi file in U-Boot.
Other changes to dts and dtsi files made by this patch are mainly to
prevent _new_ warnings during the build process. Especially the warning
at pinmux@800 stating 'unnecessary #address-cells/#size-cells without
"ranges" or child "reg"' was not removed. This warning is a good example
showing the benefit of the synchronization: if it needs to be fixed it
will be fixed in Linux and ported back to U-Boot.
Buildman reports all 46 am33xx SoC based boards to build fine, with
warnings of course. Nevertheless this patch should be tested thoroughly
on as many boards as possible to prevent any collateral damage.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
