brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

imx: add i.MX8MQ EVK support

Browse Source 
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.

The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE:  BL31: Built : 09:28:54, Nov  8 2018
lpddr4 swffc start
NOTICE:  sip svc init

U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)

CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2018-11-20 10:20:00 +00:00 committed by Stefano Babic
parent e3963c0943
commit 86ac7a9a5d
13 changed files with 3671 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/Makefile
View File

@ -465,6 +465,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb-u-boot.dtb \
r8a7795-salvator-x-u-boot.dtb \

414
arch/arm/dts/fsl-imx8mq-evk.dts Normal file
View File

@ -0,0 +1,414 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;
#include "fsl-imx8mq.dtsi"
/ {
model = "Freescale i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
chosen {
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
pwmleds {
compatible = "pwm-leds";
ledpwm2 {
label = "PWM2";
pwms = <&pwm2 0 50000>;
max-brightness = <255>;
};
};
};
&iomuxc {
pinctrl-names = "default";
imx8mq-evk {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&lcdif {
status = "okay";
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
display0: display@0 {
bits-per-pixel = <24>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash0: n25q256a@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

13
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -7,4 +7,17 @@ config IMX8M
config SYS_SOC
default "imx8m"
choice
prompt "NXP i.MX8M board select"
optional
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
select IMX8M
select IMX8M_LPDDR4
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
endif

12
board/freescale/imx8mq_evk/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_IMX8MQ_EVK
config SYS_BOARD
default "imx8mq_evk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx8mq_evk"
endif

6
board/freescale/imx8mq_evk/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
i.MX8MQ EVK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx8mq_evk/
F: include/configs/imx8mq_evk.h
F: configs/imx8mq_evk_defconfig

12
board/freescale/imx8mq_evk/Makefile Normal file
View File

@ -0,0 +1,12 @@
#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mq_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
endif

36
board/freescale/imx8mq_evk/README Normal file
View File

@ -0,0 +1,36 @@
U-Boot for the NXP i.MX8MQ EVK board
Quick Start
====================
- Build the ARM Trusted firmware binary
- Get ddr and hdmi fimware
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
====================
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
branch: imx_4.14.62_1.0.0_beta
$ make PLAT=imx8mq bl31
Get the ddr and hdmi firmware
====================
Note: srctree is U-Boot source directory
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
$ chmod +x firmware-imx-7.9.bin
$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
Build U-Boot
====================
$ export ARCH=arm64
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8mq_evk_defconfig
$ make flash.bin
Burn the flash.bin to MicroSD card offset 33KB
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
Boot
====================
Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.

130
board/freescale/imx8mq_evk/imx8mq_evk.c Normal file
View File

@ -0,0 +1,130 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <spl.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "EVK");
env_set("board_rev", "iMX8MQ");
#endif
return 0;
}

1320
board/freescale/imx8mq_evk/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

1191
board/freescale/imx8mq_evk/lpddr4_timing_b0.c Normal file
View File

File diff suppressed because it is too large Load Diff

246
board/freescale/imx8mq_evk/spl.c Normal file
View File

@ -0,0 +1,246 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <spl.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
extern struct dram_timing_info dram_timing_b0;
void spl_dram_init(void)
{
/* ddr init */
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
ddr_init(&dram_timing);
else
ddr_init(&dram_timing_b0);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
return 1;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#ifdef CONFIG_POWER
#define I2C_PMIC 0
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
}
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
return 0;
}
#endif
void spl_board_init(void)
{
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
/* Adjust pmic voltage to 1.0V for 800M */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

37
configs/imx8mq_evk_defconfig Normal file
View File

@ -0,0 +1,37 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_IMX8MQ_EVK=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
CONFIG_OF_LIST="fsl-imx8mq-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
#CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y
CONFIG_FS_FAT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000

252
include/configs/imx8mq_evk.h Normal file
View File

@ -0,0 +1,252 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __IMX8M_EVK_H
#define __IMX8M_EVK_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
#endif
#define CONFIG_SPL_TEXT_BASE 0x7E1000
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
#undef CONFIG_DM_PMIC
#undef CONFIG_DM_PMIC_PFUZE100
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#endif
#define CONFIG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
"rdinit=/linuxrc " \
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
"g_mass_storage.iSerialNumber=\"\" "\
"clk_ignore_unused "\
"\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffff\0" \
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image\0" \
"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8mq-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"echo wait for boot; " \
"fi;\0" \
"netargs=setenv bootargs console=${console} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"booti; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
#define CONFIG_LOADADDR 0x40480000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_SIZE >> 1))
#define CONFIG_BAUDRATE 115200
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "u-boot=> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_IMX_BOOTAUX
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE
/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_OF_SYSTEM_SETUP
#ifndef CONFIG_SPL_BUILD
#define CONFIG_DM_PMIC
#endif
#endif