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u-boot-imx-2019-02-16

Browse Source 
---------------------
 
 - vhybrid: add calibration
 - gw_ventana: fixes
 - Improve documentation for Secure Boot (HABv4)
 - Fix Marvell Switch
 - MX6 Sabre, switch to DM
 - Fixes for NAND
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Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imx

u-boot-imx-2019-02-16
---------------------

- vhybrid: add calibration
- gw_ventana: fixes
- Improve documentation for Secure Boot (HABv4)
- Fix Marvell Switch
- MX6 Sabre, switch to DM
- Fixes for NAND
This commit is contained in:
Tom Rini 2019-02-16 08:31:05 -05:00
commit b89074f650
70 changed files with 5154 additions and 768 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/dts/Makefile
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@ -450,7 +450,13 @@ dtb-$(CONFIG_MX6QDL) += \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb
imx6q-logicpd.dtb \
imx6q-sabreauto.dtb \
imx6q-sabresd.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb
dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
@ -467,6 +473,8 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-opos6uldev.dtb \
imx6ul-14x14-evk.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-liteboard.dtb \
imx6ul-phycore-segin.dtb
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb

6
arch/arm/dts/imx6dl-sabreauto-u-boot.dtsi Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabreauto-u-boot.dtsi"

13
arch/arm/dts/imx6dl-sabreauto.dts Normal file
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@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-sabreauto.dtsi"
/ {
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
};

6
arch/arm/dts/imx6dl-sabresd-u-boot.dtsi Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabresd-u-boot.dtsi"

18
arch/arm/dts/imx6dl-sabresd.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-sabresd.dtsi"
/ {
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
&ipu1_csi1_from_ipu1_csi1_mux {
clock-lanes = <0>;
data-lanes = <1 2>;
};

306
arch/arm/dts/imx6dl.dtsi
View File

@ -1,12 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
@ -39,6 +33,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@ -56,39 +51,57 @@
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
};
soc {
ocram: sram@00900000 {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
aips1: aips-bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@020f0000 {
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
};
epdc: epdc@020f4000 {
epdc: epdc@20f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 {
aips2: aips-bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
@ -100,14 +113,177 @@
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu1_csi0>, <&ipu1_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
};
};
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
&gpio1 {
gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
<&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
<&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
<&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
<&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
<&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
};
&gpio2 {
gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
<&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
<&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
<&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
<&iomuxc 28 113 4>;
};
&gpio3 {
gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
<&iomuxc 16 81 16>;
};
&gpio4 {
gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
<&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
<&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
<&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
<&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
};
&gpio5 {
gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
<&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
<&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
<&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
};
&gpio6 {
gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
<&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
<&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
<&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
<&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
<&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
};
&gpio7 {
gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
<&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
};
&gpr {
ipu1_csi0_mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi0_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi0_mux_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
};
};
port@2 {
reg = <2>;
ipu1_csi0_mux_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
};
};
port@3 {
reg = <3>;
ipu1_csi0_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
};
};
port@4 {
reg = <4>;
ipu1_csi0_mux_from_parallel_sensor: endpoint {
};
};
port@5 {
reg = <5>;
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
};
};
};
ipu1_csi1_mux {
compatible = "video-mux";
mux-controls = <&mux 1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi1_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi1_mux_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
};
};
port@2 {
reg = <2>;
ipu1_csi1_mux_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
};
};
port@3 {
reg = <3>;
ipu1_csi1_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
};
};
port@4 {
reg = <4>;
ipu1_csi1_mux_from_parallel_sensor: endpoint {
};
};
port@5 {
reg = <5>;
ipu1_csi1_mux_to_ipu1_csi1: endpoint {
remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
};
};
};
};
@ -119,6 +295,12 @@
compatible = "fsl,imx6dl-hdmi";
};
&ipu1_csi1 {
ipu1_csi1_from_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@ -128,6 +310,82 @@
"di0", "di1";
};
&mipi_csi {
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
};
mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
};
};
port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
};
mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
};
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
};
mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
};
};
port@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
reg = <0>;
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
};
mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
};
};
};
&mux {
mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
<0x34 0x00000038>, /* IPU_CSI1_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};

6
arch/arm/dts/imx6q-sabreauto-u-boot.dtsi Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabreauto-u-boot.dtsi"

18
arch/arm/dts/imx6q-sabreauto.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-sabreauto.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Automotive Board";
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
};
&sata {
status = "okay";
};

6
arch/arm/dts/imx6q-sabresd-u-boot.dtsi Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabresd-u-boot.dtsi"

23
arch/arm/dts/imx6q-sabresd.dts Normal file
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@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-sabresd.dtsi"
/ {
model = "Freescale i.MX6 Quad SABRE Smart Device Board";
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
};
&sata {
status = "okay";
};
&ipu1_csi1_from_mipi_vc1 {
clock-lanes = <0>;
data-lanes = <1 2>;
};

314
arch/arm/dts/imx6q.dtsi
View File

@ -1,12 +1,6 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
@ -44,6 +38,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@ -56,38 +51,119 @@
soc-supply = <&reg_soc>;
};
cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@2 {
cpu2: cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@3 {
cpu3: cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
};
soc {
ocram: sram@00900000 {
ocram: sram@900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi5: ecspi@02018000 {
aips-bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@ -96,18 +172,18 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
dma-names = "rx", "tx";
status = "disabled";
};
};
iomuxc: iomuxc@020e0000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6q-iomuxc";
};
};
sata: sata@02200000 {
sata: sata@2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
@ -118,17 +194,17 @@
status = "disabled";
};
gpu_vg: gpu@02204000 {
gpu_vg: gpu@2204000 {
compatible = "vivante,gc";
reg = <0x02204000 0x4000>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&gpc 1>;
power-domains = <&pd_pu>;
};
ipu2: ipu@02800000 {
ipu2: ipu@2800000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ipu";
@ -143,69 +219,181 @@
ipu2_csi0: port@0 {
reg = <0>;
ipu2_csi0_from_mipi_vc2: endpoint {
remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
};
};
ipu2_csi1: port@1 {
reg = <1>;
ipu2_csi1_from_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
};
};
ipu2_di0: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
ipu2_di0_disp0: disp0-endpoint {
ipu2_di0_disp0: endpoint@0 {
reg = <0>;
};
ipu2_di0_hdmi: hdmi-endpoint {
ipu2_di0_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_mux_2>;
};
ipu2_di0_mipi: mipi-endpoint {
ipu2_di0_mipi: endpoint@2 {
reg = <2>;
remote-endpoint = <&mipi_mux_2>;
};
ipu2_di0_lvds0: lvds0-endpoint {
ipu2_di0_lvds0: endpoint@3 {
reg = <3>;
remote-endpoint = <&lvds0_mux_2>;
};
ipu2_di0_lvds1: lvds1-endpoint {
ipu2_di0_lvds1: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds1_mux_2>;
};
};
ipu2_di1: port@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
ipu2_di1_hdmi: hdmi-endpoint {
ipu2_di1_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_mux_3>;
};
ipu2_di1_mipi: mipi-endpoint {
ipu2_di1_mipi: endpoint@2 {
reg = <2>;
remote-endpoint = <&mipi_mux_3>;
};
ipu2_di1_lvds0: lvds0-endpoint {
ipu2_di1_lvds0: endpoint@3 {
reg = <3>;
remote-endpoint = <&lvds0_mux_3>;
};
ipu2_di1_lvds1: lvds1-endpoint {
ipu2_di1_lvds1: endpoint@4 {
reg = <4>;
remote-endpoint = <&lvds1_mux_3>;
};
};
};
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
};
};
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
&gpio1 {
gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
<&iomuxc 22 116 10>;
};
&gpio2 {
gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
<&iomuxc 31 44 1>;
};
&gpio3 {
gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
};
&gpio4 {
gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
};
&gpio5 {
gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
};
&gpio6 {
gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
<&iomuxc 31 86 1>;
};
&gpio7 {
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
};
&gpr {
ipu1_csi0_mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu1_csi0_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
};
};
port@1 {
reg = <1>;
ipu1_csi0_mux_from_parallel_sensor: endpoint {
};
};
port@2 {
reg = <2>;
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
};
};
};
ipu2_csi1_mux {
compatible = "video-mux";
mux-controls = <&mux 1>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ipu2_csi1_mux_from_mipi_vc3: endpoint {
remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
};
};
port@1 {
reg = <1>;
ipu2_csi1_mux_from_parallel_sensor: endpoint {
};
};
port@2 {
reg = <2>;
ipu2_csi1_mux_to_ipu2_csi1: endpoint {
remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
};
};
};
};
@ -229,6 +417,12 @@
};
};
&ipu1_csi1 {
ipu1_csi1_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
};
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@ -275,6 +469,40 @@
};
};
&mipi_csi {
port@1 {
reg = <1>;
mipi_vc0_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
};
};
port@2 {
reg = <2>;
mipi_vc1_to_ipu1_csi1: endpoint {
remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
};
};
port@3 {
reg = <3>;
mipi_vc2_to_ipu2_csi0: endpoint {
remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
};
};
port@4 {
reg = <4>;
mipi_vc3_to_ipu2_csi1_mux: endpoint {
remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
};
};
};
&mipi_dsi {
ports {
port@2 {
@ -295,6 +523,16 @@
};
};
&mux {
mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
<0x04 0x00100000>, /* MIPI_IPU2_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};

21
arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-u-boot.dtsi"
/ {
aliases {
mmc0 = &usdhc3;
};
};
&usdhc3 {
no-1-8-v;
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};

810
arch/arm/dts/imx6qdl-sabreauto.dtsi Normal file
View File

@ -0,0 +1,810 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = &uart4;
};
memory@10000000 {
reg = <0x10000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
user {
label = "debug";
gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
home {
label = "Home";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
wakeup-source;
};
back {
label = "Back";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
wakeup-source;
};
program {
label = "Program";
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROGRAM>;
wakeup-source;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};
clocks {
codec_osc: anaclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_audio: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound-cs42888 {
compatible = "fsl,imx6-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
audio-cpu = <&esai>;
audio-asrc = <&asrc>;
audio-codec = <&codec>;
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "Line In Jack",
"AIN1R", "Line In Jack",
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
};
sound-spdif {
compatible = "fsl,imx-audio-spdif",
"fsl,imx-sabreauto-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-in;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
status = "okay";
};
i2cmux {
compatible = "i2c-mux-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3mux>;
mux-gpios = <&gpio5 4 0>;
i2c-parent = <&i2c3>;
idle-state = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7180: camera@21 {
compatible = "adi,adv7180";
reg = <0x21>;
powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
port {
adv7180_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
};
};
};
max7310_a: gpio@30 {
compatible = "maxim,max7310";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_b: gpio@32 {
compatible = "maxim,max7310";
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_max7310>;
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
max7310_c: gpio@34 {
compatible = "maxim,max7310";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
light-sensor@44 {
compatible = "isil,isl29023";
reg = <0x44>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
};
magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
interrupt-parent = <&gpio2>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
};
accelerometer@1c {
compatible = "fsl,mma8451";
reg = <0x1c>;
interrupt-parent = <&gpio6>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&clks {
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_PLL4_BYPASS>,
<&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
<&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
};
&ecspi1 {
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&esai {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai>;
assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
<&clks IMX6QDL_CLK_ESAI_EXTAL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
codec: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&codec_osc>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
};
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_egalax_int>;
interrupt-parent = <&gpio2>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-sabreauto {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_ecspi1_cs: ecspi1cs {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
>;
};
pinctrl_egalax_int: egalax-intgrp {
fsl,pins = <
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_esai: esaigrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_i2c3mux: i2c3muxgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_max7310: max7310grp {
fsl,pins = <
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_gpt_input_capture0: gptinputcapture0grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
>;
};
pinctrl_gpt_input_capture1: gptinputcapture1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
>;
};
pinctrl_weim_cs0: weimcs0grp {
fsl,pins = <
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor: weimnorgrp {
fsl,pins = <
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};

14
arch/arm/dts/imx6qdl-sabresd-u-boot.dtsi Normal file
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@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-u-boot.dtsi"
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
mmc1 = &usdhc3;
};
chosen {
stdout-path = &uart1;
};
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 29 0>;
enable-active-high;
vin-supply = <&swbst_reg>;
};
reg_audio: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 0>;
enable-active-high;
};
reg_pcie: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 19 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_POWER>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
status = "okay";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
red {
gpios = <&gpio1 2 0>;
default-state = "on";
};
};
panel {
compatible = "hannstar,hsd100pxn1";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
data-shift = <12>; /* Lines 19:12 used */
hsync-active = <1>;
vsync-active = <1>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ecspi1 {
cs-gpios = <&gpio4 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5642>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
reg = <0x3c>;
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
status = "disabled";
port {
ov5642_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
port {
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio6>;
interrupts = <7 2>;
wakeup-gpios = <&gpio6 7 0>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-sabresd {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
>;
};
pinctrl_ov5642: ov5642grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
pinctrl_pcie_reg: pciereggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
>;
};
};
gpio_leds {
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&reg_arm {
vin-supply = <&sw1a_reg>;
};
&reg_pu {
vin-supply = <&sw1c_reg>;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
};
&snvs_poweroff {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
no-1-8-v;
status = "okay";
};
&wdog1 {
status = "disabled";
};
&wdog2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

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arch/arm/dts/imx6qdl-u-boot.dtsi
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@ -7,11 +7,11 @@
soc {
u-boot,dm-spl;
aips-bus@02000000 {
aips-bus@2000000 {
u-boot,dm-spl;
};
aips-bus@02100000 {
aips-bus@2100000 {
u-boot,dm-spl;
};
};

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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabreauto-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2016 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-sabreauto.dtsi"
/ {
model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
};
&i2c2 {
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
imx6qdl-sabreauto {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
};
};
&pcie {
status = "disabled";
};
&vgen3_reg {
regulator-always-on;
};

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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 NXP
*/
#include "imx6qdl-sabresd-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2016 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-sabresd.dtsi"
/ {
model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
};
&reg_arm {
vin-supply = <&sw2_reg>;
};
&iomuxc {
imx6qdl-sabresd {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
};
&pcie {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2016 Freescale Semiconductor, Inc.
#include "imx6q.dtsi"
/ {
soc {
ocram2: sram@940000 {
compatible = "mmio-sram";
reg = <0x00940000 0x20000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
ocram3: sram@960000 {
compatible = "mmio-sram";
reg = <0x00960000 0x20000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE0>;
clock-names = "axi";
fsl,iram = <&ocram2>;
};
pre2: pre@21c9000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c9000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE1>;
clock-names = "axi";
fsl,iram = <&ocram2>;
};
pre3: pre@21ca000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021ca000 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE2>;
clock-names = "axi";
fsl,iram = <&ocram3>;
};
pre4: pre@21cb000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021cb000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
clocks = <&clks IMX6QDL_CLK_PRE3>;
clock-names = "axi";
fsl,iram = <&ocram3>;
};
prg1: prg@21cc000 {
compatible = "fsl,imx6qp-prg";
reg = <0x021cc000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
<&clks IMX6QDL_CLK_PRG0_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
};
prg2: prg@21cd000 {
compatible = "fsl,imx6qp-prg";
reg = <0x021cd000 0x1000>;
clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
<&clks IMX6QDL_CLK_PRG1_AXI>;
clock-names = "ipg", "axi";
fsl,pres = <&pre4>, <&pre2>, <&pre3>;
};
};
};
};
&fec {
/delete-property/interrupts-extended;
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
<0 119 IRQ_TYPE_LEVEL_HIGH>;
};
&gpc {
compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
};
&ipu1 {
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
fsl,prg = <&prg1>;
};
&ipu2 {
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
fsl,prg = <&prg2>;
};
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
"di0", "di1";
};
&mmdc0 {
compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
};
&pcie {
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
};

151
arch/arm/dts/imx6ul-liteboard.dts Normal file
View File

@ -0,0 +1,151 @@
/*
* Copyright 2016 Grinn
*
* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul-litesom.dtsi"
/ {
model = "Grinn i.MX6UL liteBoard";
compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
"fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usb_otg1_vbus: usb-otg1-vbus {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x79
>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&snvs_poweroff {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

82
arch/arm/dts/imx6ul-litesom.dtsi Normal file
View File

@ -0,0 +1,82 @@
/*
* Copyright 2016 Grinn
*
* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6ul.dtsi"
/ {
model = "Grinn i.MX6UL liteSOM";
compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059
>;
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
bus-width = <8>;
status = "okay";
};

2
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -62,7 +62,7 @@
#define BOOT_DEVICE_CPGMAC 0x47
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#ifdef CONFIG_SPL_USB_SUPPORT
#ifdef CONFIG_SPL_USB_STORAGE
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_USB
#else
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2

14
arch/arm/include/asm/arch-vf610/imx-regs.h
View File

@ -207,15 +207,27 @@
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
#define DDRMC_CR93_SW_LVL_MODE_OFF (8)
#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF)
#define DDRMC_CR93_SWLVL_LOAD BIT(16)
#define DDRMC_CR93_SWLVL_START BIT(24)
#define DDRMC_CR94_SWLVL_EXIT BIT(0)
#define DDRMC_CR94_SWLVL_OP_DONE BIT(8)
#define DDRMC_CR94_SWLVL_RESP_0_OFF (24)
#define DDRMC_CR95_SWLVL_RESP_1_OFF (0)
#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
#define DDRMC_CR97_WRLVL_EN (1 << 24)
#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff)
#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff)
#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF (24)
#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF)
#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16)
#define DDRMC_CR102_RDLVL_REG_EN (1 << 8)
#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
#define DDRMC_CR105_RDLVL_DL_0_OFF (8)
#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF)
#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff)
#define DDRMC_CR110_RDLVL_DL_1_OFF (0)
#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16)
#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)

12
arch/arm/mach-imx/Kconfig
View File

@ -78,3 +78,15 @@ config NXP_BOARD_REVISION
NXP boards based on i.MX6/7 contain the board revision information
stored in the fuses. Select this option if you want to be able to
retrieve the board revision information.
config DDRMC_VF610_CALIBRATION
bool "Enable DDRMC (DDR3) on-chip calibration"
depends on ARCH_VF610
help
Vybrid (vf610) SoC provides some on-chip facility to tune the DDR3
memory parameters. Select this option if you want to calculate them
at boot time.
NOTE:
NXP does NOT recommend to perform this calibration at each boot. One
shall perform it on a new PCB and then use those values to program
the ddrmc_cr_setting on relevant board file.

1
arch/arm/mach-imx/Makefile
View File

@ -53,6 +53,7 @@ obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
endif
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o

27
arch/arm/mach-imx/cpu.c
View File

@ -25,19 +25,27 @@
#include <fsl_esdhc.h>
#endif
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
static u32 reset_cause = -1;
static char *get_reset_cause(void)
u32 get_imx_reset_cause(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
reset_cause = cause;
if (reset_cause == -1) {
reset_cause = readl(&src_regs->srsr);
/* preserve the value for U-Boot proper */
#if !defined(CONFIG_SPL_BUILD)
writel(reset_cause, &src_regs->srsr);
#endif
}
switch (cause) {
return reset_cause;
}
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
static char *get_reset_cause(void)
{
switch (get_imx_reset_cause()) {
case 0x00001:
case 0x00011:
return "POR";
@ -77,11 +85,6 @@ static char *get_reset_cause(void)
return "unknown reset";
}
}
u32 get_imx_reset_cause(void)
{
return reset_cause;
}
#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)

342
arch/arm/mach-imx/ddrmc-vf610-calibration.c Normal file
View File

@ -0,0 +1,342 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ddrmc DDR3 calibration code for NXP's VF610
*
* Copyright (C) 2018 DENX Software Engineering
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
*/
/* #define DEBUG */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <linux/bitmap.h>
#include "ddrmc-vf610-calibration.h"
/*
* Documents:
*
* [1] "Vybrid: About DDR leveling feature on DDRMC."
* https://community.nxp.com/thread/395323
*
* [2] VFxxx Controller Reference Manual, Rev. 0, 10/2016
*
*
* NOTE
* ====
*
* NXP recommends setting 'fixed' parameters instead of performing the
* training at each boot.
*
* Use those functions to determine those values on new HW, read the
* calculated value from registers and add them to the board specific
* struct ddrmc_cr_setting.
*
* SW leveling supported operations - CR93[SW_LVL_MODE]:
*
* - 0x0 (b'00) - No leveling
*
* - 0x1 (b'01) - WRLVL_DL_X - It is not recommended to perform this tuning
* on HW designs utilizing non-flyback topology
* (Single DDR3 with x16).
* Instead the WRLVL_DL_0/1 fields shall be set
* based on trace length differences from their
* layout.
* Mismatches up to 25% or tCK (clock period) are
* allowed, so the value in the filed doesn’t have
* to be very accurate.
*
* - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
* to the DQ signals so that the strobe edge is
* centered in the window of valid read data.
*
* - 0x3 (b'11) - RDLVL_GTDL_0/1 - refers to the delay the PHY uses to un-gate
* the Read DQS strobe pad from the time that the
* PHY enables the pad to input the strobe signal.
*
*/
static int ddr_cal_get_first_edge_index(unsigned long *bmap, enum edge e,
int samples, int start, int max)
{
int i, ret = -1;
/*
* We look only for the first value (and filter out
* some wrong data)
*/
switch (e) {
case RISING_EDGE:
for (i = start; i <= max - samples; i++) {
if (test_bit(i, bmap)) {
if (!test_bit(i - 1, bmap) &&
test_bit(i + 1, bmap) &&
test_bit(i + 2, bmap) &&
test_bit(i + 3, bmap)) {
return i;
}
}
}
break;
case FALLING_EDGE:
for (i = start; i <= max - samples; i++) {
if (!test_bit(i, bmap)) {
if (test_bit(i - 1, bmap) &&
test_bit(i - 2, bmap) &&
test_bit(i - 3, bmap)) {
return i;
}
}
}
}
return ret;
}
static void bitmap_print(unsigned long *bmap, int max)
{
int i;
debug("BITMAP [0x%p]:\n", bmap);
for (i = 0; i <= max; i++) {
debug("%d ", test_bit(i, bmap) ? 1 : 0);
if (i && (i % 32) == (32 - 1))
debug("\n");
}
debug("\n");
}
#define sw_leveling_op_done \
while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
#define sw_leveling_load_value \
do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
DDRMC_CR93_SWLVL_LOAD); } while (0)
#define sw_leveling_start \
do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
DDRMC_CR93_SWLVL_START); } while (0)
#define sw_leveling_exit \
do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
DDRMC_CR94_SWLVL_EXIT); } while (0)
/*
* RDLVL_DL calibration:
*
* NXP is _NOT_ recommending performing the leveling at each
* boot. Instead - one shall run this procedure on new boards
* and then use hardcoded values.
*
*/
static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
{
DECLARE_BITMAP(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
int rdlvl_dl_0_min = -1, rdlvl_dl_0_max = -1;
int rdlvl_dl_1_min = -1, rdlvl_dl_1_max = -1;
int rdlvl_dl_0, rdlvl_dl_1;
u8 swlvl_rsp;
u32 tmp;
int i;
/* Read defaults */
u16 rdlvl_dl_0_def =
(readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF;
u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF;
debug("\nRDLVL: ======================\n");
debug("RDLVL: DQS to DQ (RDLVL)\n");
debug("RDLVL: RDLVL_DL_0_DFL:\t 0x%x\n", rdlvl_dl_0_def);
debug("RDLVL: RDLVL_DL_1_DFL:\t 0x%x\n", rdlvl_dl_1_def);
/*
* Set/Read setup for calibration
*
* Values necessary for leveling from Vybrid RM [2] - page 1600
*/
writel(0x40703030, &ddrmr->cr[144]);
writel(0x40, &ddrmr->cr[145]);
writel(0x40, &ddrmr->cr[146]);
tmp = readl(&ddrmr->cr[144]);
debug("RDLVL: PHY_RDLVL_RES:\t 0x%x\n", (tmp >> 24) & 0xFF);// set 0x40
debug("RDLVL: PHY_RDLV_LOAD:\t 0x%x\n", (tmp >> 16) & 0xFF);// set 0x70
debug("RDLVL: PHY_RDLV_DLL:\t 0x%x\n", (tmp >> 8) & 0xFF); // set 0x30
debug("RDLVL: PHY_RDLV_EN:\t 0x%x\n", tmp & 0xFF); //set 0x30
tmp = readl(&ddrmr->cr[145]);
debug("RDLVL: PHY_RDLV_RR:\t 0x%x\n", tmp & 0x3FF); //set 0x40
tmp = readl(&ddrmr->cr[146]);
debug("RDLVL: PHY_RDLV_RESP:\t 0x%x\n", tmp); //set 0x40
/*
* Program/read the leveling edge RDLVL_EDGE = 0
*
* 0x00 is the correct output on SWLVL_RSP_X
* If by any chance 1s are visible -> wrong number read
*/
clrbits_le32(&ddrmr->cr[101], DDRMC_CR101_PHY_RDLVL_EDGE);
tmp = readl(&ddrmr->cr[101]);
debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
(tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
/* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
DDRMC_CR93_SW_LVL_MODE(0x2));
tmp = readl(&ddrmr->cr[93]);
debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
(tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
/* Start procedure - CR93[SWLVL_START] to ’b1 */
sw_leveling_start;
/* Poll CR94[SWLVL_OP_DONE] */
sw_leveling_op_done;
/*
* Program delays for RDLVL_DL_0
*
* The procedure is to increase the delay values from 0 to 0xFF
* and read the response from the DDRMC
*/
debug("\nRDLVL: ---> RDLVL_DL_0\n");
bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
clrsetbits_le32(&ddrmr->cr[105],
0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
i << DDRMC_CR105_RDLVL_DL_0_OFF);
/* Load values CR93[SWLVL_LOAD] to ’b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
sw_leveling_op_done;
/*
* Read Responses - SWLVL_RESP_0
*
* The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
* -> 1 in the bit vector
*/
swlvl_rsp = (readl(&ddrmr->cr[94]) >>
DDRMC_CR94_SWLVL_RESP_0_OFF) & 0xF;
if (swlvl_rsp == 0)
generic_set_bit(i, rdlvl_rsp);
}
bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
/*
* First test for rising edge 0x0 -> 0x1 in bitmap
*/
rdlvl_dl_0_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
N_SAMPLES, N_SAMPLES,
DDRMC_DQS_DQ_MAX_DELAY);
/*
* Secondly test for falling edge 0x1 -> 0x0 in bitmap
*/
rdlvl_dl_0_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
N_SAMPLES, rdlvl_dl_0_min,
DDRMC_DQS_DQ_MAX_DELAY);
debug("RDLVL: DL_0 min: %d [0x%x] DL_0 max: %d [0x%x]\n",
rdlvl_dl_0_min, rdlvl_dl_0_min, rdlvl_dl_0_max, rdlvl_dl_0_max);
rdlvl_dl_0 = (rdlvl_dl_0_max - rdlvl_dl_0_min) / 2;
if (rdlvl_dl_0_max == -1 || rdlvl_dl_0_min == -1 || rdlvl_dl_0 <= 0) {
debug("RDLVL: The DQS to DQ delay cannot be found!\n");
debug("RDLVL: Using default - slice 0: %d!\n", rdlvl_dl_0_def);
rdlvl_dl_0 = rdlvl_dl_0_def;
}
debug("\nRDLVL: ---> RDLVL_DL_1\n");
bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
clrsetbits_le32(&ddrmr->cr[110],
0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
i << DDRMC_CR110_RDLVL_DL_1_OFF);
/* Load values CR93[SWLVL_LOAD] to ’b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
sw_leveling_op_done;
/*
* Read Responses - SWLVL_RESP_1
*
* The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
* -> 1 in the bit vector
*/
swlvl_rsp = (readl(&ddrmr->cr[95]) >>
DDRMC_CR95_SWLVL_RESP_1_OFF) & 0xF;
if (swlvl_rsp == 0)
generic_set_bit(i, rdlvl_rsp);
}
bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
/*
* First test for rising edge 0x0 -> 0x1 in bitmap
*/
rdlvl_dl_1_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
N_SAMPLES, N_SAMPLES,
DDRMC_DQS_DQ_MAX_DELAY);
/*
* Secondly test for falling edge 0x1 -> 0x0 in bitmap
*/
rdlvl_dl_1_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
N_SAMPLES, rdlvl_dl_1_min,
DDRMC_DQS_DQ_MAX_DELAY);
debug("RDLVL: DL_1 min: %d [0x%x] DL_1 max: %d [0x%x]\n",
rdlvl_dl_1_min, rdlvl_dl_1_min, rdlvl_dl_1_max, rdlvl_dl_1_max);
rdlvl_dl_1 = (rdlvl_dl_1_max - rdlvl_dl_1_min) / 2;
if (rdlvl_dl_1_max == -1 || rdlvl_dl_1_min == -1 || rdlvl_dl_1 <= 0) {
debug("RDLVL: The DQS to DQ delay cannot be found!\n");
debug("RDLVL: Using default - slice 1: %d!\n", rdlvl_dl_1_def);
rdlvl_dl_1 = rdlvl_dl_1_def;
}
debug("RDLVL: CALIBRATED: rdlvl_dl_0: 0x%x\t rdlvl_dl_1: 0x%x\n",
rdlvl_dl_0, rdlvl_dl_1);
/* Write new delay values */
writel(DDRMC_CR105_RDLVL_DL_0(rdlvl_dl_0), &ddrmr->cr[105]);
writel(DDRMC_CR110_RDLVL_DL_1(rdlvl_dl_1), &ddrmr->cr[110]);
sw_leveling_load_value;
sw_leveling_op_done;
/* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
sw_leveling_exit;
/* Poll CR94[SWLVL_OP_DONE] */
sw_leveling_op_done;
return 0;
}
/*
* WRLVL_DL calibration:
*
* For non-flyback memory architecture - where one have a single DDR3 x16
* memory - it is NOT necessary to perform "Write Leveling"
* [3] 'Vybrid DDR3 write leveling' https://community.nxp.com/thread/429362
*
*/
int ddrmc_calibration(struct ddrmr_regs *ddrmr)
{
ddrmc_cal_dqs_to_dq(ddrmr);
return 0;
}

45
arch/arm/mach-imx/ddrmc-vf610-calibration.h Normal file
View File

@ -0,0 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ddrmc DDR3 calibration code for NXP's VF610
*
* Copyright (C) 2018 DENX Software Engineering
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
*/
#ifndef __DDRMC_VF610_CALIBRATOIN_H_
#define __DDRMC_VF610_CALIBRATOIN_H_
/*
* Number of "samples" in the calibration bitmap
* to be considered during calibration.
*/
#define N_SAMPLES 3
/*
* Constants to indicate if we are looking for a rising or
* falling edge in the calibration bitmap
*/
enum edge {
FALLING_EDGE = 1,
RISING_EDGE
};
/*
* The max number of delay elements when DQS to DQ setting
*/
#define DDRMC_DQS_DQ_MAX_DELAY 0xFF
/**
* ddrmc_calibration - Vybrid's (VF610) DDR3 calibration code
*
* This function is calculating proper memory controller values
* during run time.
*
* @param ddrmr_regs - memory controller registers
*
* @return 0 on success, otherwise error code
*/
int ddrmc_calibration(struct ddrmr_regs *ddrmr);
#endif /* __DDRMC_VF610_CALIBRATOIN_H_ */

5
arch/arm/mach-imx/ddrmc-vf610.c
View File

@ -10,6 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-vf610.h>
#include <asm/arch/ddrmc-vf610.h>
#include "ddrmc-vf610-calibration.h"
void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
@ -235,4 +236,8 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
udelay(10);
writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
#ifdef CONFIG_DDRMC_VF610_CALIBRATION
ddrmc_calibration(ddrmr);
#endif
}

2
arch/arm/mach-omap2/boot-common.c
View File

@ -93,7 +93,7 @@ void save_omap_boot_params(void)
sys_boot_device = 1;
break;
#endif
#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)
#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
case BOOT_DEVICE_USB:
sys_boot_device = 1;
break;

91
board/freescale/mx6sabreauto/mx6sabreauto.c
View File

@ -159,44 +159,6 @@ static iomux_v3_cfg_t const port_exp[] = {
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/*Define for building port exp gpio, pin starts from 0*/
#define PORTEXP_IO_NR(chip, pin) \
((chip << 5) + pin)
/*Get the chip addr from a ioexp gpio*/
#define PORTEXP_IO_TO_CHIP(gpio_nr) \
(gpio_nr >> 5)
/*Get the pin number from a ioexp gpio*/
#define PORTEXP_IO_TO_PIN(gpio_nr) \
(gpio_nr & 0x1f)
static int port_exp_direction_output(unsigned gpio, int value)
{
int ret;
i2c_set_bus_num(2);
ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
if (ret)
return ret;
ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),
(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
if (ret)
return ret;
ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
(1 << PORTEXP_IO_TO_PIN(gpio)),
(value << PORTEXP_IO_TO_PIN(gpio)));
if (ret)
return ret;
return 0;
}
#ifdef CONFIG_MTD_NOR_FLASH
static iomux_v3_cfg_t const eimnor_pads[] = {
IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
@ -501,6 +463,7 @@ iomux_v3_cfg_t const backlight_pads[] = {
static void setup_iomux_backlight(void)
{
gpio_request(IMX_GPIO_NR(2, 9), "backlight");
gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
SETUP_IOMUX_PADS(backlight_pads);
}
@ -594,6 +557,7 @@ int board_init(void)
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
/* I2C 3 Steer */
gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
SETUP_IOMUX_PADS(i2c3_pads);
#ifndef CONFIG_SYS_FLASH_CFI
@ -602,6 +566,7 @@ int board_init(void)
else
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
#endif
gpio_request(IMX_GPIO_NR(1, 15), "expander en");
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
SETUP_IOMUX_PADS(port_exp);
@ -678,19 +643,10 @@ int checkboard(void)
}
#ifdef CONFIG_USB_EHCI_MX6
#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
iomux_v3_cfg_t const usb_otg_pads[] = {
IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
int board_ehci_hcd_init(int port)
{
switch (port) {
case 0:
SETUP_IOMUX_PADS(usb_otg_pads);
/*
* Set daisy chain for otg_pin_id on 6q.
* For 6dl, this bit is reserved.
@ -705,29 +661,6 @@ int board_ehci_hcd_init(int port)
}
return 0;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
if (on)
port_exp_direction_output(USB_OTG_PWR, 1);
else
port_exp_direction_output(USB_OTG_PWR, 0);
break;
case 1:
if (on)
port_exp_direction_output(USB_HOST1_PWR, 1);
else
port_exp_direction_output(USB_HOST1_PWR, 0);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return -EINVAL;
}
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
@ -1097,3 +1030,21 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq()) {
if (!strcmp(name, "imx6q-sabreauto"))
return 0;
} else if (is_mx6dqp()) {
if (!strcmp(name, "imx6qp-sabreauto"))
return 0;
} else if (is_mx6dl()) {
if (!strcmp(name, "imx6dl-sabreauto"))
return 0;
}
return -1;
}
#endif

78
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -94,12 +94,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
static void setup_iomux_enet(void)
{
SETUP_IOMUX_PADS(enet_pads);
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
udelay(100);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
@ -189,6 +183,7 @@ static iomux_v3_cfg_t const bl_pads[] = {
static void enable_backlight(void)
{
SETUP_IOMUX_PADS(bl_pads);
gpio_request(DISP0_PWR_EN, "Display Power Enable");
gpio_direction_output(DISP0_PWR_EN, 1);
}
@ -307,11 +302,13 @@ int board_mmc_init(bd_t *bis)
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc3_pads);
gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
@ -559,63 +556,13 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usb_hc1_pads[] = {
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_usb(void)
{
SETUP_IOMUX_PADS(usb_otg_pads);
/*
* set daisy chain for otg_pin_id on 6q.
* for 6dl, this bit is reserved
*/
imx_iomux_set_gpr_register(1, 13, 1, 0);
SETUP_IOMUX_PADS(usb_hc1_pads);
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
break;
case 1:
if (on)
gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
else
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return -EINVAL;
}
return 0;
}
#endif
@ -729,6 +676,7 @@ int checkboard(void)
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
gpio_request(KEY_VOL_UP, "KEY Volume UP");
gpio_direction_input(KEY_VOL_UP);
/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
@ -1062,3 +1010,21 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_mx6dq()) {
if (!strcmp(name, "imx6q-sabresd"))
return 0;
} else if (is_mx6dqp()) {
if (!strcmp(name, "imx6qp-sabresd"))
return 0;
} else if (is_mx6dl()) {
if (!strcmp(name, "imx6dl-sabresd"))
return 0;
}
return -1;
}
#endif

514
board/gateworks/gw_ventana/common.c
View File

@ -18,12 +18,6 @@
#include "common.h"
/* UART1: Function varies per baseboard */
static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
static iomux_v3_cfg_t const uart2_pads[] = {
IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
@ -32,7 +26,6 @@ static iomux_v3_cfg_t const uart2_pads[] = {
void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
SETUP_IOMUX_PADS(uart2_pads);
}
@ -85,95 +78,96 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* I2C1: GSC */
static struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
/*
* I2C pad configs:
* I2C1: GSC
* I2C2: PMIC,PCIe Switch,Clock,Mezz
* I2C3: Multimedia/Expansion
*/
static struct i2c_pads_info mx6q_i2c_pad_info[] = {
{
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
}, {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
}, {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
}
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
{
.scl = {
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
}, {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
}, {
.scl = {
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
}
};
/* I2C3: Misc/Expansion */
static struct i2c_pads_info mx6q_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
void setup_ventana_i2c(void)
void setup_ventana_i2c(int i2c)
{
if (is_cpu_type(MXC_CPU_MX6Q)) {
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
} else {
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
}
struct i2c_pads_info *p;
if (is_cpu_type(MXC_CPU_MX6Q))
p = &mx6q_i2c_pad_info[i2c];
else
p = &mx6dl_i2c_pad_info[i2c];
setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
}
/*
@ -395,6 +389,51 @@ static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* ETH1_EN */
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
/* PMIC reset */
IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
/* COM_CFGA/B/C/D */
IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
/* ETI_IRQ# */
IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
/* DIO_IRQ# */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* FIBER_SIGDET */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
/* MX6_LOCLED# */
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* CAN1_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* CAN2_STBY */
IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG),
/* UART1_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
/* 5V_UVLO */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* ETI_IRQ# */
IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
/* DIO_IRQ# */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* USBOTG_PEN */
IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
/* BKLT_12VEN */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
@ -461,6 +500,49 @@ static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
/* M2_RST# */
IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
/* EMMY_PDN# */
IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
/* MX6_LOCLED# */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* MIPI_RST */
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
/* MIPI_PWDN */
IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
/* USBEHCI_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* PCI_RST# */
IOMUX_PADS(PAD_GPIO_16__GPIO7_IO11 | DIO_PAD_CFG),
/* LVDS_BKLEN # */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
/* PCIESKT_WDIS# */
IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
/* SPK_SHDN# */
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* LOCLED# */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
/* FLASH LED1 */
IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | DIO_PAD_CFG),
/* FLASH LED2 */
IOMUX_PADS(PAD_DISP0_DAT12__GPIO5_IO06 | DIO_PAD_CFG),
/* DECT_RST# */
IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
/* USBH1_PEN (EHCI) */
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* LVDS_PWM */
IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
/* CODEC_RST */
IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
/* GYRO_CONTROL/DATA_EN */
IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
/* TOUCH_RST */
IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
/* TOUCH_IRQ */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
};
/* Digital I/O */
@ -704,6 +786,60 @@ struct dio_cfg gw560x_dio[] = {
},
};
struct dio_cfg gw5901_dio[] = {
{
{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
IMX_GPIO_NR(5, 14),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
IMX_GPIO_NR(5, 15),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
IMX_GPIO_NR(5, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
IMX_GPIO_NR(5, 17),
{ 0, 0 },
0
},
};
struct dio_cfg gw5902_dio[] = {
{
{ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
IMX_GPIO_NR(5, 14),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
IMX_GPIO_NR(5, 15),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
IMX_GPIO_NR(5, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
IMX_GPIO_NR(5, 17),
{ 0, 0 },
0
},
};
struct dio_cfg gw5903_dio[] = {
};
@ -782,6 +918,33 @@ struct dio_cfg gw5904_dio[] = {
},
};
struct dio_cfg gw5906_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
};
/*
* Board Specific GPIO
*/
@ -824,6 +987,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.vidin_en = IMX_GPIO_NR(5, 20),
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(3, 22),
.nand = true,
},
/* GW52xx */
@ -849,6 +1013,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW53xx */
@ -873,6 +1038,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW54xx */
@ -899,6 +1065,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW551x */
@ -912,6 +1079,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
.nand = true,
},
/* GW552x */
@ -929,6 +1097,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.nand = true,
},
/* GW553x */
@ -947,6 +1116,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
.mmc_cd = IMX_GPIO_NR(7, 0),
.nand = true,
},
/* GW560x */
@ -970,6 +1140,32 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW5901 */
{
.gpio_pads = gw5901_gpio_pads,
.num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
.dio_cfg = gw5901_dio,
.leds = {
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.nand = true,
},
/* GW5902 */
{
.gpio_pads = gw5902_gpio_pads,
.num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
.dio_cfg = gw5902_dio,
.leds = {
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 23),
.nand = true,
},
/* GW5903 */
{
.gpio_pads = gw5903_gpio_pads,
@ -999,8 +1195,96 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
/* GW5905 */
{
.gpio_pads = gw5905_gpio_pads,
.num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
.leds = {
IMX_GPIO_NR(6, 14),
},
.pcie_rst = IMX_GPIO_NR(7, 11),
.wdis = IMX_GPIO_NR(7, 13),
},
/* GW5906 */
{
.gpio_pads = gw552x_gpio_pads,
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = gw5906_dio,
.dio_num = ARRAY_SIZE(gw5906_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.nand = true,
},
/* GW5907 */
{
.gpio_pads = gw51xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
.dio_cfg = gw51xx_dio,
.dio_num = ARRAY_SIZE(gw51xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 10),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.wdis = IMX_GPIO_NR(7, 12),
.nand = true,
},
/* GW5908 */
{
.gpio_pads = gw53xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
.dio_cfg = gw53xx_dio,
.dio_num = ARRAY_SIZE(gw53xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 29),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
},
/* GW5909 */
{
.gpio_pads = gw5904_gpio_pads,
.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
.dio_cfg = gw5904_dio,
.dio_num = ARRAY_SIZE(gw5904_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
IMX_GPIO_NR(4, 15),
},
.pcie_rst = IMX_GPIO_NR(1, 0),
.mezz_pwren = IMX_GPIO_NR(2, 19),
.mezz_irq = IMX_GPIO_NR(2, 18),
.otgpwr_en = IMX_GPIO_NR(3, 22),
},
};
#define SETUP_GPIO_OUTPUT(gpio, name, level) \
gpio_request(gpio, name); \
gpio_direction_output(gpio, level);
#define SETUP_GPIO_INPUT(gpio, name) \
gpio_request(gpio, name); \
gpio_direction_input(gpio);
void setup_iomux_gpio(int board, struct ventana_board_info *info)
{
int i;
@ -1119,6 +1403,14 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
break;
case GW5901:
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0);
break;
case GW5902:
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
break;
case GW5903:
gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
@ -1135,7 +1427,10 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
break;
case GW5909:
case GW5904:
gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
@ -1149,6 +1444,28 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
break;
case GW5905:
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
mdelay(100);
/*
* gauruntee touch controller comes out of reset with INT
* low for address
*/
SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
break;
}
}
@ -1298,7 +1615,7 @@ void setup_pmic(void)
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
break;
case GW5903:
/* mask PGOOD during SW1 transition */
/* mask PGOOD during SW3 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_ARM) */
@ -1310,6 +1627,19 @@ void setup_pmic(void)
/* set SW4 (VDD_SOC) */
pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
break;
case GW5905:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW1 (VDD_ARM) */
pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
/* mask PGOOD during SW3 transition */
pmic_reg_write(p, LTC3676_DVB3B,
0x1f | LTC3676_PGOOD_MASK);
/* set SW3 (VDD_SOC) */
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
break;
default:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
@ -1377,6 +1707,8 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[1].max_bus_width = 4;
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
case GW5904:
case GW5905:
case GW5909:
/* usdhc3: 8bit eMMC */
SETUP_IOMUX_PADS(gw5904_emmc_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
@ -1405,6 +1737,8 @@ int board_mmc_getcd(struct mmc *mmc)
break;
case GW5903:
case GW5904:
case GW5905:
case GW5909:
/* emmc is always present */
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
return 1;

3
board/gateworks/gw_ventana/common.h
View File

@ -80,12 +80,13 @@ struct ventana {
int mmc_cd;
/* various features */
bool usd_vsel;
bool nand;
};
extern struct ventana gpio_cfg[GW_UNKNOWN];
/* configure i2c iomux */
void setup_ventana_i2c(void);
void setup_ventana_i2c(int);
/* configure uart iomux */
void setup_iomux_uart(void);
/* conifgure PMIC */

18
board/gateworks/gw_ventana/eeprom.c
View File

@ -97,10 +97,24 @@ read_eeprom(int bus, struct ventana_board_info *info)
type = GW560x;
break;
case '9':
if (info->model[4] == '0' && info->model[5] == '3')
if (info->model[4] == '0' && info->model[5] == '1')
type = GW5901;
else if (info->model[4] == '0' && info->model[5] == '2')
type = GW5902;
else if (info->model[4] == '0' && info->model[5] == '3')
type = GW5903;
if (info->model[4] == '0' && info->model[5] == '4')
else if (info->model[4] == '0' && info->model[5] == '4')
type = GW5904;
else if (info->model[4] == '0' && info->model[5] == '5')
type = GW5905;
else if (info->model[4] == '0' && info->model[5] == '6')
type = GW5906;
else if (info->model[4] == '0' && info->model[5] == '7')
type = GW5907;
else if (info->model[4] == '0' && info->model[5] == '8')
type = GW5908;
else if (info->model[4] == '0' && info->model[5] == '9')
type = GW5909;
break;
}
return type;

6
board/gateworks/gw_ventana/gsc.c
View File

@ -70,7 +70,7 @@ static void read_hwmon(const char *name, uint reg, uint size)
puts("fRD\n");
} else {
ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
if (reg == GSC_HWMON_TEMP && ui > 0x8000)
if (size == 2 && ui > 0x8000)
ui -= 0xffff;
if (ui == 0xffffff)
puts("invalid\n");
@ -140,6 +140,10 @@ int gsc_info(int verbose)
read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
break;
case '9': /* GW590x */
read_hwmon("AMONBMON", GSC_HWMON_VDD_IO3, 3);
read_hwmon("BAT_VOLT", GSC_HWMON_VDD_EXT, 3);
read_hwmon("BAT_TEMP", GSC_HWMON_VDD_IO4, 2);
}
return 0;
}

3
board/gateworks/gw_ventana/gsc.h
View File

@ -48,9 +48,10 @@ enum {
GSC_HWMON_VBATT = 0x08,
GSC_HWMON_VDD_5P0 = 0x0b,
GSC_HWMON_VDD_CORE = 0x0e,
GSC_HWMON_VDD_SOC = 0x11,
GSC_HWMON_VDD_HIGH = 0x14,
GSC_HWMON_VDD_DDR = 0x17,
GSC_HWMON_VDD_SOC = 0x11,
GSC_HWMON_VDD_EXT = 0x1a,
GSC_HWMON_VDD_1P8 = 0x1d,
GSC_HWMON_VDD_IO2 = 0x20,
GSC_HWMON_VDD_2P5 = 0x23,

151
board/gateworks/gw_ventana/gw_ventana.c
View File

@ -155,6 +155,7 @@ int board_ehci_hcd_init(int port)
switch (board_type) {
case GW53xx:
case GW552x:
case GW5906:
gpio = (IMX_GPIO_NR(1, 9));
break;
case GW54proto:
@ -267,11 +268,11 @@ int mv88e61xx_hw_reset(struct phy_device *phydev)
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
/* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
bus->write(bus, 0x10, 0, 0x16, 0x8089);
bus->write(bus, 0x11, 0, 0x16, 0x8089);
bus->write(bus, 0x12, 0, 0x16, 0x8089);
bus->write(bus, 0x13, 0, 0x16, 0x8089);
/* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
bus->write(bus, 0x10, 0, 0x16, 0x8088);
bus->write(bus, 0x11, 0, 0x16, 0x8088);
bus->write(bus, 0x12, 0, 0x16, 0x8088);
bus->write(bus, 0x13, 0, 0x16, 0x8088);
return 0;
}
@ -384,8 +385,8 @@ struct display_info_t const displays[] = {{
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC700JMG-T-4 */
.bus = 0,
.addr = 0,
.bus = 2,
.addr = 0x38,
.detect = NULL,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
@ -405,8 +406,8 @@ struct display_info_t const displays[] = {{
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC800FIG-T-3 */
.bus = 0,
.addr = 0,
.bus = 2,
.addr = 0x14,
.detect = NULL,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
@ -424,7 +425,29 @@ struct display_info_t const displays[] = {{
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
} }, {
.bus = 2,
.addr = 0x5d,
.detect = detect_i2c,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
.name = "Z101WX01",
.refresh = 60,
.xres = 1280,
.yres = 800,
.pixclock = 15385, /* 64MHz */
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
}
},
};
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
@ -625,19 +648,23 @@ int board_init(void)
/* address of linux boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* read Gateworks EEPROM into global struct (used later) */
setup_ventana_i2c(0);
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
#ifdef CONFIG_CMD_NAND
setup_gpmi_nand();
if (gpio_cfg[board_type].nand)
setup_gpmi_nand();
#endif
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
setup_ventana_i2c();
setup_ventana_i2c(1);
setup_ventana_i2c(2);
#ifdef CONFIG_SATA
setup_sata();
#endif
/* read Gateworks EEPROM into global struct (used later) */
board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
setup_iomux_gpio(board_type, &ventana_info);
@ -707,7 +734,7 @@ static const struct boot_mode board_boot_modes[] = {
/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
{ NULL, 0 },
};
#endif
@ -852,34 +879,12 @@ static int ft_sethdmiinfmt(void *blob, char *mode)
return 0;
}
/* enable a property of a node if the node is found */
static inline void ft_enable_path(void *blob, const char *path)
{
int i = fdt_path_offset(blob, path);
if (i >= 0) {
debug("enabling %s\n", path);
fdt_status_okay(blob, i);
}
}
/* remove a property of a node if the node is found */
static inline void ft_delprop_path(void *blob, const char *path,
const char *name)
{
int i = fdt_path_offset(blob, path);
if (i) {
debug("removing %s/%s\n", path, name);
fdt_delprop(blob, i, name);
}
}
#if defined(CONFIG_CMD_PCI)
#define PCI_ID(x) ( \
(PCI_BUS(x->devfn)<<16)| \
(PCI_DEV(x->devfn)<<11)| \
(PCI_FUNC(x->devfn)<<8) \
)
#define PCIE_PATH "/soc/pcie@0x01000000"
int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
{
uint32_t reg[5];
@ -912,7 +917,7 @@ int fdt_add_pci_path(void *blob, struct pci_dev *dev)
int k, np;
/* build list of parents */
np = fdt_path_offset(blob, PCIE_PATH);
np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
if (np < 0)
return np;
@ -949,7 +954,7 @@ int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
int i;
/* build irq-map based on host controllers map */
host = fdt_path_offset(blob, PCIE_PATH);
host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
if (host < 0) {
printf(" %s failed: missing host\n", __func__);
return host;
@ -1091,10 +1096,14 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
}
#endif /* if defined(CONFIG_CMD_PCI) */
void ft_board_wdog_fixup(void *blob, const char *path)
void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
{
ft_delprop_path(blob, path, "ext-reset-output");
ft_delprop_path(blob, path, "fsl,ext-reset-output");
int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
if (off) {
fdt_delprop(blob, off, "ext-reset-output");
fdt_delprop(blob, off, "fsl,ext-reset-output");
}
}
/*
@ -1106,10 +1115,11 @@ void ft_board_wdog_fixup(void *blob, const char *path)
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
#define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000"
#define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000"
#define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000"
#define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000"
#define WDOG1_ADDR 0x20bc000
#define WDOG2_ADDR 0x20c0000
#define GPIO3_ADDR 0x20a4000
#define USDHC3_ADDR 0x2198000
#define PWM0_ADDR 0x2080000
int ft_board_setup(void *blob, bd_t *bd)
{
struct ventana_board_info *info = &ventana_info;
@ -1172,14 +1182,15 @@ int ft_board_setup(void *blob, bd_t *bd)
* errata causing wdog timer to be unreliable.
*/
if (rev >= 'A' && rev < 'C') {
i = fdt_path_offset(blob, WDOG1_PATH);
i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
WDOG1_ADDR);
if (i)
fdt_status_disabled(blob, i);
}
/* GW51xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW52xx:
@ -1195,7 +1206,8 @@ int ft_board_setup(void *blob, bd_t *bd)
"reset-gpio", NULL);
if (range) {
i = fdt_path_offset(blob, GPIO3_PATH);
i = fdt_node_offset_by_compat_reg(blob,
"fsl,imx6q-gpio", GPIO3_ADDR);
if (i)
handle = fdt_get_phandle(blob, i);
if (handle) {
@ -1210,18 +1222,19 @@ int ft_board_setup(void *blob, bd_t *bd)
gpio_cfg[board_type].usd_vsel = 0;
/* GW522x-B adds WDOG1_B external reset */
ft_board_wdog_fixup(blob, WDOG1_PATH);
if (rev < 'B')
ft_board_wdog_fixup(blob, WDOG1_ADDR);
}
/* GW520x-E adds WDOG1_B external reset */
else if (info->model[4] == '0' && rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW53xx:
/* GW53xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW54xx:
@ -1229,13 +1242,12 @@ int ft_board_setup(void *blob, bd_t *bd)
* disable serial2 node for GW54xx for compatibility with older
* 3.10.x kernel that improperly had this node enabled in the DT
*/
i = fdt_path_offset(blob, UART1_PATH);
if (i)
fdt_del_node(blob, i);
fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
0);
/* GW54xx-E adds WDOG2_B external reset */
if (rev < 'E')
ft_board_wdog_fixup(blob, WDOG2_PATH);
ft_board_wdog_fixup(blob, WDOG2_ADDR);
break;
case GW551x:
@ -1284,7 +1296,13 @@ int ft_board_setup(void *blob, bd_t *bd)
/* GW551x-C adds WDOG1_B external reset */
if (rev < 'C')
ft_board_wdog_fixup(blob, WDOG1_PATH);
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
case GW5901:
case GW5902:
/* GW5901/GW5901 revB adds WDOG1_B as an external reset */
if (rev < 'B')
ft_board_wdog_fixup(blob, WDOG1_ADDR);
break;
}
@ -1298,20 +1316,27 @@ int ft_board_setup(void *blob, bd_t *bd)
continue;
if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
{
char path[48];
sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
phys_addr_t addr;
int off;
printf(" Enabling pwm%d for DIO%d\n",
cfg->pwm_param, i);
ft_enable_path(blob, path);
addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
off = fdt_node_offset_by_compat_reg(blob,
"fsl,imx6q-pwm",
addr);
if (off)
fdt_status_okay(blob, off);
}
}
/* remove no-1-8-v if UHS-I support is present */
if (gpio_cfg[board_type].usd_vsel) {
debug("Enabling UHS-I support\n");
ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
"no-1-8-v");
i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
USDHC3_ADDR);
if (i)
fdt_delprop(blob, i, "no-1-8-v");
}
#if defined(CONFIG_CMD_PCI)

97
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -217,6 +217,46 @@ static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
.p0_mpwrdlctl = 0x33382C31,
};
/* TODO: update with calibrated values */
static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x00190017,
.p0_mpwldectrl1 = 0x00140026,
.p1_mpwldectrl0 = 0x0021001C,
.p1_mpwldectrl1 = 0x0011001D,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x43380347,
.p0_mpdgctrl1 = 0x433C034D,
.p1_mpdgctrl0 = 0x032C0324,
.p1_mpdgctrl1 = 0x03310232,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x3C313539,
.p1_mprddlctl = 0x37343141,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x36393C39,
.p1_mpwrdlctl = 0x42344438,
};
/* TODO: update with calibrated values */
static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x003C003C,
.p0_mpwldectrl1 = 0x001F002A,
.p1_mpwldectrl0 = 0x00330038,
.p1_mpwldectrl1 = 0x0022003F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x42410244,
.p0_mpdgctrl1 = 0x4234023A,
.p1_mpdgctrl0 = 0x022D022D,
.p1_mpdgctrl1 = 0x021C0228,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x484A4C4B,
.p1_mprddlctl = 0x4B4D4E4B,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x33342B32,
.p1_mpwrdlctl = 0x3933332B,
};
static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x001B0016,
@ -390,6 +430,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
.p1_mpwrdlctl = 0x3F36363F,
};
static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x001F003F,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x001F004E,
.p1_mpwldectrl1 = 0x0059001F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x42220225,
.p0_mpdgctrl1 = 0x0213021F,
.p1_mpdgctrl0 = 0x022C0242,
.p1_mpdgctrl1 = 0x022C0244,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x474A4C4A,
.p1_mprddlctl = 0x48494C45,
/* Write Calibration: DQ/DM delay relative to DQS write access */
.p0_mpwrdlctl = 0x3F3F3F36,
.p1_mpwrdlctl = 0x3F36363F,
};
static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x002A0025,
@ -511,6 +570,10 @@ static void spl_dram_init(int width, int size_mb, int board_model)
} else if (width == 64 && size_mb == 512) {
mem = &mt41k64m16jt_125;
debug("1gB density\n");
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_64x64_mmdc_calib;
else
calib = &mx6sdl_64x64_mmdc_calib;
} else if (width == 64 && size_mb == 1024) {
mem = &mt41k128m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
@ -519,18 +582,33 @@ static void spl_dram_init(int width, int size_mb, int board_model)
calib = &mx6sdl_128x64_mmdc_calib;
debug("2gB density\n");
} else if (width == 64 && size_mb == 2048) {
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_256x64_mmdc_calib;
else
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
switch(board_model) {
case GW5905:
/* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
mem = &mt41k128m16jt_125;
debug("2gB density - 2 chipsel\n");
if (!is_cpu_type(MXC_CPU_MX6Q)) {
calib = &mx6sdl_128x64x2_mmdc_calib;
sysinfo.ncs = 2;
sysinfo.cs_density = 10; /* CS0_END=39 */
sysinfo.cs1_mirror = 1; /* mirror enabled */
}
break;
default:
mem = &mt41k256m16ha_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6dq_256x64_mmdc_calib;
else
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
break;
}
} else if (width == 64 && size_mb == 4096) {
switch(board_model) {
case GW5903:
/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
mem = &mt41k256m16ha_125;
debug("4gB density\n");
debug("4gB density - 2 chipsel\n");
if (!is_cpu_type(MXC_CPU_MX6Q)) {
calib = &mx6sdl_256x64x2_mmdc_calib;
sysinfo.ncs = 2;
@ -599,9 +677,10 @@ void board_init_f(ulong dummy)
/* setup AXI */
gpr_init();
/* iomux and setup of i2c */
/* iomux and setup of uart/i2c */
setup_iomux_uart();
setup_ventana_i2c();
setup_ventana_i2c(0);
setup_ventana_i2c(1);
/* setup GP timer */
timer_init();

7
board/gateworks/gw_ventana/ventana_eeprom.h
View File

@ -112,8 +112,15 @@ enum {
GW552x,
GW553x,
GW560x,
GW5901,
GW5902,
GW5903,
GW5904,
GW5905,
GW5906,
GW5907,
GW5908,
GW5909,
GW_UNKNOWN,
GW_BADCRC,
};

79
board/logicpd/imx6/imx6logic.c
View File

@ -60,57 +60,6 @@ static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#ifndef CONFIG_SPL_BUILD
static void fixup_enet_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct gpio_desc nint;
struct gpio_desc reset;
int ret;
/* Set Ref Clock to 50 MHz */
enable_fec_anatop_clock(0, ENET_50MHZ);
/* Set GPIO_16 as ENET_REF_CLK_OUT */
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
/* Request GPIO Pins to reset Ethernet with new clock */
ret = dm_gpio_lookup_name("GPIO4_7", &nint);
if (ret) {
printf("Unable to lookup GPIO4_7\n");
return;
}
ret = dm_gpio_request(&nint, "eth0_nInt");
if (ret) {
printf("Unable to request eth0_nInt\n");
return;
}
/* Ensure nINT is input or PHY won't startup */
dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
ret = dm_gpio_lookup_name("GPIO4_9", &reset);
if (ret) {
printf("Unable to lookup GPIO4_9\n");
return;
}
ret = dm_gpio_request(&reset, "eth0_reset");
if (ret) {
printf("Unable to request eth0_reset\n");
return;
}
/* Reset LAN8710A PHY */
dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
dm_gpio_set_value(&reset, 0);
udelay(150);
dm_gpio_set_value(&reset, 1);
mdelay(50);
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@ -141,8 +90,33 @@ static void setup_nand_pins(void)
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
/* To enable AR8031 output a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
/* introduce tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
val |= 0x0100;
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
ar8031_phy_fixup(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
@ -160,9 +134,6 @@ int overwrite_console(void)
int board_early_init_f(void)
{
#ifndef CONFIG_SPL_BUILD
fixup_enet_clock();
#endif
setup_iomux_uart();
setup_nand_pins();
return 0;

5
common/Makefile
View File

@ -75,8 +75,9 @@ obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
ifdef CONFIG_SPL_USB_HOST_SUPPORT
obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
obj-y += usb.o
obj-y += usb_hub.o
obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o
else
obj-$(CONFIG_USB_MUSB_HOST) += usb.o
endif

4
common/spl/Kconfig
View File

@ -794,9 +794,9 @@ config SPL_USB_HOST_SUPPORT
device can be attached. This option enables the drivers in
drivers/usb/host as part of an SPL build.
config SPL_USB_SUPPORT
config SPL_USB_STORAGE
bool "Support loading from USB"
depends on SPL_USB_HOST_SUPPORT
depends on SPL_USB_HOST_SUPPORT && !(BLK && !DM_USB)
help
Enable support for USB devices in SPL. This allows use of USB
devices such as hard drives and flash drivers for loading U-Boot.

2
common/spl/Makefile
View File

@ -22,7 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o

4
common/spl/spl_usb.c
View File

@ -15,9 +15,7 @@
#include <usb.h>
#include <fat.h>
#ifdef CONFIG_USB_STORAGE
static int usb_stor_curr_dev = -1; /* current device */
#endif
static int spl_usb_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
@ -34,13 +32,11 @@ static int spl_usb_load_image(struct spl_image_info *spl_image,
return err;
}
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, usb_stor_curr_dev);
if (!stor_dev)
return -ENODEV;
#endif
debug("boot mode - FAT\n");

2
configs/am43xx_evm_usbhost_boot_defconfig
View File

@ -14,7 +14,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_SUPPORT=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000

2
configs/am43xx_hs_evm_defconfig
View File

@ -24,7 +24,7 @@ CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_SUPPORT=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
# CONFIG_CMD_FLASH is not set

4
configs/imx6q_logic_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_TPL_BANNER_PRINT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
@ -31,7 +32,8 @@ CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_PROMPT="i.MX6 Logic # "
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_SPL_NAND_OFS=0x1500000
CONFIG_CMD_SPL_WRITE_SIZE=0x00100000
CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y

20
configs/mx6sabreauto_defconfig
View File

@ -11,12 +11,18 @@ CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NXP_BOARD_REVISION=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
@ -40,20 +46,33 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
@ -65,4 +84,3 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y

25
configs/mx6sabresd_defconfig
View File

@ -10,12 +10,18 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
@ -47,23 +53,39 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
@ -73,4 +95,3 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y

100
doc/imx/hab/habv4/secure_boot.txt
View File

@ -1,100 +0,0 @@
1. High Assurance Boot (HAB) for i.MX CPUs
------------------------------------------
To enable the authenticated or encrypted boot mode of U-Boot, it is
required to set the proper configuration for the target board. This
is done by adding the following configuration in the defconfig file:
CONFIG_SECURE_BOOT=y
In addition, the U-Boot image to be programmed into the
boot media needs to be properly constructed, i.e. it must contain a
proper Command Sequence File (CSF).
The CSF itself is generated by the i.MX High Assurance Boot Reference
Code Signing Tool.
https://www.nxp.com/webapp/sps/download/license.jsp?colCode=IMX_CST_TOOL
More information about the CSF and HAB can be found in the AN4581.
https://www.nxp.com/docs/en/application-note/AN4581.pdf
We don't want to explain how to create a PKI tree or SRK table as
this is well explained in the Application Note.
2. Secure Boot on non-SPL targets
---------------------------------
On non-SPL targets a singe U-Boot binary is generated, mkimage will
output additional information about "HAB Blocks" which can be used
in the CST to authenticate the U-Boot image (entries in the CSF file).
Image Type: Freescale IMX Boot Image
Image Ver: 2 (i.MX53/6 compatible)
Data Size: 327680 Bytes = 320.00 kB = 0.31 MB
Load Address: 177ff420
Entry Point: 17800000
HAB Blocks: 0x177ff400 0x00000000 0x0004dc00
^^^^^^^^^^ ^^^^^^^^^^ ^^^^^^^^^^
| | |
| | ----- (1)
| |
| ---------------- (2)
|
--------------------------- (3)
(1) Size of area in file u-boot-dtb.imx to sign
This area should include the IVT, the Boot Data the DCD
and U-Boot itself.
(2) Start of area in u-boot-dtb.imx to sign
(3) Start of area in RAM to authenticate
CONFIG_SECURE_BOOT currently enables only an additional command
'hab_status' in U-Boot to retrieve the HAB status and events. This
can be useful while developing and testing HAB.
Commands to generate a signed U-Boot using i.MX HAB CST tool:
# Compile CSF and create signature
cst --o csf-u-boot.bin --i command_sequence_uboot.csf
# Append compiled CSF to Binary
cat u-boot-dtb.imx csf-u-boot.bin > u-boot-signed.imx
3. Secure Boot on SPL targets
-----------------------------
This version of U-Boot is able to build a signable version of the SPL
as well as a signable version of the U-Boot image. The signature can
be verified through High Assurance Boot (HAB).
After building, you need to create a command sequence file and use
i.MX HAB Code Signing Tool to sign both binaries. After creation,
the mkimage tool outputs the required information about the HAB Blocks
parameter for the CSF. During the build, the information is preserved
in log files named as the binaries. (SPL.log and u-boot-ivt.log).
Example Output of the SPL (imximage) creation:
Image Type: Freescale IMX Boot Image
Image Ver: 2 (i.MX53/6/7 compatible)
Mode: DCD
Data Size: 61440 Bytes = 60.00 kB = 0.06 MB
Load Address: 00907420
Entry Point: 00908000
HAB Blocks: 0x00907400 0x00000000 0x0000cc00
Example Output of the u-boot-ivt.img (firmware_ivt) creation:
Image Name: U-Boot 2016.11-rc1-31589-g2a4411
Created: Sat Nov 5 21:53:28 2016
Image Type: ARM U-Boot Firmware with HABv4 IVT (uncompressed)
Data Size: 352192 Bytes = 343.94 kB = 0.34 MB
Load Address: 17800000
Entry Point: 00000000
HAB Blocks: 0x177fffc0 0x0000 0x00054020
# Compile CSF and create signature
cst --o csf-u-boot.bin --i command_sequence_uboot.csf
cst --o csf-SPL.bin --i command_sequence_spl.csf
# Append compiled CSF to Binary
cat SPL csf-SPL.bin > SPL-signed
cat u-boot-ivt.img csf-u-boot.bin > u-boot-signed.img
These two signed binaries can be used on an i.MX in closed
configuration when the according SRK Table Hash has been flashed.

34
doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt Normal file
View File

@ -0,0 +1,34 @@
[Header]
Version = 4.2
Hash Algorithm = sha256
Engine Configuration = 0
Certificate Format = X509
Signature Format = CMS
Engine = CAAM
[Install SRK]
# Index of the key location in the SRK table to be installed
File = "../crts/SRK_1_2_3_4_table.bin"
Source index = 0
[Install CSFK]
# Key used to authenticate the CSF data
File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
[Authenticate CSF]
[Install Key]
# Key slot index used to authenticate the key to be installed
Verification index = 0
# Target key slot in HAB key store where key will be installed
Target Index = 2
# Key to install
File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
[Authenticate Data]
# Key slot index used to authenticate the image data
Verification index = 2
# Authenticate Start Address, Offset, Length and file
Blocks = 0x80800000 0x00000000 0x80EEA020 "zImage", \
0x83800000 0x00000000 0x8380B927 "imx7d-sdb.dtb", \
0x84000000 0x00000000 0x840425B8 "uTee-7dsdb"

32
doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot.txt Normal file
View File

@ -0,0 +1,32 @@
[Header]
Version = 4.2
Hash Algorithm = sha256
Engine Configuration = 0
Certificate Format = X509
Signature Format = CMS
Engine = CAAM
[Install SRK]
# Index of the key location in the SRK table to be installed
File = "../crts/SRK_1_2_3_4_table.bin"
Source index = 0
[Install CSFK]
# Key used to authenticate the CSF data
File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
[Authenticate CSF]
[Install Key]
# Key slot index used to authenticate the key to be installed
Verification index = 0
# Target key slot in HAB key store where key will be installed
Target Index = 2
# Key to install
File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
[Authenticate Data]
# Key slot index used to authenticate the image data
Verification index = 2
# Authenticate Start Address, Offset, Length and file
Blocks = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx"

23
doc/imx/habv4/csf_examples/mx6_mx7/csf_uboot_fast_authentication.txt Normal file
View File

@ -0,0 +1,23 @@
[Header]
Version = 4.2
Hash Algorithm = sha256
Engine Configuration = 0
Certificate Format = X509
Signature Format = CMS
Engine = CAAM
[Install SRK]
# Index of the key location in the SRK table to be installed
File = "../crts/SRK_1_2_3_4_table.bin"
Source index = 0
[Install NOCAK]
File = "../crts/SRK1_sha256_2048_65537_v3_usr_crt.pem"
[Authenticate CSF]
[Authenticate Data]
# Key slot index 0 used to authenticate the image data
Verification index = 0
# Authenticate Start Address, Offset, Length and file
Blocks = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx"

0
doc/imx/hab/habv4/encrypted_boot.txt → doc/imx/habv4/guides/encrypted_boot.txt
View File

402
doc/imx/habv4/guides/mx6_mx7_secure_boot.txt Normal file
View File

@ -0,0 +1,402 @@
+=======================================================+
+ i.MX6, i.MX7 U-Boot Secure Boot guide using HABv4 +
+=======================================================+
1. HABv4 secure boot process
-----------------------------
This document describes a step-by-step procedure on how to sign and securely
boot an U-Boot image for non-SPL targets. It is assumed that the reader is
familiar with basic HAB concepts and with the PKI tree generation.
Details about HAB can be found in the application note AN4581[1] and in the
introduction_habv4.txt document.
1.1 Building a u-boot-dtb.imx image supporting secure boot
-----------------------------------------------------------
The U-Boot provides support to secure boot configuration and also provide
access to the HAB APIs exposed by the ROM vector table, the support is
enabled by selecting the CONFIG_SECURE_BOOT option.
When built with this configuration, the U-Boot provides extra functions for
HAB, such as the HAB status logs retrievement through the hab_status command
and support for extending the root of trust.
The U-Boot also correctly pads the final image by aligning to the next 0xC00
address, so the CSF signature data generated by CST can be concatenated to
image.
The diagram below illustrate a signed u-boot-dtb.imx image layout:
------- +-----------------------------+ <-- *start
^ | Image Vector Table |
| +-----------------------------+ <-- *boot_data
| | Boot Data |
| +-----------------------------+ <-- *dcd
| | DCD Table |
| +-----------------------------+
Signed | | Padding |
Data | +-----------------------------+ <-- *entry
| | |
| | |
| | u-boot-dtb.bin |
| | |
| | |
| +-----------------------------+
v | Padding |
------- +-----------------------------+ <-- *csf
| |
| Command Sequence File (CSF) |
| |
+-----------------------------+
| Padding (optional) |
+-----------------------------+
1.2 Enabling the secure boot support
-------------------------------------
The first step is to generate an U-Boot image supporting the HAB features
mentioned above, this can be achieved by adding CONFIG_SECURE_BOOT to the
build configuration:
- Defconfig:
CONFIG_SECURE_BOOT=y
- Kconfig:
ARM architecture -> Support i.MX HAB features
1.3 Creating the CSF description file
--------------------------------------
The CSF contains all the commands that the HAB executes during the secure
boot. These commands instruct the HAB on which memory areas of the image
to authenticate, which keys to install, use and etc.
CSF examples are available under doc/imx/habv4/csf_examples/ directory.
A build log containing the "Authenticate Data" parameters is available after
the U-Boot build, the example below is a log for mx7dsabresd_defconfig target:
- mkimage build log:
$ cat u-boot-dtb.imx.log
Image Type: Freescale IMX Boot Image
Image Ver: 2 (i.MX53/6/7 compatible)
Mode: DCD
Data Size: 667648 Bytes = 652.00 KiB = 0.64 MiB
Load Address: 877ff420
Entry Point: 87800000
HAB Blocks: 0x877ff400 0x00000000 0x0009ec00
^^^^^^^^^^ ^^^^^^^^^^ ^^^^^^^^^^
| | |
| | ------- (1)
| |
| ------------------ (2)
|
----------------------------- (3)
(1) Size of area in file u-boot-dtb.imx to sign.
This area should include the IVT, the Boot Data the DCD
and the U-Boot itself.
(2) Start of area in u-boot-dtb.imx to sign.
(3) Start of area in RAM to authenticate.
- In "Authenticate Data" CSF command users can copy and past the output
addresses:
Block = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx"
1.4 Signing the U-Boot binary
------------------------------
The CST tool is used for singing the U-Boot binary and generating a CSF binary,
users should input the CSF description file created in the step above and
should receive a CSF binary, which contains the CSF commands, SRK table,
signatures and certificates.
- Create CSF binary file:
$ ./cst -i csf_uboot.txt -o csf_uboot.bin
- Append CSF signature to the end of U-Boot image:
$ cat u-boot-dtb.imx csf_uboot.bin > u-boot-signed.imx
The u-boot-signed.imx is the signed binary and should be flashed into the boot
media.
- Flash signed U-Boot binary:
$ sudo dd if=u-boot-signed.imx of=/dev/sd<x> bs=1K seek=1 && sync
1.5 Programming SRK Hash
-------------------------
As explained in AN4581[1] and in introduction_habv4.txt document the SRK Hash
fuse values are generated by the srktool and should be programmed in the
SoC SRK_HASH[255:0] fuses.
Be careful when programming these values, as this data is the basis for the
root of trust. An error in SRK Hash results in a part that does not boot.
The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs.
- Dump SRK Hash fuses values in host machine:
$ hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin
0x20593752
0x6ACE6962
0x26E0D06C
0xFC600661
0x1240E88F
0x1209F144
0x831C8117
0x1190FD4D
- Program SRK_HASH[255:0] fuses, using i.MX6 series as example:
=> fuse prog 3 0 0x20593752
=> fuse prog 3 1 0x6ACE6962
=> fuse prog 3 2 0x26E0D06C
=> fuse prog 3 3 0xFC600661
=> fuse prog 3 4 0x1240E88F
=> fuse prog 3 5 0x1209F144
=> fuse prog 3 6 0x831C8117
=> fuse prog 3 7 0x1190FD4D
The table below lists the SRK_HASH bank and word according to the i.MX device:
+-------------------+---------------+---------------+---------------+
| | i.MX6 Series | i.MX7D/S | i.MX7ULP |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[31:00] | bank 3 word 0 | bank 6 word 0 | bank 5 word 0 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[63:32] | bank 3 word 1 | bank 6 word 1 | bank 5 word 1 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[95:64] | bank 3 word 2 | bank 6 word 2 | bank 5 word 2 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[127:96] | bank 3 word 3 | bank 6 word 3 | bank 5 word 3 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[159:128] | bank 3 word 4 | bank 7 word 0 | bank 5 word 4 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[191:160] | bank 3 word 5 | bank 7 word 1 | bank 5 word 5 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[223:192] | bank 3 word 6 | bank 7 word 2 | bank 5 word 6 |
+-------------------+---------------+---------------+---------------+
| SRK_HASH[255:224] | bank 3 word 7 | bank 7 word 3 | bank 5 word 7 |
+-------------------+---------------+---------------+---------------+
1.6 Verifying HAB events
-------------------------
The next step is to verify that the signature attached to U-Boot is
successfully processed without errors. HAB generates events when processing
the commands if it encounters issues.
The hab_status U-Boot command call the hab_report_event() and hab_status()
HAB API functions to verify the processor security configuration and status.
This command displays any events that were generated during the process.
Prior to closing the device users should ensure no HAB events were found, as
the example below:
- Verify HAB events:
=> hab_status
Secure boot disabled
HAB Configuration: 0xf0, HAB State: 0x66
No HAB Events Found!
1.7 Closing the device
-----------------------
After the device successfully boots a signed image without generating any HAB
events, it is safe to close the device. This is the last step in the HAB
process, and is achieved by programming the SEC_CONFIG[1] fuse bit.
Once the fuse is programmed, the chip does not load an image that has not been
signed using the correct PKI tree.
- Program SEC_CONFIG[1] fuse, using i.MX6 series as example:
=> fuse prog 0 6 0x00000002
The table below list the SEC_CONFIG[1] bank and word according to the i.MX
device:
+--------------+-----------------+------------+
| Device | Bank and Word | Value |
+--------------+-----------------+------------+
| i.MX6 Series | bank 0 word 6 | 0x00000002 |
+--------------+-----------------+------------+
| i.MX7D/S | bank 1 word 3 | 0x02000000 |
+--------------+-----------------+------------+
| i.MX7ULP | bank 29 word 6 | 0x80000000 |
+--------------+-----------------+------------+
1.8 Completely secure the device
---------------------------------
Additional fuses can be programmed for completely secure the device, more
details about these fuses and their possible impact can be found at AN4581[1].
- Program SRK_LOCK, using i.MX6 series as example:
=> fuse prog 0 0 0x4000
- Program DIR_BT_DIS, using i.MX6 series as example:
=> fuse prog 0 6 0x8
- Program SJC_DISABLE, using i.MX6 series as example:
=> fuse prog 0 6 0x100000
- JTAG_SMODE, using i.MX6 series as example:
=> fuse prog 0 6 0xC00000
The table below list the SRK_LOCK, DIR_BT_DIS, SJC_DISABLE, and JTAG_SMODE bank
and word according to the i.MX device:
+--------------+---------------+------------+
| Device | Bank and Word | Value |
+--------------+---------------+------------+
| SRK_LOCK |
+-------------------------------------------+
| i.MX6 Series | bank 0 word 0 | 0x00004000 |
+--------------+---------------+------------+
| i.MX7D/S | bank 0 word 0 | 0x00000200 |
+--------------+---------------+------------+
| i.MX7ULP | bank 1 word 1 | 0x00000080 |
+--------------+---------------+------------+
| DIR_BT_DIS |
+-------------------------------------------+
| i.MX6 Series | bank 0 word 6 | 0x00000008 |
+--------------+---------------+------------+
| i.MX7D/S | bank 1 word 3 | 0x08000000 |
+--------------+---------------+------------+
| i.MX7ULP | bank 1 word 1 | 0x00002000 |
+--------------+---------------+------------+
| SJC_DISABLE |
+-------------------------------------------+
| i.MX6 Series | bank 0 word 6 | 0x00100000 |
+--------------+---------------+------------+
| i.MX7D/S | bank 1 word 3 | 0x00200000 |
+--------------+---------------+------------+
| i.MX7ULP | bank 1 word 1 | 0x00000020 |
+--------------+---------------+------------+
| JTAG_SMODE |
+-------------------------------------------+
| i.MX6 Series | bank 0 word 6 | 0x00C00000 |
+--------------+---------------+------------+
| i.MX7D/S | bank 1 word 3 | 0x00C00000 |
+--------------+---------------+------------+
| i.MX7ULP | bank 1 word 1 | 0x000000C0 |
+--------------+---------------+------------+
2. Extending the root of trust
-------------------------------
The High Assurance Boot (HAB) code located in the on-chip ROM provides an
Application Programming Interface (API) making it possible to call back
into the HAB code for authenticating additional boot images.
The U-Boot supports this feature and can be used to authenticate the Linux
Kernel Image.
The process of signing an additional image is similar to the U-Boot.
The diagram below illustrate the zImage layout:
------- +-----------------------------+ <-- *load_address
^ | |
| | |
| | |
| | |
| | zImage |
Signed | | |
Data | | |
| | |
| +-----------------------------+
| | Padding Next Boundary |
| +-----------------------------+ <-- *ivt
v | Image Vector Table |
------- +-----------------------------+ <-- *csf
| |
| Command Sequence File (CSF) |
| |
+-----------------------------+
| Padding (optional) |
+-----------------------------+
2.1 Padding the image
----------------------
The zImage must be padded to the next boundary address (0x1000), for instance
if the image size is 0x649920 it must be padded to 0x64A000.
The tool objcopy can be used for padding the image.
- Pad the zImage:
$ objcopy -I binary -O binary --pad-to 0x64A000 --gap-fill=0x00 \
zImage zImage_pad.bin
2.2 Generating Image Vector Table
----------------------------------
The HAB code requires an Image Vector Table (IVT) for determining the image
length and the CSF location. Since zImage does not include an IVT this has
to be manually created and appended to the end of the padded zImage, the
script genIVT.pl in script_examples directory can be used as reference.
- Generate IVT:
$ genIVT.pl
Note: The load Address may change depending on the device.
- Append the ivt.bin at the end of the padded zImage:
$ cat zImage_pad.bin ivt.bin > zImage_pad_ivt.bin
2.3 Signing the image
----------------------
A CSF file has to be created to sign the image. HAB does not allow to change
the SRK once the first image is authenticated, so the same SRK key used in
U-Boot must be used when extending the root of trust.
CSF examples are available in ../csf_examples/additional_images/
directory.
- Create CSF binary file:
$ ./cst --i csf_additional_images.txt --o csf_zImage.bin
- Attach the CSF binary to the end of the image:
$ cat zImage_pad_ivt.bin csf_zImage.bin > zImage_signed.bin
2.4 Verifying HAB events
-------------------------
The U-Boot includes the hab_auth_img command which can be used for
authenticating and troubleshooting the signed image, zImage must be
loaded at the load address specified in the IVT.
- Authenticate additional image:
=> hab_auth_img <Load Address> <Image Size> <IVT Offset>
If no HAB events were found the zImage is successfully signed.
References:
[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using
HABv4" - Rev 2.

181
doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt Normal file
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@ -0,0 +1,181 @@
+===============================================================+
+ i.MX6, i.MX7 U-Boot HABv4 Secure Boot guide for SPL targets +
+===============================================================+
1. HABv4 secure boot process
-----------------------------
This document is an addendum of mx6_mx7_secure_boot.txt guide describing a
step-by-step procedure on how to sign and securely boot an U-Boot image for
SPL targets.
Details about HAB can be found in the application note AN4581[1] and in the
introduction_habv4.txt document.
1.1 Building a SPL target supporting secure boot
-------------------------------------------------
The U-Boot provides Second Program Loader (SPL) support which generates two
final images, SPL and U-Boot proper. The HABv4 can be used to authenticate
both binaries.
Out of reset the ROM code authenticates the SPL which is responsible for
initializing essential features such as DDR, UART, PMIC and clock
enablement. Once the DDR is available, the SPL code loads the U-Boot proper
image to its specific execution address and call the HAB APIs to extend the
root of trust.
The U-Boot provides support to secure boot configuration and also provide
access to the HAB APIs exposed by the ROM vector table, the support is
enabled by selecting the CONFIG_SECURE_BOOT option.
When built with this configuration the U-Boot correctly pads the final SPL
image by aligning to the next 0xC00 address, so the CSF signature data
generated by CST can be concatenated to the image.
The U-Boot also append an Image Vector Table (IVT) in the final U-Boot proper
binary (u-boot-ivt.img) so it can be used by HAB API in a post ROM stage.
The diagram below illustrate a signed SPL image layout:
------- +-----------------------------+ <-- *start
^ | Image Vector Table |
| +-----------------------------+ <-- *boot_data
| | Boot Data |
| +-----------------------------+
Signed | | Padding |
Data | +-----------------------------+ <-- *entry
| | |
| | SPL |
| | |
| +-----------------------------+
v | Padding |
------- +-----------------------------+ <-- *csf
| |
| Command Sequence File (CSF) |
| |
+-----------------------------+
| Padding (optional) |
+-----------------------------+
The diagram below illustrate a signed u-boot-ivt.img image layout:
------- +-----------------------------+ <-- *load_address
^ | |
| | |
| | u-boot.img |
Signed | | |
Data | | |
| +-----------------------------+
| | Padding Next Boundary |
| +-----------------------------+ <-- *ivt
v | Image Vector Table |
------- +-----------------------------+ <-- *csf
| |
| Command Sequence File (CSF) |
| |
+-----------------------------+
| Padding (optional) |
+-----------------------------+
1.2 Enabling the secure boot support
-------------------------------------
The first step is to generate an U-Boot image supporting the HAB features
mentioned above, this can be achieved by adding CONFIG_SECURE_BOOT to the
build configuration:
- Defconfig:
CONFIG_SECURE_BOOT=y
- Kconfig:
ARM architecture -> Support i.MX HAB features
1.3 Creating the CSF description file
--------------------------------------
The CSF contains all the commands that the HAB executes during the secure
boot. These commands instruct the HAB code on which memory areas of the image
to authenticate, which keys to install, use and etc.
CSF examples are available under doc/imx/habv4/csf_examples/ directory.
Build logs containing the "Authenticate Data" parameters are available after
the U-Boot build, the example below is a log for mx6sabresd_defconfig target:
- SPL build log:
$ cat SPL.log
Image Type: Freescale IMX Boot Image
Image Ver: 2 (i.MX53/6/7 compatible)
Mode: DCD
Data Size: 69632 Bytes = 68.00 KiB = 0.07 MiB
Load Address: 00907420
Entry Point: 00908000
HAB Blocks: 0x00907400 0x00000000 0x0000ec00
- u-boot-ivt.img build log:
$ cat u-boot-ivt.img.log
Image Name: U-Boot 2019.01-00003-g78ee492eb3
Created: Mon Jan 14 17:58:10 2019
Image Type: ARM U-Boot Firmware with HABv4 IVT (uncompressed)
Data Size: 458688 Bytes = 447.94 KiB = 0.44 MiB
Load Address: 17800000
Entry Point: 00000000
HAB Blocks: 0x177fffc0 0x0000 0x0006e020
As explained in section above the SPL is first authenticated by the ROM code
and the root of trust is extended to the U-Boot image, hence two CSF files are
necessary to completely sign a bootloader image.
In "Authenticate Data" CSF command users can copy and past the output
addresses, the csf_uboot.txt can be used as example:
- In csf_SPL.txt:
Block = 0x00907400 0x00000000 0x0000ec00 "SPL"
- In csf_uboot-ivt.txt:
Block = 0x177fffc0 0x0000 0x0006e020 "u-boot-ivt.img"
1.4 Signing the images
-----------------------
The CST tool is used for singing the U-Boot binary and generating a CSF binary,
users should input the CSF description file created in the step above and
receive a CSF binary, which contains the CSF commands, SRK table, signatures
and certificates.
- Create SPL CSF binary file:
$ ./cst -i csf_SPL.txt -o csf_SPL.bin
- Append CSF signature to the end of SPL image:
$ cat SPL csf_SPL.bin > SPL-signed
- Create U-Boot proper CSF binary file:
$ ./cst -i csf_uboot-ivt.txt -o csf_uboot-ivt.bin
- Append CSF signature to the end of U-Boot proper image:
$ cat u-boot-ivt.img csf_uboot-ivt.bin > u-boot-signed.img
The bootloader is signed and can be flashed into the boot media.
1.5 Closing the device
-----------------------
The procedure for closing the device is similar as in Non-SPL targets, for a
complete procedure please refer to section "1.5 Programming SRK Hash" in
mx6_mx7_secure_boot.txt document available under doc/imx/habv4/guides/
directory.
References:
[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using
HABv4" - Rev 2.

262
doc/imx/habv4/introduction_habv4.txt Normal file
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@ -0,0 +1,262 @@
+=======================================================+
+ i.MX Secure and Encrypted Boot using HABv4 +
+=======================================================+
1. Introduction
----------------
The i.MX family of applications processors provides the High Assurance Boot
(HAB) feature in the on-chip ROM. The ROM is responsible for loading the
initial program image (U-Boot) from the boot media and HAB enables the ROM
to authenticate and/or decrypt the program image by using cryptography
operations.
This feature is supported in i.MX 50, i.MX 53, i.MX 6, i.MX 7 series and
i.MX 8M, i.MX 8MM devices.
Step-by-step guides are available under doc/imx/habv4/guides/ directory,
users familiar with HAB and CST PKI tree generation should refer to these
documents instead.
1.1 The HABv4 Secure Boot Architecture
---------------------------------------
The HABv4 secure boot feature uses digital signatures to prevent unauthorized
software execution during the device boot sequence. In case a malware takes
control of the boot sequence, sensitive data, services and network can be
impacted.
The HAB authentication is based on public key cryptography using the RSA
algorithm in which image data is signed offline using a series of private
keys. The resulting signed image data is then verified on the i.MX processor
using the corresponding public keys. The public keys are included in the CSF
binary and the SRK Hash is programmed in the SoC fuses for establishing the
root of trust.
The diagram below illustrate the secure boot process overview:
Host PC + CST i.MX + HAB
+----------+ +----------+
---> | U-Boot | | Compare |
| +----------+ +----------+
| | ^ ^
| v Reference / \ Generated
| +----------+ Hash / \ Hash
| | Hash | Private / \
| +----------+ Key / \
| | | +----------+ +----------+
| v | | Verify | | Hash |
| +----------+ | +----------+ +----------+
| | Sign | <--- SRK ^ ^
| +----------+ HASH \ /
| | | CSF \ / U-Boot
| v v \ /
| +----------+ +----------+ +----------+
| | U-Boot | | | | U-Boot |
---> | + | -----> | i.MX | -----> | + |
| CSF | | | | CSF |
+----------+ +----------+ +----------+
The U-Boot image to be programmed into the boot media needs to be properly
constructed i.e. it must contain a proper Command Sequence File (CSF).
The CSF is a binary data structure interpreted by the HAB to guide
authentication process, this is generated by the Code Signing Tool[1].
The CSF structure contains the commands, SRK table, signatures and
certificates.
Details about the Secure Boot and Code Signing Tool (CST) can be found in
the application note AN4581[2] and in the secure boot guides.
1.2 The HABv4 Encrypted Boot Architecture
------------------------------------------
The HAB Encrypted Boot feature available in CAAM supported devices adds an
extra security operation to the bootloading sequence. It uses cryptographic
techniques (AES-CCM) to obscure the U-Boot data, so it cannot be seen or used
by unauthorized users. This mechanism protects the U-Boot code residing on
flash or external memory and also ensures that the final image is unique
per device.
The process can be divided into two protection mechanisms. The first mechanism
is the bootloader code encryption which provides data confidentiality and the
second mechanism is the digital signature, which authenticates the encrypted
image.
Keep in mind that the encrypted boot makes use of both mechanisms whatever the
order is (sign and then encrypt, or encrypt and then sign), both operations
can be applied on the same region with exception of the U-Boot Header (IVT,
boot data and DCD) which can only be signed, not encrypted.
The diagram below illustrate the encrypted boot process overview:
Host PC + CST i.MX + HAB
+------------+ +--------------+
| U-Boot | | U-Boot |
+------------+ +--------------+
| ^
| |
v DEK +--------------+
+------------+ | ----> | Decrypt |
| Encrypt | <--- | +--------------+
+------------+ DEK | ^
| | |
| Private | |
v Key +------+ +--------------+
+------------+ | | CAAM | | Authenticate |
| Sign | <--- +------+ +--------------+
+------------+ DEK ^ ^
| + OTPMK DEK \ / U-Boot
| | Blob \ / + CSF
v v \ /
+------------+ +----------+ +------------+
| Enc U-Boot | | | | Enc U-Boot |
| + CSF | ----> | i.MX | -------> | + CSF |
| + DEK Blob | | | | + DEK Blob |
+------------+ +----------+ +------------+
^ |
| |
---------------------
DEK Blob
(CAAM)
The Code Signing Tool automatically generates a random AES Data Encryption Key
(DEK) when encrypting an image. This key is used in both encrypt and decrypt
operations and should be present in the final image structure encapsulated
by a CAAM blob.
The OTP Master Key (OTPMK) is used to encrypt and wrap the DEK in a blob
structure. The OTPMK is unique per device and can be accessed by CAAM only.
To further add to the security of the DEK, the blob is decapsulated and
decrypted inside a secure memory partition that can only be accessed by CAAM.
During the design of encrypted boot using DEK blob, it is necessary to inhibit
any modification or replacement of DEK blob with a counterfeit one allowing
execution of malicious code. The PRIBLOB setting in CAAM allows secure boot
software to have its own private blobs that cannot be decapsulated or
encapsulated by any other user code, including any software running in trusted
mode.
Details about DEK Blob generation and PRIBLOB setting can be found in the
encrypted boot guide and application note AN12056[3] .
2. Generating a PKI tree
-------------------------
The first step is to generate the private keys and public keys certificates.
The HAB architecture is based in a Public Key Infrastructure (PKI) tree.
The Code Signing Tools package contains an OpenSSL based key generation script
under keys/ directory. The hab4_pki_tree.sh script is able to generate a PKI
tree containing up to 4 Super Root Keys (SRK) as well as their subordinated
IMG and CSF keys.
A new PKI tree can be generated by following the example below:
- Generating 2048-bit PKI tree on CST v3.1.0:
$ ./hab4_pki_tree.sh
...
Do you want to use an existing CA key (y/n)?: n
Do you want to use Elliptic Curve Cryptography (y/n)?: n
Enter key length in bits for PKI tree: 2048
Enter PKI tree duration (years): 5
How many Super Root Keys should be generated? 4
Do you want the SRK certificates to have the CA flag set? (y/n)?: y
The diagram below illustrate the PKI tree:
+---------+
| CA |
+---------+
|
|
---------------------------------------------------
| | | |
| | | |
v v v v
+--------+ +--------+ +--------+ +--------+
| SRK1 | | SRK2 | | SRK3 | | SRK4 |
+--------+ +--------+ +--------+ +--------+
/ \ / \ / \ / \
v v v v v v v v
+----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+
|CSF1| |IMG1| |CSF2| |IMG2| |CSF3| |IMG3| |CSF4| |IMG4|
+----+ +----+ +----+ +----+ +----+ +----+ +----+ +----+
After running the script users can check the private keys under keys/ directory
and their respective X.509v3 public key certificates under crts/ directory.
Those files will be used during the signing and authentication process.
2.1 Generating a fast authentication PKI tree
----------------------------------------------
Starting in HAB v4.1.2 users can use a single SRK key to authenticate the both
CSF and IMG contents. This reduces the number of key pair authentications that
must occur during the ROM/HAB boot stage, thus providing a faster boot process.
The script hab4_pki_tree.sh is also able to generate a Public Key Infrastructure
(PKI) tree which only contains SRK Keys, users should not set the CA flag when
generating the SRK certificates.
- Generating 2048-bit fast authentication PKI tree on CST v3.1.0:
$ ./hab4_pki_tree.sh
...
Do you want to use an existing CA key (y/n)?: n
Do you want to use Elliptic Curve Cryptography (y/n)?: n
Enter key length in bits for PKI tree: 2048
Enter PKI tree duration (years): 5
How many Super Root Keys should be generated? 4
Do you want the SRK certificates to have the CA flag set? (y/n)?: n
The diagram below illustrate the PKI tree generated:
+---------+
| CA |
+---------+
|
|
---------------------------------------------------
| | | |
| | | |
v v v v
+--------+ +--------+ +--------+ +--------+
| SRK1 | | SRK2 | | SRK3 | | SRK4 |
+--------+ +--------+ +--------+ +--------+
2.2 Generating a SRK Table and SRK Hash
----------------------------------------
The next step is to generated the SRK Table and its respective SRK Table Hash
from the SRK public key certificates created in one of the steps above.
In the HAB architecture, the SRK Table is included in the CSF binary and the
SRK Hash is programmed in the SoC SRK_HASH[255:0] fuses.
On the target device during the authentication process the HAB code verify the
SRK Table against the SoC SRK_HASH fuses, in case the verification success the
root of trust is established and the HAB code can progress with the image
authentication.
The srktool can be used for generating the SRK Table and its respective SRK
Table Hash.
- Generating SRK Table and SRK Hash in Linux 64-bit machines:
$ ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e \
SRK_1_2_3_4_fuse.bin -d sha256 -c \
SRK1_sha256_2048_65537_v3_ca_crt.pem,\
SRK2_sha256_2048_65537_v3_ca_crt.pem,\
SRK3_sha256_2048_65537_v3_ca_crt.pem,\
SRK4_sha256_2048_65537_v3_ca_crt.pem
The SRK_1_2_3_4_table.bin and SRK_1_2_3_4_fuse.bin files can be used in further
steps as explained in HAB guides available under doc/imx/habv4/guides/
directory.
References:
[1] CST: i.MX High Assurance Boot Reference Code Signing Tool.
[2] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using
HABv4" - Rev 2.
[3] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" - Rev. 1

12
doc/imx/habv4/script_examples/genIVT.pl Normal file
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@ -0,0 +1,12 @@
#! /usr/bin/perl -w
use strict;
open(my $out, '>:raw', 'ivt.bin') or die "Unable to open: $!";
print $out pack("V", 0x412000D1); # Signature
print $out pack("V", 0x80800000); # Load Address (*load_address)
print $out pack("V", 0x0); # Reserved
print $out pack("V", 0x0); # DCD pointer
print $out pack("V", 0x0); # Boot Data
print $out pack("V", 0x80EEA000); # Self Pointer (*ivt)
print $out pack("V", 0x80EEA020); # CSF Pointer (*csf)
print $out pack("V", 0x0); # Reserved
close($out);

8
drivers/mmc/fsl_esdhc.c
View File

@ -804,7 +804,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
case MMC_SIGNAL_VOLTAGE_330:
if (priv->vs18_enable)
return -EIO;
#ifdef CONFIG_DM_REGULATOR
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
ret = regulator_set_value(priv->vqmmc_dev, 3300000);
if (ret) {
@ -823,7 +823,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
return -EAGAIN;
case MMC_SIGNAL_VOLTAGE_180:
#ifdef CONFIG_DM_REGULATOR
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
ret = regulator_set_value(priv->vqmmc_dev, 1800000);
if (ret) {
@ -1442,7 +1442,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
int node = dev_of_offset(dev);
struct esdhc_soc_data *data =
(struct esdhc_soc_data *)dev_get_driver_data(dev);
#ifdef CONFIG_DM_REGULATOR
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
#endif
fdt_addr_t addr;
@ -1500,7 +1500,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->vs18_enable = 0;
#ifdef CONFIG_DM_REGULATOR
#if CONFIG_IS_ENABLED(DM_REGULATOR)
/*
* If emmc I/O has a fixed voltage at 1.8V, this must be provided,
* otherwise, emmc will work abnormally.

11
drivers/mtd/nand/raw/mxs_nand.c
View File

@ -1092,7 +1092,7 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
/*
* Initializes the NFC hardware.
*/
int mxs_nand_init_dma(struct mxs_nand_info *info)
static int mxs_nand_init_dma(struct mxs_nand_info *info)
{
int i = 0, j, ret = 0;
@ -1163,6 +1163,12 @@ int mxs_nand_init_spl(struct nand_chip *nand)
nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
if (is_mx6sx() || is_mx7())
nand_info->max_ecc_strength_supported = 62;
else
nand_info->max_ecc_strength_supported = 40;
err = mxs_nand_alloc_buffers(nand_info);
if (err)
return err;
@ -1185,9 +1191,6 @@ int mxs_nand_init_spl(struct nand_chip *nand)
nand->ecc.read_page = mxs_nand_ecc_read_page;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.bytes = 9;
nand->ecc.size = 512;
nand->ecc.strength = 8;
return 0;
}

1
drivers/mtd/nand/raw/mxs_nand_spl.c
View File

@ -201,6 +201,7 @@ static int mxs_nand_init(void)
/* setup flash layout (does not scan as we override that) */
mtd->size = nand_chip.chipsize;
nand_chip.scan_bbt(mtd);
mxs_nand_setup_ecc(mtd);
return 0;
}

2
drivers/net/fec_mxc.c
View File

@ -1348,7 +1348,7 @@ static int fecmxc_probe(struct udevice *dev)
#ifdef CONFIG_DM_REGULATOR
if (priv->phy_supply) {
ret = regulator_autoset(priv->phy_supply);
ret = regulator_set_enable(priv->phy_supply, true);
if (ret) {
printf("%s: Error enabling phy supply\n", dev->name);
return ret;

10
drivers/net/phy/mv88e61xx.c
View File

@ -945,16 +945,16 @@ static int mv88e61xx_phy_config(struct phy_device *phydev)
continue;
}
res = genphy_config_aneg(phydev);
if (res < 0) {
printf("Error setting PHY %i autoneg\n", i);
continue;
}
res = phy_reset(phydev);
if (res < 0) {
printf("Error resetting PHY %i\n", i);
continue;
}
res = genphy_config_aneg(phydev);
if (res < 0) {
printf("Error setting PHY %i autoneg\n", i);
continue;
}
/* Return success if any PHY succeeds */
ret = 0;

13
drivers/serial/serial_mxc.c
View File

@ -138,13 +138,18 @@ struct mxc_uart {
u32 ts;
};
static void _mxc_serial_init(struct mxc_uart *base)
static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
{
writel(0, &base->cr1);
writel(0, &base->cr2);
while (!(readl(&base->cr2) & UCR2_SRST));
if (use_dte)
writel(0x404 | UCR3_ADNIMP, &base->cr3);
else
writel(0x704 | UCR3_ADNIMP, &base->cr3);
writel(0x704 | UCR3_ADNIMP, &base->cr3);
writel(0x8000, &base->cr4);
writel(0x2b, &base->esc);
@ -226,7 +231,7 @@ static int mxc_serial_tstc(void)
*/
static int mxc_serial_init(void)
{
_mxc_serial_init(mxc_base);
_mxc_serial_init(mxc_base, false);
serial_setbrg();
@ -271,7 +276,7 @@ static int mxc_serial_probe(struct udevice *dev)
{
struct mxc_serial_platdata *plat = dev->platdata;
_mxc_serial_init(plat->reg);
_mxc_serial_init(plat->reg, plat->use_dte);
return 0;
}
@ -367,7 +372,7 @@ static inline void _debug_uart_init(void)
{
struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
_mxc_serial_init(base);
_mxc_serial_init(base, false);
_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
CONFIG_BAUDRATE, false);
}

7
drivers/usb/host/ehci-mx6.c
View File

@ -404,6 +404,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
if (ret)
return ret;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
ret = regulator_set_enable(priv->vbus_supply,
(type == USB_INIT_DEVICE) ?
@ -413,6 +414,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
return ret;
}
}
#endif
if (type == USB_INIT_DEVICE)
return 0;
@ -514,15 +516,17 @@ static int ehci_usb_probe(struct udevice *dev)
priv->portnr = dev->seq;
priv->init_type = type;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
ret = device_get_supply_regulator(dev, "vbus-supply",
&priv->vbus_supply);
if (ret)
debug("%s: No vbus supply\n", dev->name);
#endif
ret = ehci_mx6_common_init(ehci, priv->portnr);
if (ret)
return ret;
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
ret = regulator_set_enable(priv->vbus_supply,
(type == USB_INIT_DEVICE) ?
@ -532,6 +536,7 @@ static int ehci_usb_probe(struct udevice *dev)
return ret;
}
}
#endif
if (priv->init_type == USB_INIT_HOST) {
setbits_le32(&ehci->usbmode, CM_HOST);

4
include/configs/imx6_logic.h
View File

@ -144,6 +144,8 @@
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
#define CONFIG_SYS_NAND_USE_FLASH_BBT
/* MTD device */
/* DMA stuff, needed for GPMI/MXS NAND support */
@ -162,7 +164,7 @@
/* Falcon Mode */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
#define CONFIG_SYS_SPL_ARGS_ADDR 0x15000000
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */