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Merge git://git.denx.de/u-boot-fsl-qoriq 

- DPAA2 fixes and DDR errata workaround for LS1021A
This commit is contained in:
Tom Rini 2019-03-15 11:58:17 -04:00
parent 821aa1916e 158097052a
commit 8303467e80
17 changed files with 117 additions and 56 deletions
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6
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -4,6 +4,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
@ -63,6 +64,11 @@ config SYS_CCI400_OFFSET
Offset for CCI400 base.
CCI400 base addr = CCSRBAR + CCI400_OFFSET
config SYS_FSL_ERRATUM_A008850
bool
help
Workaround for DDR erratum A008850
config SYS_FSL_ERRATUM_A008997
bool
help

44
arch/arm/cpu/armv7/ls102xa/soc.c
View File

@ -11,6 +11,7 @@
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <fsl_csu.h>
#include <fsl_ddr_sdram.h>
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@ -103,6 +104,41 @@ static void erratum_a009007(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
}
static void erratum_a008850_early(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
/* disable the re-ordering in DDRC */
out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
#endif
}
void erratum_a008850_post(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
/* enable the re-ordering in DDRC */
tmp = in_be32(&ddr->eor);
tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
out_be32(&ddr->eor, tmp);
#endif
}
void s_init(void)
{
}
@ -163,13 +199,6 @@ int arch_soc_init(void)
*/
out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
* terminate the barrier transaction. After DDR is initialized,
* allow barrier transaction to DDR again */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
}
/* Enable all the snoop signal for various masters */
@ -191,6 +220,7 @@ int arch_soc_init(void)
out_be32(&scfg->eddrtqcfg, 0x63b20042);
/* Erratum */
erratum_a008850_early();
erratum_a009008();
erratum_a009798();
erratum_a008997();

2
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
View File

@ -10,6 +10,8 @@ unsigned int get_soc_major_rev(void);
int arch_soc_init(void);
int ls102xa_smmu_stream_id_init(void);
void erratum_a008850_post(void);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void);
#endif

2
board/freescale/ls1021aiot/ls1021aiot.c
View File

@ -97,6 +97,8 @@ int dram_init(void)
ddrmc_init();
#endif
erratum_a008850_post();
gd->ram_size = DDR_SIZE;
return 0;
}

2
board/freescale/ls1021aqds/ddr.c
View File

@ -179,6 +179,8 @@ int fsl_initdram(void)
fsl_dp_resume();
#endif
erratum_a008850_post();
gd->ram_size = dram_size;
return 0;

3
board/freescale/ls1021aqds/ddr.h
View File

@ -5,6 +5,9 @@
#ifndef __DDR_H__
#define __DDR_H__
void erratum_a008850_post(void);
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;

30
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -200,10 +200,6 @@ int board_early_init_f(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
@ -240,10 +236,6 @@ void board_init_f(ulong dummy)
i2c_init_all();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
timer_init();
dram_init();
@ -420,22 +412,12 @@ int misc_init_r(void)
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
erratum_a009942_check_cpo();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
}
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@ -456,18 +438,6 @@ int board_init(void)
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
}
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif

2
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -222,6 +222,8 @@ int dram_init(void)
ddrmc_init();
#endif
erratum_a008850_post();
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)

38
board/freescale/lx2160a/eth_lx2160aqds.c
View File

@ -628,8 +628,9 @@ int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
{
char mdio_ioslot_str[] = "mdio@00";
char mdio_mux_str[] = "mdio-mux-0";
struct lx2160a_qds_mdio *priv;
u64 reg;
u32 phandle;
int offset, mux_val;
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
@ -643,15 +644,32 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
debug("real_bus_num = %d, ioslot = %d\n",
priv->realbusnum, priv->ioslot);
sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
if (priv->realbusnum == EMI1)
reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
else
reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
printf("%s node not found under node %s in device tree\n",
mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
printf("mdio@%llx node not found in device tree\n", reg);
return offset;
}
phandle = fdt_get_phandle(fdt, offset);
phandle = cpu_to_fdt32(phandle);
offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
&phandle, 4);
if (offset < 0) {
printf("mdio-mux-%d node not found in device tree\n",
priv->realbusnum == EMI1 ? 1 : 2);
return offset;
}
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
else
mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
@ -675,7 +693,9 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
if (*subnodeoffset <= 0) {
printf("Could not add subnode %s\n", phy_node_name);
printf("Could not add subnode %s inside node %s err = %s\n",
phy_node_name, fdt_get_name(fdt, offset, NULL),
fdt_strerror(*subnodeoffset));
return *subnodeoffset;
}
@ -779,7 +799,6 @@ int fdt_fixup_board_phy(void *fdt)
}
if (dpmac_id == NUM_WRIOP_PORTS)
continue;
ret = fdt_create_phy_node(fdt, offset, i,
&subnodeoffset,
phy_dev, phandle);
@ -792,6 +811,11 @@ int fdt_fixup_board_phy(void *fdt)
fdt_del_node(fdt, subnodeoffset);
break;
}
/* calculate offset again as new node addition may have
* changed offset;
*/
offset = fdt_get_ioslot_offset(fdt, mii_dev,
fpga_offset);
phandle++;
}

26
drivers/net/fsl-mc/mc.c
View File

@ -28,6 +28,7 @@
#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
#define MC_BOOT_ENV_VAR "mcinitcmd"
#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
DECLARE_GLOBAL_DATA_PTR;
static int mc_memset_resv_ram;
@ -421,9 +422,11 @@ static int mc_fixup_dpc(u64 dpc_addr)
/* fixup MAC addresses for dpmac ports */
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
if (nodeoffset < 0)
return 0;
goto out;
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
out:
flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
return err;
@ -680,13 +683,20 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
size_t mc_ram_size = mc_get_dram_block_size();
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
if (mc_ram_num_256mb_blocks >= 0xff) {
error = -EINVAL;
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
mc_ram_size);
goto out;
}
/*
* To support 128 MB DDR Size for MC
*/
if (mc_ram_num_256mb_blocks == 0)
mc_ram_num_256mb_blocks = 0xFF;
/*
* Management Complex cores should be held at reset out of POR.
* U-Boot should be the first software to touch MC. To be safe,
@ -727,8 +737,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
/*
* Tell MC what is the address range of the DRAM block assigned to it:
*/
reg_mcfbalr = (u32)mc_ram_addr |
(mc_ram_num_256mb_blocks - 1);
if (mc_ram_num_256mb_blocks < 0xFF) {
reg_mcfbalr = (u32)mc_ram_addr |
(mc_ram_num_256mb_blocks - 1);
} else {
reg_mcfbalr = (u32)mc_ram_addr |
(mc_ram_num_256mb_blocks);
}
out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(&mc_ccsr_regs->reg_mcfbahr,
(u32)(mc_ram_addr >> 32));
@ -878,7 +894,7 @@ unsigned long mc_get_dram_block_size(void)
"\' environment variable: %lu\n",
dram_block_size);
dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
}
}

4
drivers/net/ldpaa_eth/ls1088a.c
View File

@ -93,7 +93,7 @@ void fsl_rgmii_init(void)
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
@ -102,7 +102,7 @@ void fsl_rgmii_init(void)
#endif
#ifdef CONFIG_SYS_FSL_EC2
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;

4
drivers/net/ldpaa_eth/lx2160a.c
View File

@ -91,7 +91,7 @@ void fsl_rgmii_init(void)
& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
if (!ec)
if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
#endif
@ -100,7 +100,7 @@ void fsl_rgmii_init(void)
& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
if (!ec)
if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
#endif
}

2
include/configs/ls1021aiot.h
View File

@ -85,6 +85,8 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
/*
* Serial Port
*/

2
include/configs/ls1021atwr.h
View File

@ -104,6 +104,8 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR

2
include/configs/ls1088a_common.h
View File

@ -147,7 +147,7 @@ unsigned long long get_qixis_addr(void);
*/
#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
#define CONFIG_CMD_CACHE

2
include/configs/ls2080a_common.h
View File

@ -152,7 +152,7 @@ unsigned long long get_qixis_addr(void);
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */

2
include/configs/lx2160a_common.h
View File

@ -100,7 +100,7 @@
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
#endif
/* I2C bus multiplexer */