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some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
108 lines
3.1 KiB
C
108 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <phy.h>
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#include <fsl-mc/ldpaa_wriop.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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u32 dpmac_to_devdisr[] = {
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[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
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[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
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[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
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[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
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[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
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[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
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[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
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[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
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[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
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[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
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[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
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[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
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[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
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[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
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[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
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[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
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[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
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[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
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};
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static int is_device_disabled(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 devdisr2 = in_le32(&gur->devdisr2);
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return dpmac_to_devdisr[dpmac_id] & devdisr2;
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}
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void wriop_dpmac_disable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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void wriop_dpmac_enable(int dpmac_id)
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{
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
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}
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phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
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{
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enum srds_prtcl;
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if (is_device_disabled(dpmac_id + 1))
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return PHY_INTERFACE_MODE_NONE;
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if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
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return PHY_INTERFACE_MODE_SGMII;
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if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
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return PHY_INTERFACE_MODE_XGMII;
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if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
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return PHY_INTERFACE_MODE_25G_AUI;
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if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
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return PHY_INTERFACE_MODE_XLAUI;
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if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
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return PHY_INTERFACE_MODE_CAUI2;
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if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
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return PHY_INTERFACE_MODE_CAUI4;
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return PHY_INTERFACE_MODE_NONE;
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}
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#ifdef CONFIG_SYS_FSL_HAS_RGMII
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void fsl_rgmii_init(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 ec;
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#ifdef CONFIG_SYS_FSL_EC1
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ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
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& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
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ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
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if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
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wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
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#endif
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#ifdef CONFIG_SYS_FSL_EC2
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ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
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& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
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ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
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if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
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wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
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#endif
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}
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#endif
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