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Fixes for 2019.01 

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Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imx

Fixes for 2019.01
This commit is contained in:
Tom Rini 2019-01-10 09:28:16 -05:00
parent 43a6a1ec90 d4a0c09892
commit e5aa3f4d97
17 changed files with 51 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -123,7 +123,7 @@ F: drivers/spi/bcmstb_spi.c
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <fabio.estevam@nxp.com>
R: NXP Linux Team <linux-imx@nxp.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/

3
Makefile
View File

@ -1155,6 +1155,9 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
else
ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
U_BOOT_ITS := u-boot.its
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
U_BOOT_ITS_DEPS += u-boot-nodtb.bin
endif
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
U_BOOT_ITS_DEPS += u-boot
endif

5
arch/arm/include/asm/arch-vf610/imx-regs.h
View File

@ -200,7 +200,8 @@
#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8)
#define DDRMC_CR82_INT_MASK (1 << 28)
#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
@ -239,7 +240,7 @@
#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16)
#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16)
#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8)
#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8)
#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)

2
arch/arm/include/asm/arch-vf610/iomux-vf610.h
View File

@ -244,6 +244,8 @@ enum {
VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
};
#endif /* __IOMUX_VF610_H__ */

6
arch/arm/mach-imx/ddrmc-vf610.c
View File

@ -61,6 +61,8 @@ void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
VF610_PAD_DDR_WE__DDR_WE_B,
VF610_PAD_DDR_ODT1__DDR_ODT_0,
VF610_PAD_DDR_ODT0__DDR_ODT_1,
VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
VF610_PAD_DDR_RESETB,
};
@ -188,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
@ -231,6 +232,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
/* all inits done, start the DDR controller */
writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
while (!(readl(&ddrmr->cr[80]) && 0x100))
while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
udelay(10);
writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
}

2
arch/arm/mach-imx/imx8/cpu.c
View File

@ -573,7 +573,7 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
if (size < 100)
return -ENOSPC;
snprintf(buf, size, "CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n",
snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
plat->type, plat->rev, plat->name, plat->freq_mhz);
return 0;

4
arch/arm/mach-imx/imx8m/clock.c
View File

@ -250,9 +250,9 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
case OSC_25M_CLK:
return 25000000;
case OSC_27M_CLK:
return 25000000;
return 27000000;
case OSC_32K_CLK:
return 32000;
return 32768;
case ARM_PLL_CLK:
return decode_frac_pll(root_src);
case SYSTEM_PLL1_800M_CLK:

10
board/toradex/colibri_vf/colibri_vf.c
View File

@ -42,14 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define USB_CDET_GPIO 102
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* levelling */
{ DDRMC_CR97_WRLVL_EN, 97 },
{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
/* AXI */
{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
@ -88,7 +80,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
DDRMC_CR154_PAD_ZQ_MODE(1) |
DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
{ DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
{ DDRMC_CR158_TWR(6), 158 },
{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
DDRMC_CR161_TODTH_WR(2), 161 },

3
configs/colibri_vf_defconfig
View File

@ -23,11 +23,14 @@ CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y

8
configs/m53menlo_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
@ -33,6 +34,7 @@ CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_DATE=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4=y
@ -44,6 +46,11 @@ CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
CONFIG_FSL_ESDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXC=y
@ -58,5 +65,6 @@ CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_IMX_WATCHDOG=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

1
configs/tbs2910_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_TBS2910=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_PRE_CON_BUF_ADDR=0x7c000000

2
drivers/clk/imx/clk-imx8.c
View File

@ -18,6 +18,7 @@ struct imx8_clks {
const char *name;
};
#if CONFIG_IS_ENABLED(CMD_CLK)
static struct imx8_clks imx8_clk_names[] = {
{ IMX8QXP_A35_DIV, "A35_DIV" },
{ IMX8QXP_I2C0_CLK, "I2C0" },
@ -39,6 +40,7 @@ static struct imx8_clks imx8_clk_names[] = {
{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
};
#endif
static ulong imx8_clk_get_rate(struct clk *clk)
{

26
drivers/misc/imx8/scu.c
View File

@ -158,7 +158,7 @@ static int sc_ipc_write(struct mu_type *base, void *data)
static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
int tx_size, void *rx_msg, int rx_size)
{
struct imx8_scu *priv = dev_get_priv(dev);
struct imx8_scu *plat = dev_get_platdata(dev);
sc_err_t result;
int ret;
@ -166,11 +166,11 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
if (rx_msg && tx_msg != rx_msg)
printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
ret = sc_ipc_write(priv->base, tx_msg);
ret = sc_ipc_write(plat->base, tx_msg);
if (ret)
return ret;
if (!no_resp) {
ret = sc_ipc_read(priv->base, rx_msg);
ret = sc_ipc_read(plat->base, rx_msg);
if (ret)
return ret;
}
@ -182,24 +182,24 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
static int imx8_scu_probe(struct udevice *dev)
{
struct imx8_scu *priv = dev_get_priv(dev);
struct imx8_scu *plat = dev_get_platdata(dev);
fdt_addr_t addr;
debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = (struct mu_type *)addr;
plat->base = (struct mu_type *)addr;
/* U-Boot not enable interrupts, so need to enable RX interrupts */
mu_hal_init(priv->base);
mu_hal_init(plat->base);
gd->arch.scu_dev = dev;
device_probe(priv->clk);
device_probe(priv->pinclk);
device_probe(plat->clk);
device_probe(plat->pinclk);
return 0;
}
@ -211,7 +211,7 @@ static int imx8_scu_remove(struct udevice *dev)
static int imx8_scu_bind(struct udevice *dev)
{
struct imx8_scu *priv = dev_get_priv(dev);
struct imx8_scu *plat = dev_get_platdata(dev);
int ret;
struct udevice *child;
int node;
@ -227,7 +227,7 @@ static int imx8_scu_bind(struct udevice *dev)
if (ret)
return ret;
priv->clk = child;
plat->clk = child;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx8qxp-iomuxc");
@ -238,7 +238,7 @@ static int imx8_scu_bind(struct udevice *dev)
if (ret)
return ret;
priv->pinclk = child;
plat->pinclk = child;
return 0;
}
@ -261,6 +261,6 @@ U_BOOT_DRIVER(imx8_scu) = {
.bind = imx8_scu_bind,
.remove = imx8_scu_remove,
.ops = &imx8_scu_ops,
.priv_auto_alloc_size = sizeof(struct imx8_scu),
.platdata_auto_alloc_size = sizeof(struct imx8_scu),
.flags = DM_FLAG_PRE_RELOC,
};

4
drivers/misc/imx8/scu_api.c
View File

@ -169,7 +169,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
printf("%s: ctrl:%d resource:%d: res:%d\n",
__func__, ctrl, resource, RPC_R8(&msg));
if (!val)
if (val)
*val = RPC_U32(&msg, 0U);
return ret;
@ -194,7 +194,7 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev)
if (ret)
printf("%s: res:%d\n", __func__, RPC_R8(&msg));
if (!boot_dev)
if (boot_dev)
*boot_dev = RPC_U16(&msg, 0U);
}

3
include/configs/m53menlo.h
View File

@ -157,6 +157,9 @@
/* IIM Fuses */
#define CONFIG_FSL_IIM
/* Watchdog */
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
/*
* Boot Linux
*/

2
include/configs/tbs2910.h
View File

@ -122,6 +122,8 @@
#define CONFIG_ENV_OFFSET (384 * 1024)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \

2
tools/imx8image.c
View File

@ -968,7 +968,7 @@ int imx8image_copy_image(int outfd, struct image_tool_params *mparams)
fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version);
build_container(soc, sector_size, emmc_fastboot,
img_sp, false, fuse_version, sw_version, outfd);
img_sp, true, fuse_version, sw_version, outfd);
return 0;
}