ARM: rockchip: Add rv1108-elgin-r1 board support

Add the initial support for Elgin R1 board, which is based on the
RV1108 SoC and has the following features currently supported in
U-Boot:

- UART
- eMMC
- USB

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

arch/arm/dts/Makefile

@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3399-puma-ddr1600.dtb \
 	rk3399-puma-ddr1866.dtb \
 	rk3399-rock960.dtb \
+	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb
 dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxbb-nanopi-k2.dtb \

arch/arm/dts/rv1108-elgin-r1.dts

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+
+#include "rv1108.dtsi"
+
+/ {
+	model = "Elgin RV1108 R1 board";
+	compatible = "elgin,rv1108-elgin", "rockchip,rv1108";
+
+	memory@60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x08000000>;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+};
+
+&emmc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	disable-wp;
+	non-removable;
+	status = "okay";
+};
+
+&u2phy {
+	status = "okay";
+
+	u2phy_otg: otg-port {
+		status = "okay";
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb20_otg {
+	status = "okay";
+};

arch/arm/mach-rockchip/rv1108/Kconfig

@@ -17,6 +17,11 @@ config TARGET_EVB_RV1108
 	   * 10/100 Mbps Ethernet
 	   * camera interface compatible with imx323 / ov2710 / ov4689
 
+config TARGET_ELGIN_RV1108
+	bool "ELGIN_RV1108"
+	help
+	  RV1108 ELGIN is a board based on the Rockchip RV1108.
+
 config SYS_SOC
 	default "rockchip"
 
@@ -24,5 +29,6 @@ config SYS_MALLOC_F_LEN
 	default 0x400
 
 source board/rockchip/evb_rv1108/Kconfig
+source board/elgin/elgin_rv1108/Kconfig
 
 endif

board/elgin/elgin_rv1108/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_ELGIN_RV1108
+
+config SYS_BOARD
+	default "elgin_rv1108"
+
+config SYS_VENDOR
+	default "elgin"
+
+config SYS_CONFIG_NAME
+	default "elgin_rv1108"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif

board/elgin/elgin_rv1108/MAINTAINERS

@@ -0,0 +1,6 @@
+ELGIN-RV1108
+M:      Otavio Salvador <otavio@ossystems.com.br>
+S:      Maintained
+F:      board/elgin/elgin_rv1108
+F:      include/configs/elgin_rv1108.h
+F:      configs/elgin-rv1108_defconfig

board/elgin/elgin_rv1108/Makefile

@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= elgin_rv1108.o

board/elgin/elgin_rv1108/elgin_rv1108.c

@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C)Copyright 2016 Rockchip Electronics Co., Ltd
+ * Authors: Andy Yan <andy.yan@rock-chips.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fdtdec.h>
+#include <asm/arch/grf_rv1108.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+	int node;
+	struct rv1108_grf *grf;
+	enum {
+		GPIO3C3_SHIFT           = 6,
+		GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
+
+		GPIO3C2_SHIFT           = 4,
+		GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
+
+		GPIO2D2_SHIFT		= 4,
+		GPIO2D2_MASK		= 3 << GPIO2D2_SHIFT,
+		GPIO2D2_GPIO            = 0,
+		GPIO2D2_UART2_SOUT_M0,
+
+		GPIO2D1_SHIFT		= 2,
+		GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART2_SIN_M0,
+	};
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
+	grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+
+	/* Elgin board use UART2 m0 for debug*/
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D2_MASK | GPIO2D1_MASK,
+		     GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
+		     GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
+	rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
+
+	return 0;
+}
+
+#define MODEM_ENABLE_GPIO 111
+
+int board_init(void)
+{
+	gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
+	gpio_direction_output(MODEM_ENABLE_GPIO, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x8000000;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = 0x60000000;
+	gd->bd->bi_dram[0].size = 0x8000000;
+
+	return 0;
+}

configs/elgin-rv1108_defconfig

@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x60000000
+CONFIG_ROCKCHIP_RV1108=y
+CONFIG_TARGET_ELGIN_RV1108=y
+CONFIG_DEBUG_UART_BASE=0x10210000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GPIO=y
+CONFIG_RANDOM_UUID=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x62000000
+CONFIG_FASTBOOT_BUF_SIZE=0x08000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RV1108=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_BAUDRATE=1500000
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x110a
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_ERRNO_STR=y

include/configs/elgin_rv1108.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rv1108_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV	0
+
+#endif