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imx for 2019.01 

- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
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Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
This commit is contained in:
Tom Rini 2019-01-01 09:56:41 -05:00
parent 08337cd648 57d2beb91d
commit 522e035441
106 changed files with 8718 additions and 564 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Kconfig
View File

@ -251,6 +251,16 @@ config FIT
if FIT
config FIT_EXTERNAL_OFFSET
hex "Text Base"
default 0x0
help
This specifies a data offset in fit image.
The offset is from data payload offset to the beginning of
fit image header. When specifies a offset, specific data
could be put in the hole between data payload and fit image
header, such as CSF data on i.MX platform.
config FIT_ENABLE_SHA256_SUPPORT
bool "Support SHA256 checksum of FIT image contents"
default y

7
Makefile
View File

@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_mkfitimage = MKIMAGE $@
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_cat = CAT $@
@ -1207,6 +1207,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
ifeq ($(CONFIG_ARCH_IMX8M), y)
flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

4
arch/arm/Kconfig
View File

@ -694,7 +694,7 @@ config ARCH_IMX8
select DM
select OF_CONTROL
config ARCH_MX8M
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARM64
select DM
@ -1451,7 +1451,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig"
source "arch/arm/mach-imx/imx8/Kconfig"
source "arch/arm/mach-imx/mx8m/Kconfig"
source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"

4
arch/arm/Makefile
View File

@ -103,11 +103,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
libs-y += arch/arm/mach-imx/
endif
else
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610))
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
libs-y += arch/arm/mach-imx/
endif
endif

11
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
View File

@ -8,3 +8,14 @@ Freescale LayerScape with Chassis Generation 2
This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
for example LS1043A.
Watchdog support Overview
-------------------
Support watchdog driver for LSCH2. The driver is disabled in default.
You can enable it by setting CONFIG_IMX_WATCHDOG.
Use following config to set watchdog timeout, if this config is not defined,
the default timeout value is 128s which is the maximum. Set 10 seconds for
example:
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000
Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the
watchdog will not be fed in u-boot.

2
arch/arm/dts/Makefile
View File

@ -466,6 +466,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb-u-boot.dtb \
r8a7795-salvator-x-u-boot.dtb \

414
arch/arm/dts/fsl-imx8mq-evk.dts Normal file
View File

@ -0,0 +1,414 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;
#include "fsl-imx8mq.dtsi"
/ {
model = "Freescale i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
chosen {
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
pwmleds {
compatible = "pwm-leds";
ledpwm2 {
label = "PWM2";
pwms = <&pwm2 0 50000>;
max-brightness = <255>;
};
};
};
&iomuxc {
pinctrl-names = "default";
imx8mq-evk {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&lcdif {
status = "okay";
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
display0: display@0 {
bits-per-pixel = <24>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash0: n25q256a@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <6>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

6
arch/arm/dts/vf.dtsi
View File

@ -89,6 +89,12 @@
status = "disabled";
};
iomuxc: iomuxc@40048000 {
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
fsl,mux_mask = <0x700000>;
};
gpio0: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x400ff000 0x40>;

810
arch/arm/dts/vf610-pinfunc.h Normal file
View File

@ -0,0 +1,810 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_VF610_PINFUNC_H
#define __DTS_VF610_PINFUNC_H
/*
* The pin function ID for VF610 is a tuple of:
* <mux_reg input_reg mux_mode input_val>
*/
#define ALT0 0x0
#define ALT1 0x1
#define ALT2 0x2
#define ALT3 0x3
#define ALT4 0x4
#define ALT5 0x5
#define ALT6 0x6
#define ALT7 0x7
#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0
#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0
#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0
#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0
#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0
#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0
#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0
#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0
#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0
#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0
#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0
#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0
#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0
#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0
#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0
#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0
#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0
#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0
#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0
#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1
#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0
#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0
#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0
#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0
#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0
#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0
#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0
#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0
#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0
#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0
#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0
#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0
#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0
#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0
#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0
#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0
#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0
#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0
#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0
#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0
#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0
#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0
#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0
#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0
#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0
#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0
#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0
#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0
#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0
#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0
#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0
#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0
#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0
#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0
#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0
#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0
#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0
#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0
#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0
#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0
#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0
#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0
#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0
#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0
#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0
#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0
#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0
#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0
#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0
#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0
#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0
#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0
#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0
#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0
#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0
#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0
#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0
#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0
#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0
#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0
#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0
#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0
#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0
#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0
#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0
#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0
#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0
#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0
#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0
#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0
#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0
#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0
#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0
#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0
#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0
#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0
#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0
#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1
#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0
#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0
#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0
#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0
#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0
#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1
#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0
#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0
#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0
#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0
#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1
#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0
#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0
#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0
#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0
#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0
#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0
#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1
#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0
#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0
#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0
#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0
#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0
#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0
#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1
#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0
#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0
#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0
#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0
#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0
#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0
#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0
#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0
#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0
#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0
#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0
#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0
#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0
#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0
#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0
#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0
#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0
#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0
#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0
#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0
#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0
#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0
#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0
#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0
#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0
#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0
#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0
#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0
#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0
#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0
#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0
#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0
#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0
#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0
#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0
#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1
#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1
#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0
#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0
#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1
#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0
#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0
#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0
#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2
#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0
#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1
#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0
#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0
#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0
#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0
#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0
#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0
#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0
#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0
#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0
#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0
#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0
#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0
#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0
#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0
#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0
#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0
#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0
#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1
#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0
#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0
#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0
#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1
#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0
#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0
#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0
#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1
#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0
#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0
#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1
#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0
#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0
#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2
#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0
#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0
#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0
#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0
#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0
#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0
#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0
#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0
#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0
#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0
#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0
#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0
#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1
#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0
#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1
#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0
#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0
#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0
#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0
#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0
#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0
#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1
#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0
#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0
#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0
#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0
#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0
#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0
#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1
#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0
#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0
#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0
#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0
#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0
#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1
#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0
#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0
#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0
#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0
#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0
#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0
#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0
#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0
#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0
#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0
#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0
#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0
#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1
#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0
#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0
#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0
#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0
#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0
#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0
#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0
#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0
#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0
#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0
#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0
#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0
#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0
#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0
#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0
#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0
#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0
#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0
#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0
#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0
#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0
#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1
#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1
#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0
#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0
#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1
#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1
#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0
#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0
#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1
#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1
#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0
#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0
#define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0
#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1
#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0
#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0
#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1
#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2
#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0
#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0
#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1
#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0
#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2
#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0
#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0
#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0
#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1
#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0
#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0
#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0
#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0
#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0
#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1
#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0
#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2
#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0
#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0
#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0
#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0
#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0
#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1
#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0
#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0
#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0
#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0
#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0
#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0
#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0
#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0
#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0
#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0
#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0
#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0
#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0
#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0
#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0
#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0
#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0
#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0
#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0
#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1
#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0
#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0
#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0
#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0
#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0
#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0
#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0
#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0
#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0
#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0
#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0
#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0
#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0
#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0
#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0
#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0
#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0
#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0
#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0
#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1
#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0
#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1
#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0
#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0
#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0
#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0
#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0
#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1
#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0
#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1
#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0
#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0
#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0
#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0
#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0
#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0
#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0
#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0
#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0
#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0
#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0
#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0
#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0
#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0
#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0
#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0
#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0
#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0
#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0
#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2
#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0
#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0
#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0
#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0
#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0
#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0
#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2
#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0
#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0
#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0
#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0
#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0
#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2
#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0
#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0
#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0
#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0
#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0
#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2
#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0
#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0
#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0
#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2
#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0
#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0
#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0
#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0
#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0
#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2
#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0
#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0
#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0
#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0
#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0
#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0
#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0
#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0
#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0
#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0
#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0
#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0
#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1
#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0
#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0
#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0
#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0
#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0
#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0
#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0
#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0
#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0
#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0
#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0
#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0
#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1
#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0
#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0
#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0
#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0
#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1
#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0
#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0
#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0
#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0
#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0
#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0
#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0
#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0
#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0
#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0
#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1
#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0
#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0
#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0
#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0
#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0
#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0
#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0
#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0
#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0
#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0
#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0
#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0
#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0
#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0
#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0
#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0
#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0
#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0
#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0
#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0
#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0
#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0
#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0
#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0
#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0
#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0
#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0
#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0
#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0
#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2
#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1
#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0
#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0
#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0
#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0
#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0
#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2
#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1
#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0
#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0
#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0
#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0
#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0
#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0
#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0
#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1
#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0
#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0
#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0
#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0
#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0
#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2
#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0
#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0
#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0
#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0
#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0
#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0
#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0
#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0
#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0
#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0
#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0
#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0
#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0
#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0
#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0
#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0
#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0
#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0
#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0
#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0
#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0
#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0
#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0
#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0
#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0
#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0
#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0
#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0
#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0
#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0
#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0
#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0
#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0
#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0
#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0
#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0
#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0
#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0
#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0
#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0
#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0
#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0
#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0
#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0
#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0
#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0
#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0
#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0
#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0
#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0
#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0
#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0
#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0
#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0
#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0
#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1
#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0
#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0
#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0
#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0
#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0
#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0
#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0
#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0
#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0
#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0
#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0
#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0
#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0
#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0
#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0
#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0
#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0
#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0
#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0
#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0
#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0
#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0
#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0
#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0
#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0
#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0
#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0
#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0
#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0
#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0
#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0
#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0
#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0
#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0
#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0
#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0
#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0
#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0
#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0
#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0
#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0
#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0
#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0
#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0
#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0
#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0
#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0
#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0
#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0
#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0
#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0
#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0
#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0
#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0
#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0
#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0
#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0
#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0
#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0
#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0
#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0
#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0
#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0
#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0
#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0
#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0
#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0
#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0
#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0
#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0
#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0
#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0
#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0
#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0
#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0
#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0
#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0
#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0
#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0
#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0
#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0
#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0
#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0
#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0
#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0
#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0
#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0
#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0
#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0
#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0
#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0
#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0
#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0
#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3
#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0
#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0
#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0
#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0
#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3
#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0
#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0
#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0
#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0
#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0
#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0
#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0
#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0
#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0
#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0
#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0
#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0
#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0
#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0
#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0
#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0
#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0
#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0
#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0
#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0
#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0
#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0
#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0
#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0
#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0
#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0
#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0
#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3
#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0
#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0
#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0
#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0
#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3
#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
#endif

5
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -24,7 +24,7 @@
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_MX8MQ 0x82
#define MXC_CPU_IMX8MQ 0x82
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
@ -32,7 +32,7 @@
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define MXC_SOC_MX8M 0x80
#define MXC_SOC_IMX8M 0x80
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
@ -41,6 +41,7 @@
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
#define CHIP_REV_2_1 0x21
#define CHIP_REV_2_5 0x25
#define CHIP_REV_3_0 0x30

22
arch/arm/include/asm/arch-mx8m/clock.h → arch/arm/include/asm/arch-imx8m/clock.h
View File

@ -10,6 +10,8 @@
#include <linux/bitops.h>
#define MHZ(X) ((X) * 1000000UL)
enum pll_clocks {
ANATOP_ARM_PLL,
ANATOP_GPU_PLL,
@ -631,6 +633,26 @@ enum frac_pll_out_val {
FRAC_PLL_OUT_1600M,
};
#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
{ \
.clk = (_rate), \
.alt_root_sel = (_m), \
.alt_pre_div = (_p), \
.apb_root_sel = (_s), \
.apb_pre_div = (_k), \
}
struct dram_bypass_clk_setting {
ulong clk;
int alt_root_sel;
enum root_pre_div alt_pre_div;
int apb_root_sel;
enum root_pre_div apb_pre_div;
};
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
u32 imx_get_fecclk(void);
u32 imx_get_uartclk(void);
int clock_init(void);

4
arch/arm/include/asm/arch-mx8m/crm_regs.h → arch/arm/include/asm/arch-imx8m/crm_regs.h
View File

@ -3,7 +3,7 @@
* Copyright 2017 NXP
*/
#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
#define _ASM_ARCH_MX8M_CRM_REGS_H
#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
#define _ASM_ARCH_IMX8M_CRM_REGS_H
/* Dummy header, some imx-common code needs this file */
#endif

740
arch/arm/include/asm/arch-imx8m/ddr.h Normal file
View File

@ -0,0 +1,740 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
*/
#ifndef __ASM_ARCH_IMX8M_DDR_H
#define __ASM_ARCH_IMX8M_DDR_H
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/ddr.h>
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR_0 0x3f400000
#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
struct ddrc_freq {
u32 res0[8];
u32 derateen;
u32 derateint;
u32 res1[10];
u32 rfshctl0;
u32 res2[4];
u32 rfshtmg;
u32 rfshtmg1;
u32 res3[28];
u32 init3;
u32 init4;
u32 res;
u32 init6;
u32 init7;
u32 res4[4];
u32 dramtmg0;
u32 dramtmg1;
u32 dramtmg2;
u32 dramtmg3;
u32 dramtmg4;
u32 dramtmg5;
u32 dramtmg6;
u32 dramtmg7;
u32 dramtmg8;
u32 dramtmg9;
u32 dramtmg10;
u32 dramtmg11;
u32 dramtmg12;
u32 dramtmg13;
u32 dramtmg14;
u32 dramtmg15;
u32 dramtmg16;
u32 dramtmg17;
u32 res5[10];
u32 mramtmg0;
u32 mramtmg1;
u32 mramtmg4;
u32 mramtmg9;
u32 zqctl0;
u32 res6[3];
u32 dfitmg0;
u32 dfitmg1;
u32 res7[7];
u32 dfitmg2;
u32 dfitmg3;
u32 res8[33];
u32 odtcfg;
};
struct imx8m_ddrc_regs {
u32 mstr;
u32 stat;
u32 mstr1;
u32 res1;
u32 mrctrl0;
u32 mrctrl1;
u32 mrstat;
u32 mrctrl2;
u32 derateen;
u32 derateint;
u32 mstr2;
u32 res2;
u32 pwrctl;
u32 pwrtmg;
u32 hwlpctl;
u32 hwffcctl;
u32 hwffcstat;
u32 res3[3];
u32 rfshctl0;
u32 rfshctl1;
u32 rfshctl2;
u32 rfshctl4;
u32 rfshctl3;
u32 rfshtmg;
u32 rfshtmg1;
u32 res4;
u32 ecccfg0;
u32 ecccfg1;
u32 eccstat;
u32 eccclr;
u32 eccerrcnt;
u32 ecccaddr0;
u32 ecccaddr1;
u32 ecccsyn0;
u32 ecccsyn1;
u32 ecccsyn2;
u32 eccbitmask0;
u32 eccbitmask1;
u32 eccbitmask2;
u32 eccuaddr0;
u32 eccuaddr1;
u32 eccusyn0;
u32 eccusyn1;
u32 eccusyn2;
u32 eccpoisonaddr0;
u32 eccpoisonaddr1;
u32 crcparctl0;
u32 crcparctl1;
u32 crcparctl2;
u32 crcparstat;
u32 init0;
u32 init1;
u32 init2;
u32 init3;
u32 init4;
u32 init5;
u32 init6;
u32 init7;
u32 dimmctl;
u32 rankctl;
u32 res5;
u32 chctl;
u32 dramtmg0;
u32 dramtmg1;
u32 dramtmg2;
u32 dramtmg3;
u32 dramtmg4;
u32 dramtmg5;
u32 dramtmg6;
u32 dramtmg7;
u32 dramtmg8;
u32 dramtmg9;
u32 dramtmg10;
u32 dramtmg11;
u32 dramtmg12;
u32 dramtmg13;
u32 dramtmg14;
u32 dramtmg15;
u32 dramtmg16;
u32 dramtmg17;
u32 res6[10];
u32 mramtmg0;
u32 mramtmg1;
u32 mramtmg4;
u32 mramtmg9;
u32 zqctl0;
u32 zqctl1;
u32 zqctl2;
u32 zqstat;
u32 dfitmg0;
u32 dfitmg1;
u32 dfilpcfg0;
u32 dfilpcfg1;
u32 dfiupd0;
u32 dfiupd1;
u32 dfiupd2;
u32 res7;
u32 dfimisc;
u32 dfitmg2;
u32 dfitmg3;
u32 dfistat;
u32 dbictl;
u32 dfiphymstr;
u32 res8[14];
u32 addrmap0;
u32 addrmap1;
u32 addrmap2;
u32 addrmap3;
u32 addrmap4;
u32 addrmap5;
u32 addrmap6;
u32 addrmap7;
u32 addrmap8;
u32 addrmap9;
u32 addrmap10;
u32 addrmap11;
u32 res9[4];
u32 odtcfg;
u32 odtmap;
u32 res10[2];
u32 sched;
u32 sched1;
u32 sched2;
u32 perfhpr1;
u32 res11;
u32 perflpr1;
u32 res12;
u32 perfwr1;
u32 res13[4];
u32 dqmap0;
u32 dqmap1;
u32 dqmap2;
u32 dqmap3;
u32 dqmap4;
u32 dqmap5;
u32 res14[26];
u32 dbg0;
u32 dbg1;
u32 dbgcam;
u32 dbgcmd;
u32 dbgstat;
u32 res15[3];
u32 swctl;
u32 swstat;
u32 res16[2];
u32 ocparcfg0;
u32 ocparcfg1;
u32 ocparcfg2;
u32 ocparcfg3;
u32 ocparstat0;
u32 ocparstat1;
u32 ocparwlog0;
u32 ocparwlog1;
u32 ocparwlog2;
u32 ocparawlog0;
u32 ocparawlog1;
u32 ocparrlog0;
u32 ocparrlog1;
u32 ocpararlog0;
u32 ocpararlog1;
u32 poisoncfg;
u32 poisonstat;
u32 adveccindex;
union {
u32 adveccstat;
u32 eccapstat;
};
u32 eccpoisonpat0;
u32 eccpoisonpat1;
u32 eccpoisonpat2;
u32 res17[6];
u32 caparpoisonctl;
u32 caparpoisonstat;
u32 res18[2];
u32 dynbsmstat;
u32 res19[18];
u32 pstat;
u32 pccfg;
struct {
u32 pcfgr;
u32 pcfgw;
u32 pcfgc;
struct {
u32 pcfgidmaskch0;
u32 pcfidvaluech0;
} pcfgid[16];
u32 pctrl;
u32 pcfgqos0;
u32 pcfgqos1;
u32 pcfgwqos0;
u32 pcfgwqos1;
u32 res[4];
} pcfg[16];
struct {
u32 sarbase;
u32 sarsize;
} sar[4];
u32 sbrctl;
u32 sbrstat;
u32 sbrwdata0;
u32 sbrwdata1;
u32 pdch;
u32 res20[755];
/* umctl2_regs_dch1 */
u32 ch1_stat;
u32 res21[2];
u32 ch1_mrctrl0;
u32 ch1_mrctrl1;
u32 ch1_mrstat;
u32 ch1_mrctrl2;
u32 res22[4];
u32 ch1_pwrctl;
u32 ch1_pwrtmg;
u32 ch1_hwlpctl;
u32 res23[15];
u32 ch1_eccstat;
u32 ch1_eccclr;
u32 ch1_eccerrcnt;
u32 ch1_ecccaddr0;
u32 ch1_ecccaddr1;
u32 ch1_ecccsyn0;
u32 ch1_ecccsyn1;
u32 ch1_ecccsyn2;
u32 ch1_eccbitmask0;
u32 ch1_eccbitmask1;
u32 ch1_eccbitmask2;
u32 ch1_eccuaddr0;
u32 ch1_eccuaddr1;
u32 ch1_eccusyn0;
u32 ch1_eccusyn1;
u32 ch1_eccusyn2;
u32 res24[2];
u32 ch1_crcparctl0;
u32 res25[2];
u32 ch1_crcparstat;
u32 res26[46];
u32 ch1_zqctl2;
u32 ch1_zqstat;
u32 res27[11];
u32 ch1_dfistat;
u32 res28[33];
u32 ch1_odtmap;
u32 res29[47];
u32 ch1_dbg1;
u32 ch1_dbgcam;
u32 ch1_dbgcmd;
u32 ch1_dbgstat;
u32 res30[123];
/* umctl2_regs_freq1 */
struct ddrc_freq freq1;
u32 res31[109];
/* umctl2_regs_addrmap_alt */
u32 addrmap0_alt;
u32 addrmap1_alt;
u32 addrmap2_alt;
u32 addrmap3_alt;
u32 addrmap4_alt;
u32 addrmap5_alt;
u32 addrmap6_alt;
u32 addrmap7_alt;
u32 addrmap8_alt;
u32 addrmap9_alt;
u32 addrmap10_alt;
u32 addrmap11_alt;
u32 res32[758];
/* umctl2_regs_freq2 */
struct ddrc_freq freq2;
u32 res33[879];
/* umctl2_regs_freq3 */
struct ddrc_freq freq3;
};
struct imx8m_ddrphy_regs {
u32 reg[0xf0000];
};
/* PHY State */
enum pstate {
PS0,
PS1,
PS2,
PS3,
};
enum msg_response {
TRAIN_SUCCESS = 0x7,
TRAIN_STREAM_START = 0x8,
TRAIN_FAIL = 0xff,
};
#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
/* user data type */
enum fw_type {
FW_1D_IMAGE,
FW_2D_IMAGE,
};
struct dram_cfg_param {
unsigned int reg;
unsigned int val;
};
struct dram_fsp_msg {
unsigned int drate;
enum fw_type fw_type;
struct dram_cfg_param *fsp_cfg;
unsigned int fsp_cfg_num;
};
struct dram_timing_info {
/* umctl2 config */
struct dram_cfg_param *ddrc_cfg;
unsigned int ddrc_cfg_num;
/* ddrphy config */
struct dram_cfg_param *ddrphy_cfg;
unsigned int ddrphy_cfg_num;
/* ddr fsp train info */
struct dram_fsp_msg *fsp_msg;
unsigned int fsp_msg_num;
/* ddr phy trained CSR */
struct dram_cfg_param *ddrphy_trained_csr;
unsigned int ddrphy_trained_csr_num;
/* ddr phy PIE */
struct dram_cfg_param *ddrphy_pie;
unsigned int ddrphy_pie_num;
/* initialized drate table */
unsigned int fsp_table[4];
};
extern struct dram_timing_info dram_timing;
void ddr_load_train_firmware(enum fw_type type);
void ddr_init(struct dram_timing_info *timing_info);
void ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void dram_config_save(struct dram_timing_info *info, unsigned long base);
/* utils function for ddr phy training */
void wait_ddrphy_training_complete(void);
void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
}
static inline u32 reg32_read(unsigned long addr)
{
return readl(addr);
}
static inline void reg32setbit(unsigned long addr, u32 bit)
{
setbits_le32(addr, (1 << bit));
}
#define dwc_ddrphy_apb_wr(addr, data) \
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
#define dwc_ddrphy_apb_rd(addr) \
reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
#endif

4
arch/arm/include/asm/arch-mx8m/gpio.h → arch/arm/include/asm/arch-imx8m/gpio.h
View File

@ -3,8 +3,8 @@
* Copyright 2017 NXP
*/
#ifndef __ASM_ARCH_MX8M_GPIO_H
#define __ASM_ARCH_MX8M_GPIO_H
#ifndef __ASM_ARCH_IMX8M_GPIO_H
#define __ASM_ARCH_IMX8M_GPIO_H
#include <asm/mach-imx/gpio.h>

4
arch/arm/include/asm/arch-mx8m/imx-regs.h → arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -3,8 +3,8 @@
* Copyright 2017 NXP
*/
#ifndef __ASM_ARCH_MX8M_REGS_H__
#define __ASM_ARCH_MX8M_REGS_H__
#ifndef __ASM_ARCH_IMX8M_REGS_H__
#define __ASM_ARCH_IMX8M_REGS_H__
#include <asm/mach-imx/regs-lcdif.h>

4
arch/arm/include/asm/arch-mx8m/mx8mq_pins.h → arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
View File

@ -3,8 +3,8 @@
* Copyright (C) 2017 NXP
*/
#ifndef __ASM_ARCH_MX8MQ_PINS_H__
#define __ASM_ARCH_MX8MQ_PINS_H__
#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
#define __ASM_ARCH_IMX8MQ_PINS_H__
#include <asm/mach-imx/iomux-v3.h>

97
arch/arm/include/asm/arch-imx8m/lpddr4_define.h Normal file
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@ -0,0 +1,97 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __LPDDR4_DEFINE_H_
#define __LPDDR4_DEFINE_H_
#define LPDDR4_DVFS_DBI
#define DDR_ONE_RANK
/* #define LPDDR4_DBI_ON */
#define DFI_BUG_WR
#define M845S_4GBx2
#define PRETRAIN
/* DRAM MR setting */
#ifdef LPDDR4_DBI_ON
#define LPDDR4_MR3 0xf1
#define LPDDR4_PHY_DMIPinPresent 0x1
#else
#define LPDDR4_MR3 0x31
#define LPDDR4_PHY_DMIPinPresent 0x0
#endif
#ifdef DDR_ONE_RANK
#define LPDDR4_CS 0x1
#else
#define LPDDR4_CS 0x3
#endif
/* PHY training feature */
#define LPDDR4_HDT_CTL_2D 0xC8
#define LPDDR4_HDT_CTL_3200_1D 0xC8
#define LPDDR4_HDT_CTL_400_1D 0xC8
#define LPDDR4_HDT_CTL_100_1D 0xC8
/* 400/100 training seq */
#define LPDDR4_TRAIN_SEQ_P2 0x121f
#define LPDDR4_TRAIN_SEQ_P1 0x121f
#define LPDDR4_TRAIN_SEQ_P0 0x121f
#define LPDDR4_TRAIN_SEQ_100 0x121f
#define LPDDR4_TRAIN_SEQ_400 0x121f
/* 2D share & weight */
#define LPDDR4_2D_WEIGHT 0x1f7f
#define LPDDR4_2D_SHARE 1
#define LPDDR4_CATRAIN_3200_1d 0
#define LPDDR4_CATRAIN_400 0
#define LPDDR4_CATRAIN_100 0
#define LPDDR4_CATRAIN_3200_2d 0
/* MRS parameter */
/* for LPDDR4 Rtt */
#define LPDDR4_RTT40 6
#define LPDDR4_RTT48 5
#define LPDDR4_RTT60 4
#define LPDDR4_RTT80 3
#define LPDDR4_RTT120 2
#define LPDDR4_RTT240 1
#define LPDDR4_RTT_DIS 0
/* for LPDDR4 Ron */
#define LPDDR4_RON34 7
#define LPDDR4_RON40 6
#define LPDDR4_RON48 5
#define LPDDR4_RON60 4
#define LPDDR4_RON80 3
#define LPDDR4_PHY_ADDR_RON60 0x1
#define LPDDR4_PHY_ADDR_RON40 0x3
#define LPDDR4_PHY_ADDR_RON30 0x7
#define LPDDR4_PHY_ADDR_RON24 0xf
#define LPDDR4_PHY_ADDR_RON20 0x1f
/* for read channel */
#define LPDDR4_RON LPDDR4_RON40
#define LPDDR4_PHY_RTT 30
#define LPDDR4_PHY_VREF_VALUE 17
/* for write channel */
#define LPDDR4_PHY_RON 30
#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
#define LPDDR4_RTT_DQ LPDDR4_RTT40
#define LPDDR4_RTT_CA LPDDR4_RTT40
#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40
#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40
#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd))
#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd))
#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd))
#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \
(LPDDR4_RTT40))
#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \
(LPDDR4_RTT40))
#define LPDDR4_MR3_PU_CAL 1
#endif /* __LPDDR4_DEFINE_H__ */

4
arch/arm/include/asm/arch-mx8m/sys_proto.h → arch/arm/include/asm/arch-imx8m/sys_proto.h
View File

@ -3,8 +3,8 @@
* Copyright (C) 2017 NXP
*/
#ifndef __ARCH_MX8M_SYS_PROTO_H
#define __ARCH_MX8M_SYS_PROTO_H
#ifndef __ARCH_IMX8M_SYS_PROTO_H
#define __ARCH_NMX8M_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>

355
arch/arm/include/asm/arch-mx8m/ddr.h
View File

@ -1,355 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
*/
#ifndef __ASM_ARCH_MX8M_DDR_H
#define __ASM_ARCH_MX8M_DDR_H
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR_0 0x3f400000
#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
struct ddrc_freq {
u32 res0[8];
u32 derateen;
u32 derateint;
u32 res1[10];
u32 rfshctl0;
u32 res2[4];
u32 rfshtmg;
u32 rfshtmg1;
u32 res3[28];
u32 init3;
u32 init4;
u32 res;
u32 init6;
u32 init7;
u32 res4[4];
u32 dramtmg0;
u32 dramtmg1;
u32 dramtmg2;
u32 dramtmg3;
u32 dramtmg4;
u32 dramtmg5;
u32 dramtmg6;
u32 dramtmg7;
u32 dramtmg8;
u32 dramtmg9;
u32 dramtmg10;
u32 dramtmg11;
u32 dramtmg12;
u32 dramtmg13;
u32 dramtmg14;
u32 dramtmg15;
u32 dramtmg16;
u32 dramtmg17;
u32 res5[10];
u32 mramtmg0;
u32 mramtmg1;
u32 mramtmg4;
u32 mramtmg9;
u32 zqctl0;
u32 res6[3];
u32 dfitmg0;
u32 dfitmg1;
u32 res7[7];
u32 dfitmg2;
u32 dfitmg3;
u32 res8[33];
u32 odtcfg;
};
struct imx8m_ddrc_regs {
u32 mstr;
u32 stat;
u32 mstr1;
u32 res1;
u32 mrctrl0;
u32 mrctrl1;
u32 mrstat;
u32 mrctrl2;
u32 derateen;
u32 derateint;
u32 mstr2;
u32 res2;
u32 pwrctl;
u32 pwrtmg;
u32 hwlpctl;
u32 hwffcctl;
u32 hwffcstat;
u32 res3[3];
u32 rfshctl0;
u32 rfshctl1;
u32 rfshctl2;
u32 rfshctl4;
u32 rfshctl3;
u32 rfshtmg;
u32 rfshtmg1;
u32 res4;
u32 ecccfg0;
u32 ecccfg1;
u32 eccstat;
u32 eccclr;
u32 eccerrcnt;
u32 ecccaddr0;
u32 ecccaddr1;
u32 ecccsyn0;
u32 ecccsyn1;
u32 ecccsyn2;
u32 eccbitmask0;
u32 eccbitmask1;
u32 eccbitmask2;
u32 eccuaddr0;
u32 eccuaddr1;
u32 eccusyn0;
u32 eccusyn1;
u32 eccusyn2;
u32 eccpoisonaddr0;
u32 eccpoisonaddr1;
u32 crcparctl0;
u32 crcparctl1;
u32 crcparctl2;
u32 crcparstat;
u32 init0;
u32 init1;
u32 init2;
u32 init3;
u32 init4;
u32 init5;
u32 init6;
u32 init7;
u32 dimmctl;
u32 rankctl;
u32 res5;
u32 chctl;
u32 dramtmg0;
u32 dramtmg1;
u32 dramtmg2;
u32 dramtmg3;
u32 dramtmg4;
u32 dramtmg5;
u32 dramtmg6;
u32 dramtmg7;
u32 dramtmg8;
u32 dramtmg9;
u32 dramtmg10;
u32 dramtmg11;
u32 dramtmg12;
u32 dramtmg13;
u32 dramtmg14;
u32 dramtmg15;
u32 dramtmg16;
u32 dramtmg17;
u32 res6[10];
u32 mramtmg0;
u32 mramtmg1;
u32 mramtmg4;
u32 mramtmg9;
u32 zqctl0;
u32 zqctl1;
u32 zqctl2;
u32 zqstat;
u32 dfitmg0;
u32 dfitmg1;
u32 dfilpcfg0;
u32 dfilpcfg1;
u32 dfiupd0;
u32 dfiupd1;
u32 dfiupd2;
u32 res7;
u32 dfimisc;
u32 dfitmg2;
u32 dfitmg3;
u32 dfistat;
u32 dbictl;
u32 dfiphymstr;
u32 res8[14];
u32 addrmap0;
u32 addrmap1;
u32 addrmap2;
u32 addrmap3;
u32 addrmap4;
u32 addrmap5;
u32 addrmap6;
u32 addrmap7;
u32 addrmap8;
u32 addrmap9;
u32 addrmap10;
u32 addrmap11;
u32 res9[4];
u32 odtcfg;
u32 odtmap;
u32 res10[2];
u32 sched;
u32 sched1;
u32 sched2;
u32 perfhpr1;
u32 res11;
u32 perflpr1;
u32 res12;
u32 perfwr1;
u32 res13[4];
u32 dqmap0;
u32 dqmap1;
u32 dqmap2;
u32 dqmap3;
u32 dqmap4;
u32 dqmap5;
u32 res14[26];
u32 dbg0;
u32 dbg1;
u32 dbgcam;
u32 dbgcmd;
u32 dbgstat;
u32 res15[3];
u32 swctl;
u32 swstat;
u32 res16[2];
u32 ocparcfg0;
u32 ocparcfg1;
u32 ocparcfg2;
u32 ocparcfg3;
u32 ocparstat0;
u32 ocparstat1;
u32 ocparwlog0;
u32 ocparwlog1;
u32 ocparwlog2;
u32 ocparawlog0;
u32 ocparawlog1;
u32 ocparrlog0;
u32 ocparrlog1;
u32 ocpararlog0;
u32 ocpararlog1;
u32 poisoncfg;
u32 poisonstat;
u32 adveccindex;
union {
u32 adveccstat;
u32 eccapstat;
};
u32 eccpoisonpat0;
u32 eccpoisonpat1;
u32 eccpoisonpat2;
u32 res17[6];
u32 caparpoisonctl;
u32 caparpoisonstat;
u32 res18[2];
u32 dynbsmstat;
u32 res19[18];
u32 pstat;
u32 pccfg;
struct {
u32 pcfgr;
u32 pcfgw;
u32 pcfgc;
struct {
u32 pcfgidmaskch0;
u32 pcfidvaluech0;
} pcfgid[16];
u32 pctrl;
u32 pcfgqos0;
u32 pcfgqos1;
u32 pcfgwqos0;
u32 pcfgwqos1;
u32 res[4];
} pcfg[16];
struct {
u32 sarbase;
u32 sarsize;
} sar[4];
u32 sbrctl;
u32 sbrstat;
u32 sbrwdata0;
u32 sbrwdata1;
u32 pdch;
u32 res20[755];
/* umctl2_regs_dch1 */
u32 ch1_stat;
u32 res21[2];
u32 ch1_mrctrl0;
u32 ch1_mrctrl1;
u32 ch1_mrstat;
u32 ch1_mrctrl2;
u32 res22[4];
u32 ch1_pwrctl;
u32 ch1_pwrtmg;
u32 ch1_hwlpctl;
u32 res23[15];
u32 ch1_eccstat;
u32 ch1_eccclr;
u32 ch1_eccerrcnt;
u32 ch1_ecccaddr0;
u32 ch1_ecccaddr1;
u32 ch1_ecccsyn0;
u32 ch1_ecccsyn1;
u32 ch1_ecccsyn2;
u32 ch1_eccbitmask0;
u32 ch1_eccbitmask1;
u32 ch1_eccbitmask2;
u32 ch1_eccuaddr0;
u32 ch1_eccuaddr1;
u32 ch1_eccusyn0;
u32 ch1_eccusyn1;
u32 ch1_eccusyn2;
u32 res24[2];
u32 ch1_crcparctl0;
u32 res25[2];
u32 ch1_crcparstat;
u32 res26[46];
u32 ch1_zqctl2;
u32 ch1_zqstat;
u32 res27[11];
u32 ch1_dfistat;
u32 res28[33];
u32 ch1_odtmap;
u32 res29[47];
u32 ch1_dbg1;
u32 ch1_dbgcam;
u32 ch1_dbgcmd;
u32 ch1_dbgstat;
u32 res30[123];
/* umctl2_regs_freq1 */
struct ddrc_freq freq1;
u32 res31[109];
/* umctl2_regs_addrmap_alt */
u32 addrmap0_alt;
u32 addrmap1_alt;
u32 addrmap2_alt;
u32 addrmap3_alt;
u32 addrmap4_alt;
u32 addrmap5_alt;
u32 addrmap6_alt;
u32 addrmap7_alt;
u32 addrmap8_alt;
u32 addrmap9_alt;
u32 addrmap10_alt;
u32 addrmap11_alt;
u32 res32[758];
/* umctl2_regs_freq2 */
struct ddrc_freq freq2;
u32 res33[879];
/* umctl2_regs_freq3 */
struct ddrc_freq freq3;
};
struct imx8m_ddrphy_regs {
u32 reg[0xf0000];
};
/* PHY State */
enum pstate {
PS0,
PS1,
PS2,
PS3,
};
enum msg_response {
TRAIN_SUCCESS = 0x7,
TRAIN_STREAM_START = 0x8,
TRAIN_FAIL = 0xff,
};
#endif

2
arch/arm/include/asm/mach-imx/iomux-v3.h
View File

@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
#define IOMUX_CONFIG_LPSR 0x20
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_MX8M
#ifdef CONFIG_IMX8M
#define PAD_CTL_DSE0 (0x0 << 0)
#define PAD_CTL_DSE1 (0x1 << 0)
#define PAD_CTL_DSE2 (0x2 << 0)

6
arch/arm/include/asm/mach-imx/regs-lcdif.h
View File

@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_MX8M)
defined(CONFIG_IMX8M)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_MX8M)
defined(CONFIG_IMX8M)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@ -73,7 +73,7 @@ struct mxs_lcdif_regs {
defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_MX8M)
defined(CONFIG_IMX8M)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)

3
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -26,7 +26,7 @@
#define is_mx6() (is_soc_type(MXC_SOC_MX6))
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@ -42,6 +42,7 @@
#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#ifdef CONFIG_MX6

37
arch/arm/mach-imx/Makefile
View File

@ -5,12 +5,14 @@
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
obj-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx8m))
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
@ -22,7 +24,7 @@ obj-y += cpu.o speed.o
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
@ -104,7 +106,11 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
ifeq ($(CONFIG_ARCH_IMX8), y)
CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
IMAGE_TYPE := imx8image
DEPFILE_EXISTS := $(shell if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
@ -129,6 +135,26 @@ ifeq ($(DEPFILE_EXISTS),0)
endif
endif
ifdef CONFIG_ARM64
ifeq ($(CONFIG_ARCH_IMX8M), y)
SPL:
MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
flash.bin: MKIMAGEOUTPUT = flash.log
spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
ifeq ($(DEPFILE_EXISTS),0)
$(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
endif
flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
ifeq ($(DEPFILE_EXISTS),0)
$(call if_changed,mkimage)
endif
endif
else
MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
SPL: MKIMAGEOUTPUT = SPL.log
@ -160,6 +186,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
spl/u-boot-nand-spl.imx: SPL FORCE
$(call if_changed,u-boot-nand-spl_imx)
endif
targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
@ -169,5 +196,5 @@ obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_MX8M) += mx8m/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/

16
arch/arm/mach-imx/cpu.c
View File

@ -62,7 +62,7 @@ static char *get_reset_cause(void)
return "WDOG4";
case 0x00200:
return "TEMPSENSE";
#elif defined(CONFIG_MX8M)
#elif defined(CONFIG_IMX8M)
case 0x00100:
return "WDOG2";
case 0x00200:
@ -142,8 +142,8 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_MX8MQ:
return "8MQ"; /* Quad-core version of the mx8m */
case MXC_CPU_IMX8MQ:
return "8MQ"; /* Quad-core version of the imx8m */
case MXC_CPU_MX7S:
return "7S"; /* Single-core version of the mx7 */
case MXC_CPU_MX7D:
@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -300,7 +300,7 @@ void arch_preboot_os(void)
#endif
}
#ifndef CONFIG_MX8M
#ifndef CONFIG_IMX8M
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size)
}
#endif
#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
/*
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
}
#endif
#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
enum boot_device get_boot_device(void)
{
struct bootrom_sw_info **p =
@ -438,7 +438,7 @@ enum boot_device get_boot_device(void)
case BOOT_TYPE_SPINOR:
boot_dev = SPI_NOR_BOOT;
break;
#ifdef CONFIG_MX8M
#ifdef CONFIG_IMX8M
case BOOT_TYPE_USB:
boot_dev = USB_BOOT;
break;

29
arch/arm/mach-imx/hab.c
View File

@ -6,6 +6,8 @@
#include <common.h>
#include <config.h>
#include <fuse.h>
#include <mapmem.h>
#include <image.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/clock.h>
@ -302,18 +304,41 @@ static int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc,
return 0;
}
static ulong get_image_ivt_offset(ulong img_addr)
{
const void *buf;
buf = map_sysmem(img_addr, 0);
switch (genimg_get_format(buf)) {
#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
return (image_get_image_size((image_header_t *)img_addr)
+ 0x1000 - 1) & ~(0x1000 - 1);
#endif
#if IMAGE_ENABLE_FIT
case IMAGE_FORMAT_FIT:
return (fit_get_size(buf) + 0x1000 - 1) & ~(0x1000 - 1);
#endif
default:
return 0;
}
}
static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
ulong addr, length, ivt_offset;
int rcode = 0;
if (argc < 4)
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
length = simple_strtoul(argv[2], NULL, 16);
ivt_offset = simple_strtoul(argv[3], NULL, 16);
if (argc == 3)
ivt_offset = get_image_ivt_offset(addr);
else
ivt_offset = simple_strtoul(argv[3], NULL, 16);
rcode = imx_hab_authenticate_image(addr, length, ivt_offset);
if (rcode == 0)

23
arch/arm/mach-imx/imx8m/Kconfig Normal file
View File

@ -0,0 +1,23 @@
if ARCH_IMX8M
config IMX8M
bool
select ROM_UNIFIED_SECTIONS
config SYS_SOC
default "imx8m"
choice
prompt "NXP i.MX8M board select"
optional
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
select IMX8M
select IMX8M_LPDDR4
endchoice
source "board/freescale/imx8mq_evk/Kconfig"
endif

0
arch/arm/mach-imx/mx8m/Makefile → arch/arm/mach-imx/imx8m/Makefile
View File

138
arch/arm/mach-imx/mx8m/clock.c → arch/arm/mach-imx/imx8m/clock.c
View File

@ -525,41 +525,127 @@ u32 imx_get_fecclk(void)
return get_root_clk(ENET_AXI_CLK_ROOT);
}
#ifdef CONFIG_SPL_BUILD
void dram_pll_init(void)
static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
CLK_ROOT_PRE_DIV2),
DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
CLK_ROOT_PRE_DIV2),
DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
CLK_ROOT_PRE_DIV2),
};
void dram_enable_bypass(ulong clk_val)
{
int i;
struct dram_bypass_clk_setting *config;
for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
break;
}
if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
printf("No matched freq table %lu\n", clk_val);
return;
}
config = &imx8mq_dram_bypass_tbl[i];
clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
CLK_ROOT_PRE_DIV(config->alt_pre_div));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
CLK_ROOT_PRE_DIV(config->apb_pre_div));
clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(1));
}
void dram_disable_bypass(void)
{
clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(0));
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
}
#ifdef CONFIG_SPL_BUILD
void dram_pll_init(ulong pll_val)
{
struct src *src = (struct src *)SRC_BASE_ADDR;
void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
u32 val;
int ret;
void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
/* Bypass */
setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
pwdn_mask = SSCG_PLL_PD_MASK;
pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
bypass1 = SSCG_PLL_BYPASS1_MASK;
bypass2 = SSCG_PLL_BYPASS2_MASK;
/* Enable DDR1 and DDR2 domain */
writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
switch (pll_val) {
case MHZ(800):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
val |= SSCG_PLL_REF_DIVR2_VAL(29);
writel(val, pll_cfg_reg2);
break;
case MHZ(600):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
val |= SSCG_PLL_REF_DIVR2_VAL(29);
writel(val, pll_cfg_reg2);
break;
case MHZ(400):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
val |= SSCG_PLL_REF_DIVR2_VAL(29);
writel(val, pll_cfg_reg2);
break;
case MHZ(167):
val = readl(pll_cfg_reg2);
val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
SSCG_PLL_FEEDBACK_DIV_F2_MASK |
SSCG_PLL_FEEDBACK_DIV_F1_MASK |
SSCG_PLL_REF_DIVR2_MASK);
val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
val |= SSCG_PLL_REF_DIVR2_VAL(30);
writel(val, pll_cfg_reg2);
break;
default:
break;
}
/* Clear power down bit */
clrbits_le32(pll_control_reg, pwdn_mask);
clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
/* Eanble ARM_PLL/SYS_PLL */
setbits_le32(pll_control_reg, pll_clke);
setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
/* Clear bypass */
clrbits_le32(pll_control_reg, bypass1);
clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
__udelay(100);
clrbits_le32(pll_control_reg, bypass2);
clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
/* Wait lock */
ret = readl_poll_timeout(pll_control_reg, val,
val & SSCG_PLL_LOCK_MASK, 1);
if (ret)
printf("%s timeout\n", __func__);
while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
;
}
int frac_pll_init(u32 pll, enum frac_pll_out_val val)
@ -730,7 +816,7 @@ int clock_init(void)
* Dump some clockes.
*/
#ifndef CONFIG_SPL_BUILD
int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
u32 freq;
@ -785,7 +871,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
"display clocks",
""
);

0
arch/arm/mach-imx/mx8m/clock_slice.c → arch/arm/mach-imx/imx8m/clock_slice.c
View File

17
arch/arm/mach-imx/imx8m/imximage.cfg Normal file
View File

@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#define __ASSEMBLY__
FIT
BOOT_FROM sd
SIGNED_HDMI signed_hdmi_imx8m.bin
LOADER spl/u-boot-spl-ddr.bin 0x7E1000
SECOND_LOADER u-boot.itb 0x40200000 0x60000
DDR_FW lpddr4_pmu_train_1d_imem.bin
DDR_FW lpddr4_pmu_train_1d_dmem.bin
DDR_FW lpddr4_pmu_train_2d_imem.bin
DDR_FW lpddr4_pmu_train_2d_dmem.bin

0
arch/arm/mach-imx/mx8m/lowlevel_init.S → arch/arm/mach-imx/imx8m/lowlevel_init.S
View File

16
arch/arm/mach-imx/mx8m/soc.c → arch/arm/mach-imx/imx8m/soc.c
View File

@ -77,6 +77,22 @@ static struct mm_region imx8m_mem_map[] = {
.size = 0x100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* CAAM */
.virt = 0x100000UL,
.phys = 0x100000UL,
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* TCM */
.virt = 0x7C0000UL,
.phys = 0x7C0000UL,
.size = 0x80000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* OCRAM */
.virt = 0x900000UL,

8
arch/arm/mach-imx/imx_bootaux.c
View File

@ -17,15 +17,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
if (!boot_private_data)
return -EINVAL;
stack = *(ulong *)boot_private_data;
pc = *(ulong *)(boot_private_data + 4);
stack = *(u32 *)boot_private_data;
pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Enable M4 */
#ifdef CONFIG_MX8M
#ifdef CONFIG_IMX8M
call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
#else
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
int arch_auxiliary_core_check_up(u32 core_id)
{
#ifdef CONFIG_MX8M
#ifdef CONFIG_IMX8M
return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
#else
unsigned int val;

137
arch/arm/mach-imx/mkimage_fit_atf.sh Executable file
View File

@ -0,0 +1,137 @@
#!/bin/sh
# SPDX-License-Identifier: GPL-2.0+
#
# script to generate FIT image source for i.MX8MQ boards with
# ARM Trusted Firmware and multiple device trees (given on the command line)
#
# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
[ -z "$BL31" ] && BL31="bl31.bin"
[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
if [ ! -f $BL31 ]; then
echo "ERROR: BL31 file $BL31 NOT found" >&2
exit 0
else
echo "$BL31 size: " >&2
ls -lct $BL31 | awk '{print $5}' >&2
fi
BL32="tee.bin"
if [ ! -f $BL32 ]; then
BL32=/dev/null
else
echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
echo "$BL32 size: " >&2
ls -lct $BL32 | awk '{print $5}' >&2
fi
BL33="u-boot-nodtb.bin"
if [ ! -f $BL33 ]; then
echo "ERROR: $BL33 file NOT found" >&2
exit 0
else
echo "u-boot-nodtb.bin size: " >&2
ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
fi
for dtname in $*
do
echo "$dtname size: " >&2
ls -lct $dtname | awk '{print $5}' >&2
done
cat << __HEADER_EOF
/dts-v1/;
/ {
description = "Configuration to load ATF before U-Boot";
images {
uboot@1 {
description = "U-Boot (64-bit)";
data = /incbin/("$BL33");
type = "standalone";
arch = "arm64";
compression = "none";
load = <0x40200000>;
};
atf@1 {
description = "ARM Trusted Firmware";
data = /incbin/("$BL31");
type = "firmware";
arch = "arm64";
compression = "none";
load = <$ATF_LOAD_ADDR>;
entry = <$ATF_LOAD_ADDR>;
};
__HEADER_EOF
if [ -f $BL32 ]; then
cat << __HEADER_EOF
tee@1 {
description = "TEE firmware";
data = /incbin/("$BL32");
type = "firmware";
arch = "arm64";
compression = "none";
load = <$TEE_LOAD_ADDR>;
entry = <$TEE_LOAD_ADDR>;
};
__HEADER_EOF
fi
cnt=1
for dtname in $*
do
cat << __FDT_IMAGE_EOF
fdt@$cnt {
description = "$(basename $dtname .dtb)";
data = /incbin/("$dtname");
type = "flat_dt";
compression = "none";
};
__FDT_IMAGE_EOF
cnt=$((cnt+1))
done
cat << __CONF_HEADER_EOF
};
configurations {
default = "config@1";
__CONF_HEADER_EOF
cnt=1
for dtname in $*
do
if [ -f $BL32 ]; then
cat << __CONF_SECTION_EOF
config@$cnt {
description = "$(basename $dtname .dtb)";
firmware = "uboot@1";
loadables = "atf@1", "tee@1";
fdt = "fdt@$cnt";
};
__CONF_SECTION_EOF
else
cat << __CONF_SECTION1_EOF
config@$cnt {
description = "$(basename $dtname .dtb)";
firmware = "uboot@1";
loadables = "atf@1";
fdt = "fdt@$cnt";
};
__CONF_SECTION1_EOF
fi
cnt=$((cnt+1))
done
cat << __ITS_EOF
};
};
__ITS_EOF

1
arch/arm/mach-imx/mx6/Kconfig
View File

@ -182,6 +182,7 @@ config TARGET_DISPLAY5
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_GE_BX50V3
bool "General Electric Bx50v3"

10
arch/arm/mach-imx/mx8m/Kconfig
View File

@ -1,10 +0,0 @@
if ARCH_MX8M
config MX8M
bool
select ROM_UNIFIED_SECTIONS
config SYS_SOC
default "mx8m"
endif

59
arch/arm/mach-imx/spl.c
View File

@ -96,8 +96,8 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
u32 spl_boot_device(void)
{
#if defined(CONFIG_MX7)
@ -126,6 +126,7 @@ u32 spl_boot_device(void)
enum boot_device boot_device_spl = get_boot_device();
switch (boot_device_spl) {
#if defined(CONFIG_MX7)
case SD1_BOOT:
case MMC1_BOOT:
case SD2_BOOT:
@ -133,6 +134,14 @@ u32 spl_boot_device(void)
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC1;
#elif defined(CONFIG_IMX8M)
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
#endif
case NAND_BOOT:
return BOOT_DEVICE_NAND;
case SPI_NOR_BOOT:
@ -143,7 +152,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
}
#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
#endif /* CONFIG_MX7 || CONFIG_IMX8M */
#ifdef CONFIG_SPL_USB_GADGET_SUPPORT
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
@ -220,14 +229,46 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
debug("image entry point: 0x%lX\n", spl_image->entry_point);
/* HAB looks for the CSF at the end of the authenticated data therefore,
* we need to subtract the size of the CSF from the actual filesize */
offset = spl_image->size - CONFIG_CSF_SIZE;
if (!imx_hab_authenticate_image(spl_image->load_addr,
offset + IVT_SIZE + CSF_PAD_SIZE,
offset)) {
if (spl_image->flags & SPL_FIT_FOUND) {
image_entry();
} else {
/*
* HAB looks for the CSF at the end of the authenticated
* data therefore, we need to subtract the size of the
* CSF from the actual filesize
*/
offset = spl_image->size - CONFIG_CSF_SIZE;
if (!imx_hab_authenticate_image(spl_image->load_addr,
offset + IVT_SIZE +
CSF_PAD_SIZE, offset)) {
image_entry();
} else {
puts("spl: ERROR: image authentication fail\n");
hang();
}
}
}
ulong board_spl_fit_size_align(ulong size)
{
/*
* HAB authenticate_image requests the IVT offset is
* aligned to 0x1000
*/
size = ALIGN(size, 0x1000);
size += CONFIG_CSF_SIZE;
return size;
}
void board_spl_fit_post_load(ulong load_addr, size_t length)
{
u32 offset = length - CONFIG_CSF_SIZE;
if (imx_hab_authenticate_image(load_addr,
offset + IVT_SIZE + CSF_PAD_SIZE,
offset)) {
puts("spl: ERROR: image authentication unsuccessful\n");
hang();
}

1
board/embest/mx6boards/MAINTAINERS
View File

@ -5,3 +5,4 @@ F: board/embest/mx6boards/
F: include/configs/embestmx6boards.h
F: configs/marsboard_defconfig
F: configs/riotboard_defconfig
F: configs/riotboard_spl_defconfig

48
board/embest/mx6boards/mx6boards.c
View File

@ -608,3 +608,51 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
void board_init_f(ulong dummy)
{
u32 cputype = cpu_type(get_cpu_rev());
switch (cputype) {
case MXC_CPU_MX6SOLO:
board_type = BOARD_IS_RIOTBOARD;
break;
case MXC_CPU_MX6D:
board_type = BOARD_IS_MARSBOARD;
break;
}
arch_cpu_init();
/* setup GP timer */
timer_init();
#ifdef CONFIG_SPL_SERIAL_SUPPORT
setup_iomux_uart();
preloader_console_init();
#endif
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_MMC1;
}
/*
* In order to jump to standard u-boot shell, you have to connect pin 5 of J13
* to pin 3 (ground).
*/
int spl_start_uboot(void)
{
int gpio_key = IMX_GPIO_NR(4, 16);
gpio_direction_input(gpio_key);
if (gpio_get_value(gpio_key) == 0)
return 1;
else
return 0;
}
#endif

12
board/freescale/imx8mq_evk/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_IMX8MQ_EVK
config SYS_BOARD
default "imx8mq_evk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx8mq_evk"
endif

6
board/freescale/imx8mq_evk/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
i.MX8MQ EVK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx8mq_evk/
F: include/configs/imx8mq_evk.h
F: configs/imx8mq_evk_defconfig

12
board/freescale/imx8mq_evk/Makefile Normal file
View File

@ -0,0 +1,12 @@
#
# Copyright 2017 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mq_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
endif

36
board/freescale/imx8mq_evk/README Normal file
View File

@ -0,0 +1,36 @@
U-Boot for the NXP i.MX8MQ EVK board
Quick Start
====================
- Build the ARM Trusted firmware binary
- Get ddr and hdmi fimware
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
====================
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
branch: imx_4.14.62_1.0.0_beta
$ make PLAT=imx8mq bl31
Get the ddr and hdmi firmware
====================
Note: srctree is U-Boot source directory
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
$ chmod +x firmware-imx-7.9.bin
$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
Build U-Boot
====================
$ export ARCH=arm64
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8mq_evk_defconfig
$ make flash.bin
Burn the flash.bin to MicroSD card offset 33KB
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
Boot
====================
Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.

130
board/freescale/imx8mq_evk/imx8mq_evk.c Normal file
View File

@ -0,0 +1,130 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <spl.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_FEC_MXC
#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_init(void)
{
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "EVK");
env_set("board_rev", "iMX8MQ");
#endif
return 0;
}

1320
board/freescale/imx8mq_evk/lpddr4_timing.c Normal file
View File

File diff suppressed because it is too large Load Diff

1191
board/freescale/imx8mq_evk/lpddr4_timing_b0.c Normal file
View File

File diff suppressed because it is too large Load Diff

246
board/freescale/imx8mq_evk/spl.c Normal file
View File

@ -0,0 +1,246 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <spl.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
extern struct dram_timing_info dram_timing_b0;
void spl_dram_init(void)
{
/* ddr init */
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
ddr_init(&dram_timing);
else
ddr_init(&dram_timing_b0);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
return 1;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#ifdef CONFIG_POWER
#define I2C_PMIC 0
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
}
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
return 0;
}
#endif
void spl_board_init(void)
{
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
arch_cpu_init();
init_uart_clk(0);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
/* Adjust pmic voltage to 1.0V for 800M */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

1
board/freescale/imx8qxp_mek/imximage.cfg
View File

@ -7,7 +7,6 @@
*/
#define __ASSEMBLY__
#include <config.h>
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400

2
board/ge/bx50v3/Kconfig
View File

@ -15,4 +15,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ge_bx50v3"
source "board/ge/common/Kconfig"
endif

57
board/ge/bx50v3/bx50v3.c
View File

@ -33,20 +33,9 @@
#include "../../../drivers/net/e1000.h"
DECLARE_GLOBAL_DATA_PTR;
struct vpd_cache;
static int confidx = 3; /* Default to b850v3. */
static struct vpd_cache vpd;
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#endif
#ifndef CONFIG_SYS_I2C_EEPROM_BUS
#define CONFIG_SYS_I2C_EEPROM_BUS 4
#endif
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
@ -569,6 +558,7 @@ int overwrite_console(void)
#define VPD_MAC_ADDRESS_LENGTH 6
struct vpd_cache {
bool is_read;
u8 product_id;
u8 has;
unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
@ -578,11 +568,9 @@ struct vpd_cache {
/*
* Extracts MAC and product information from the VPD.
*/
static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
size_t size, u8 const *data)
{
struct vpd_cache *vpd = (struct vpd_cache *)userdata;
if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
size >= 1) {
vpd->product_id = data[0];
@ -606,6 +594,11 @@ static void process_vpd(struct vpd_cache *vpd)
int fec_index = -1;
int i210_index = -1;
if (!vpd->is_read) {
printf("VPD wasn't read");
return;
}
switch (vpd->product_id) {
case VPD_PRODUCT_B450:
env_set("confidx", "1");
@ -631,35 +624,6 @@ static void process_vpd(struct vpd_cache *vpd)
eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
}
static int read_vpd(uint eeprom_bus)
{
int res;
int size = 1024;
uint8_t *data;
unsigned int current_i2c_bus = i2c_get_bus_num();
res = i2c_set_bus_num(eeprom_bus);
if (res < 0)
return res;
data = (uint8_t *)malloc(size);
if (!data)
return -ENOMEM;
res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
if (res == 0) {
memset(&vpd, 0, sizeof(vpd));
vpd_reader(size, data, &vpd, vpd_callback);
}
free(data);
i2c_set_bus_num(current_i2c_bus);
return res;
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
@ -718,9 +682,10 @@ int board_init(void)
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
set_confidx(&vpd);
if (!read_vpd(&vpd, vpd_callback)) {
vpd.is_read = true;
set_confidx(&vpd);
}
gpio_direction_output(SUS_S3_OUT, 1);
gpio_direction_output(WIFI_EN, 1);

14
board/ge/common/Kconfig Normal file
View File

@ -0,0 +1,14 @@
config SYS_VPD_EEPROM_I2C_ADDR
hex "I2C address of the EEPROM device used for VPD"
help
VPD = Vital Product Data
config SYS_VPD_EEPROM_I2C_BUS
int "I2C bus of the EEPROM device used for VPD."
config SYS_VPD_EEPROM_SIZE
int "Size in bytes of the EEPROM device used for VPD"
config SYS_VPD_EEPROM_I2C_ADDR_LEN
int "Number of bytes to use for VPD EEPROM address"
default 1

37
board/ge/common/vpd_reader.c
View File

@ -5,6 +5,7 @@
#include "vpd_reader.h"
#include <i2c.h>
#include <linux/bch.h>
#include <stdlib.h>
@ -105,9 +106,9 @@ static const size_t HEADER_BLOCK_ECC_LEN = 4;
static const u8 ECC_BLOCK_ID = 0xFF;
int vpd_reader(size_t size, u8 *data, void *userdata,
int (*fn)(void *userdata, u8 id, u8 version, u8 type,
size_t size, u8 const *data))
static int vpd_reader(size_t size, u8 *data, struct vpd_cache *userdata,
int (*fn)(struct vpd_cache *, u8 id, u8 version, u8 type,
size_t size, u8 const *data))
{
if (size < HEADER_BLOCK_LEN || !data || !fn)
return -EINVAL;
@ -194,3 +195,33 @@ int vpd_reader(size_t size, u8 *data, void *userdata,
return ret;
}
}
int read_vpd(struct vpd_cache *cache,
int (*process_block)(struct vpd_cache *, u8 id, u8 version,
u8 type, size_t size, u8 const *data))
{
static const size_t size = CONFIG_SYS_VPD_EEPROM_SIZE;
int res;
u8 *data;
unsigned int current_i2c_bus = i2c_get_bus_num();
res = i2c_set_bus_num(CONFIG_SYS_VPD_EEPROM_I2C_BUS);
if (res < 0)
return res;
data = malloc(size);
if (!data)
return -ENOMEM;
res = i2c_read(CONFIG_SYS_VPD_EEPROM_I2C_ADDR, 0,
CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN,
data, size);
if (res == 0)
res = vpd_reader(size, data, cache, process_block);
free(data);
i2c_set_bus_num(current_i2c_bus);
return res;
}

16
board/ge/common/vpd_reader.h
View File

@ -5,12 +5,18 @@
#include "common.h"
struct vpd_cache;
/*
* Read VPD from given data, verify content, and call callback
* for each vital product data block.
* Read VPD from given data, verify content, call callback for each vital
* product data block.
*
* cache: structure used by process block to store VPD information
* process_block: callback called for each VPD data block
*
* Returns Non-zero on error. Negative numbers encode errno.
*/
int vpd_reader(size_t size, u8 *data, void *userdata,
int (*fn)(void *userdata, u8 id, u8 version, u8 type,
size_t size, u8 const *data));
int read_vpd(struct vpd_cache *cache,
int (*process_block)(struct vpd_cache *,
u8 id, u8 version, u8 type,
size_t size, u8 const *data));

2
board/ge/mx53ppd/Kconfig
View File

@ -13,4 +13,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "mx53ppd"
source "board/ge/common/Kconfig"
endif

50
board/ge/mx53ppd/mx53ppd.c
View File

@ -40,13 +40,6 @@
DECLARE_GLOBAL_DATA_PTR;
/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
#define VPD_EEPROM_BUS 2
/* Address of 24C08 EEPROM. */
#define VPD_EEPROM_ADDR 0x50
#define VPD_EEPROM_ADDR_LEN 1
static u32 mx53_dram_size[2];
phys_size_t get_effective_memsize(void)
@ -297,10 +290,10 @@ struct vpd_cache {
/*
* Extracts MAC and product information from the VPD.
*/
static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size,
u8 const *data)
static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
u8 type, size_t size, u8 const *data)
{
struct vpd_cache *vpd = (struct vpd_cache *)userdata;
struct vpd_cache *vpd = userdata;
if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
size >= 1) {
@ -328,35 +321,6 @@ static void process_vpd(struct vpd_cache *vpd)
eth_env_set_enetaddr("ethaddr", vpd->mac1);
}
static int read_vpd(uint eeprom_bus)
{
struct vpd_cache vpd;
int res;
int size = 1024;
u8 *data;
unsigned int current_i2c_bus = i2c_get_bus_num();
res = i2c_set_bus_num(eeprom_bus);
if (res < 0)
return res;
data = malloc(size);
if (!data)
return -ENOMEM;
res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
if (res == 0) {
memset(&vpd, 0, sizeof(vpd));
vpd_reader(size, data, &vpd, vpd_callback);
process_vpd(&vpd);
}
free(data);
i2c_set_bus_num(current_i2c_bus);
return res;
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@ -389,8 +353,14 @@ int misc_init_r(void)
int board_late_init(void)
{
int res;
struct vpd_cache vpd;
read_vpd(VPD_EEPROM_BUS);
memset(&vpd, 0, sizeof(vpd));
res = read_vpd(&vpd, vpd_callback);
if (!res)
process_vpd(&vpd);
else
printf("Can't read VPD");
res = clock_1GHz();
if (res != 0)

1
common/image.c
View File

@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",},
{ IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",},
{ IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",},
{ IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",},
{ IH_TYPE_INVALID, "invalid", "Invalid Image", },
{ IH_TYPE_MULTI, "multi", "Multi-File Image", },
{ IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",},

1
common/spl/Kconfig
View File

@ -286,6 +286,7 @@ config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
depends on SPL_FIT
default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
default y if ARCH_IMX8M
help
Enable this to reduce the size of the FIT image loading code
in SPL, if space for the SPL binary is very tight.

21
common/spl/spl_fit.c
View File

@ -15,6 +15,15 @@
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
#endif
__weak void board_spl_fit_post_load(ulong load_addr, size_t length)
{
}
__weak ulong board_spl_fit_size_align(ulong size)
{
return size;
}
/**
* spl_fit_get_image_name(): By using the matching configuration subnode,
* retrieve the name of an image, specified by a property name and an index
@ -350,6 +359,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
*/
size = fdt_totalsize(fit);
size = (size + 3) & ~3;
size = board_spl_fit_size_align(size);
base_offset = (size + 3) & ~3;
/*
@ -373,8 +383,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
fit = spl_get_load_buffer(-hsize, hsize);
sectors = get_aligned_image_size(info, size, 0);
count = info->read(info, sector, sectors, fit);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
sector, sectors, fit, count);
debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
sector, sectors, fit, count, size);
if (count == 0)
return -EIO;
@ -510,5 +521,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0)
spl_image->entry_point = spl_image->load_addr;
spl_image->flags |= SPL_FIT_FOUND;
#ifdef CONFIG_SECURE_BOOT
board_spl_fit_post_load((ulong)fit, size);
#endif
return 0;
}

6
configs/cl-som-imx7_defconfig
View File

@ -43,8 +43,11 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
@ -56,12 +59,13 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MII=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y

9
configs/ge_bx50v3_defconfig
View File

@ -8,6 +8,15 @@ CONFIG_FIT=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# monitor's EEPROM is connected to the bus through the mux channel 1
# (the number is the offset in CONFIG_SYS_I2C_BUSES)
CONFIG_SYS_VPD_EEPROM_I2C_BUS=4
# Address of Atmel 24C08 EEPROM
CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50
CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN=1
CONFIG_SYS_VPD_EEPROM_SIZE=1024
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_LAST_STAGE_INIT=y

37
configs/imx8mq_evk_defconfig Normal file
View File

@ -0,0 +1,37 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_TARGET_IMX8MQ_EVK=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
CONFIG_OF_LIST="fsl-imx8mq-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
#CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPL=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y
CONFIG_FS_FAT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000

3
configs/mx23_olinuxino_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTEFI is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
@ -27,7 +28,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=59
CONFIG_LED_STATUS_BIT=778
CONFIG_LED_STATUS_STATE=2
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0

10
configs/mx53ppd_defconfig
View File

@ -9,6 +9,16 @@ CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# monitor's EEPROM is connected to the bus through the mux channel 1
# (the number is the offset in CONFIG_SYS_I2C_BUSES)
# (there is also Frame EEPROM connected to the channel 4 (bus 4))
CONFIG_SYS_VPD_EEPROM_I2C_BUS=2
# Address of Atmel 24C08 EEPROM
CONFIG_SYS_VPD_EEPROM_I2C_ADDR=0x50
CONFIG_SYS_VPD_EEPROM_I2C_ADDR_LEN=1
CONFIG_SYS_VPD_EEPROM_SIZE=1024
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y

48
configs/riotboard_spl_defconfig Normal file
View File

@ -0,0 +1,48 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,MX6S,DDR_MB=1024"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
CONFIG_SPL_OF_LIBFDT=y

2
configs/warp7_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set

37
doc/device-tree-bindings/w1/mxc-w1.txt Normal file
View File

@ -0,0 +1,37 @@
NXP i.MX (MXC) One wire bus master controller
=======================
Child nodes are required in device tree. The driver will detect
the devices serial number and then search in the child nodes in the device tree
for the proper node and try to match it with the device.
Also check doc/device-tree-bindings/w1-eeprom for possible child nodes drivers
Driver:
- drivers/w1/mxc_w1.c
Required properties:
- compatible : should be one of
"fsl,imx21-owire", "fsl,imx27-owire", "fsl,imx31-owire", "fsl,imx25-owire"
"fsl,imx25-owire", "fsl,imx35-owire", "fsl,imx50-owire", "fsl,imx53-owire"
- reg : Address and length of the register set for the device
Optional:
* none
Example:
onewire {
compatible = "fsl,imx53-owire";
reg = <0x63fa4000 0x4000>;
};
Example with child:
onewire {
compatible = "fsl,imx53-owire";
reg = <0x63fa4000 0x4000>;
eeprom1: eeprom@0 {
compatible = "maxim,ds24xxx";
};
};

2
doc/imx/mkimage/imximage.txt
View File

@ -175,7 +175,7 @@ Warning: setting sector offset for DOS compatiblity
We have set 255 heads, 63 sector. We have to set the cylinder.
The value to be set can be calculated with:
cilynder = <total size> / <heads> / <sectors> / <blocksize>
cylinder = <total size> / <heads> / <sectors> / <blocksize>
in this example,
1981284352 / 255 / 63 / 512 = 239.x = 239

4
doc/imx/mkimage/mxsimage.txt
View File

@ -46,7 +46,7 @@ These semantics and rules will be outlined now.
TAG [LAST]
- LAST :: Flag denoting the last section in the file
- After a "TAG" unstruction, any of the following instructions may follow
- After a "TAG" instruction, any of the following instructions may follow
in any order and any quantity:
NOOP
@ -142,7 +142,7 @@ These semantics and rules will be outlined now.
- An optional flags lines can be one of the following:
DISPLAYPROGRESS
- Enable boot progress output form the BootROM.
- Enable boot progress output from the BootROM.
- If the boot progress output from the BootROM is enabled, the BootROM will
produce a letter on the Debug UART for each instruction it started processing.

1
drivers/Makefile
View File

@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/

1
drivers/ddr/Kconfig
View File

@ -1 +1,2 @@
source "drivers/ddr/altera/Kconfig"
source "drivers/ddr/imx/Kconfig"

1
drivers/ddr/imx/Kconfig Normal file
View File

@ -0,0 +1 @@
source "drivers/ddr/imx/imx8m/Kconfig"

22
drivers/ddr/imx/imx8m/Kconfig Normal file
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@ -0,0 +1,22 @@
config IMX8M_DRAM
bool "imx8m dram"
config IMX8M_LPDDR4
bool "imx8m lpddr4"
select IMX8M_DRAM
help
Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
config IMX8M_DDR4
bool "imx8m ddr4"
select IMX8M_DRAM
help
Select the i.MX8M DDR4 driver support on i.MX8M SOC.
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
after DRAM is trained, need to save the dram related timming
info into memory for low power use. OCRAM_S is used for this
purpose on i.MX8MM.
default 0x180000

11
drivers/ddr/imx/imx8m/Makefile Normal file
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@ -0,0 +1,11 @@
#
# Copyright 2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o
endif

113
drivers/ddr/imx/imx8m/ddr4_init.c Normal file
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@ -0,0 +1,113 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8m_ddr.h>
#include <asm/arch/sys_proto.h>
void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
{
int i = 0;
for (i = 0; i < num; i++) {
reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
ddrc_cfg++;
}
}
void ddr_init(struct dram_timing_info *dram_timing)
{
volatile unsigned int tmp_t;
/*
* assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
* [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
* [4]src_system_rst_b!
*/
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F);
/* deassert [4]src_system_rst_b! */
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
/*
* change the clock source of dram_apb_clk_root
* to source 4 --800MHz/4
*/
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
dram_pll_init(DRAM_PLL_OUT_600M);
reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
/* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
reg32_write(DDRC_DBG1(0), 0x00000001);
reg32_write(DDRC_PWRCTL(0), 0x00000001);
while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
;
/* config the uMCTL2's registers */
ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
reg32_write(DDRC_RFSHCTL3(0), 0x00000001);
/* RESET: <ctn> DEASSERTED */
/* RESET: <a Port 0 DEASSERTED(0) */
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
reg32_write(DDRC_DBG1(0), 0x00000000);
reg32_write(DDRC_PWRCTL(0), 0x00000aa);
reg32_write(DDRC_SWCTL(0), 0x00000000);
reg32_write(DDRC_DFIMISC(0), 0x00000000);
/* config the DDR PHY's registers */
ddr_cfg_phy(dram_timing);
do {
tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
4 * 0x00020097);
} while (tmp_t != 0);
reg32_write(DDRC_DFIMISC(0), 0x00000020);
/* wait DFISTAT.dfi_init_complete to 1 */
while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
;
/* clear DFIMISC.dfi_init_complete_en */
reg32_write(DDRC_DFIMISC(0), 0x00000000);
/* set DFIMISC.dfi_init_complete_en again */
reg32_write(DDRC_DFIMISC(0), 0x00000001);
reg32_write(DDRC_PWRCTL(0), 0x0000088);
/*
* set SWCTL.sw_done to enable quasi-dynamic register
* programming outside reset.
*/
reg32_write(DDRC_SWCTL(0), 0x00000001);
/* wait SWSTAT.sw_done_ack to 1 */
while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
;
/* wait STAT to normal state */
while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
;
reg32_write(DDRC_PWRCTL(0), 0x0000088);
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
/* dis_auto-refresh is set to 0 */
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
}

732
drivers/ddr/imx/imx8m/ddrphy_csr.c Normal file
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@ -0,0 +1,732 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
/* ddr phy trained csr */
struct dram_cfg_param ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },
{ 0x1200b2, 0x0 },
{ 0x2200b2, 0x0 },
{ 0x200cb, 0x0 },
{ 0x10043, 0x0 },
{ 0x110043, 0x0 },
{ 0x210043, 0x0 },
{ 0x10143, 0x0 },
{ 0x110143, 0x0 },
{ 0x210143, 0x0 },
{ 0x11043, 0x0 },
{ 0x111043, 0x0 },
{ 0x211043, 0x0 },
{ 0x11143, 0x0 },
{ 0x111143, 0x0 },
{ 0x211143, 0x0 },
{ 0x12043, 0x0 },
{ 0x112043, 0x0 },
{ 0x212043, 0x0 },
{ 0x12143, 0x0 },
{ 0x112143, 0x0 },
{ 0x212143, 0x0 },
{ 0x13043, 0x0 },
{ 0x113043, 0x0 },
{ 0x213043, 0x0 },
{ 0x13143, 0x0 },
{ 0x113143, 0x0 },
{ 0x213143, 0x0 },
{ 0x80, 0x0 },
{ 0x100080, 0x0 },
{ 0x200080, 0x0 },
{ 0x1080, 0x0 },
{ 0x101080, 0x0 },
{ 0x201080, 0x0 },
{ 0x2080, 0x0 },
{ 0x102080, 0x0 },
{ 0x202080, 0x0 },
{ 0x3080, 0x0 },
{ 0x103080, 0x0 },
{ 0x203080, 0x0 },
{ 0x4080, 0x0 },
{ 0x104080, 0x0 },
{ 0x204080, 0x0 },
{ 0x5080, 0x0 },
{ 0x105080, 0x0 },
{ 0x205080, 0x0 },
{ 0x6080, 0x0 },
{ 0x106080, 0x0 },
{ 0x206080, 0x0 },
{ 0x7080, 0x0 },
{ 0x107080, 0x0 },
{ 0x207080, 0x0 },
{ 0x8080, 0x0 },
{ 0x108080, 0x0 },
{ 0x208080, 0x0 },
{ 0x9080, 0x0 },
{ 0x109080, 0x0 },
{ 0x209080, 0x0 },
{ 0x10080, 0x0 },
{ 0x110080, 0x0 },
{ 0x210080, 0x0 },
{ 0x10180, 0x0 },
{ 0x110180, 0x0 },
{ 0x210180, 0x0 },
{ 0x11080, 0x0 },
{ 0x111080, 0x0 },
{ 0x211080, 0x0 },
{ 0x11180, 0x0 },
{ 0x111180, 0x0 },
{ 0x211180, 0x0 },
{ 0x12080, 0x0 },
{ 0x112080, 0x0 },
{ 0x212080, 0x0 },
{ 0x12180, 0x0 },
{ 0x112180, 0x0 },
{ 0x212180, 0x0 },
{ 0x13080, 0x0 },
{ 0x113080, 0x0 },
{ 0x213080, 0x0 },
{ 0x13180, 0x0 },
{ 0x113180, 0x0 },
{ 0x213180, 0x0 },
{ 0x10081, 0x0 },
{ 0x110081, 0x0 },
{ 0x210081, 0x0 },
{ 0x10181, 0x0 },
{ 0x110181, 0x0 },
{ 0x210181, 0x0 },
{ 0x11081, 0x0 },
{ 0x111081, 0x0 },
{ 0x211081, 0x0 },
{ 0x11181, 0x0 },
{ 0x111181, 0x0 },
{ 0x211181, 0x0 },
{ 0x12081, 0x0 },
{ 0x112081, 0x0 },
{ 0x212081, 0x0 },
{ 0x12181, 0x0 },
{ 0x112181, 0x0 },
{ 0x212181, 0x0 },
{ 0x13081, 0x0 },
{ 0x113081, 0x0 },
{ 0x213081, 0x0 },
{ 0x13181, 0x0 },
{ 0x113181, 0x0 },
{ 0x213181, 0x0 },
{ 0x100d0, 0x0 },
{ 0x1100d0, 0x0 },
{ 0x2100d0, 0x0 },
{ 0x101d0, 0x0 },
{ 0x1101d0, 0x0 },
{ 0x2101d0, 0x0 },
{ 0x110d0, 0x0 },
{ 0x1110d0, 0x0 },
{ 0x2110d0, 0x0 },
{ 0x111d0, 0x0 },
{ 0x1111d0, 0x0 },
{ 0x2111d0, 0x0 },
{ 0x120d0, 0x0 },
{ 0x1120d0, 0x0 },
{ 0x2120d0, 0x0 },
{ 0x121d0, 0x0 },
{ 0x1121d0, 0x0 },
{ 0x2121d0, 0x0 },
{ 0x130d0, 0x0 },
{ 0x1130d0, 0x0 },
{ 0x2130d0, 0x0 },
{ 0x131d0, 0x0 },
{ 0x1131d0, 0x0 },
{ 0x2131d0, 0x0 },
{ 0x100d1, 0x0 },
{ 0x1100d1, 0x0 },
{ 0x2100d1, 0x0 },
{ 0x101d1, 0x0 },
{ 0x1101d1, 0x0 },
{ 0x2101d1, 0x0 },
{ 0x110d1, 0x0 },
{ 0x1110d1, 0x0 },
{ 0x2110d1, 0x0 },
{ 0x111d1, 0x0 },
{ 0x1111d1, 0x0 },
{ 0x2111d1, 0x0 },
{ 0x120d1, 0x0 },
{ 0x1120d1, 0x0 },
{ 0x2120d1, 0x0 },
{ 0x121d1, 0x0 },
{ 0x1121d1, 0x0 },
{ 0x2121d1, 0x0 },
{ 0x130d1, 0x0 },
{ 0x1130d1, 0x0 },
{ 0x2130d1, 0x0 },
{ 0x131d1, 0x0 },
{ 0x1131d1, 0x0 },
{ 0x2131d1, 0x0 },
{ 0x10068, 0x0 },
{ 0x10168, 0x0 },
{ 0x10268, 0x0 },
{ 0x10368, 0x0 },
{ 0x10468, 0x0 },
{ 0x10568, 0x0 },
{ 0x10668, 0x0 },
{ 0x10768, 0x0 },
{ 0x10868, 0x0 },
{ 0x11068, 0x0 },
{ 0x11168, 0x0 },
{ 0x11268, 0x0 },
{ 0x11368, 0x0 },
{ 0x11468, 0x0 },
{ 0x11568, 0x0 },
{ 0x11668, 0x0 },
{ 0x11768, 0x0 },
{ 0x11868, 0x0 },
{ 0x12068, 0x0 },
{ 0x12168, 0x0 },
{ 0x12268, 0x0 },
{ 0x12368, 0x0 },
{ 0x12468, 0x0 },
{ 0x12568, 0x0 },
{ 0x12668, 0x0 },
{ 0x12768, 0x0 },
{ 0x12868, 0x0 },
{ 0x13068, 0x0 },
{ 0x13168, 0x0 },
{ 0x13268, 0x0 },
{ 0x13368, 0x0 },
{ 0x13468, 0x0 },
{ 0x13568, 0x0 },
{ 0x13668, 0x0 },
{ 0x13768, 0x0 },
{ 0x13868, 0x0 },
{ 0x10069, 0x0 },
{ 0x10169, 0x0 },
{ 0x10269, 0x0 },
{ 0x10369, 0x0 },
{ 0x10469, 0x0 },
{ 0x10569, 0x0 },
{ 0x10669, 0x0 },
{ 0x10769, 0x0 },
{ 0x10869, 0x0 },
{ 0x11069, 0x0 },
{ 0x11169, 0x0 },
{ 0x11269, 0x0 },
{ 0x11369, 0x0 },
{ 0x11469, 0x0 },
{ 0x11569, 0x0 },
{ 0x11669, 0x0 },
{ 0x11769, 0x0 },
{ 0x11869, 0x0 },
{ 0x12069, 0x0 },
{ 0x12169, 0x0 },
{ 0x12269, 0x0 },
{ 0x12369, 0x0 },
{ 0x12469, 0x0 },
{ 0x12569, 0x0 },
{ 0x12669, 0x0 },
{ 0x12769, 0x0 },
{ 0x12869, 0x0 },
{ 0x13069, 0x0 },
{ 0x13169, 0x0 },
{ 0x13269, 0x0 },
{ 0x13369, 0x0 },
{ 0x13469, 0x0 },
{ 0x13569, 0x0 },
{ 0x13669, 0x0 },
{ 0x13769, 0x0 },
{ 0x13869, 0x0 },
{ 0x1008c, 0x0 },
{ 0x11008c, 0x0 },
{ 0x21008c, 0x0 },
{ 0x1018c, 0x0 },
{ 0x11018c, 0x0 },
{ 0x21018c, 0x0 },
{ 0x1108c, 0x0 },
{ 0x11108c, 0x0 },
{ 0x21108c, 0x0 },
{ 0x1118c, 0x0 },
{ 0x11118c, 0x0 },
{ 0x21118c, 0x0 },
{ 0x1208c, 0x0 },
{ 0x11208c, 0x0 },
{ 0x21208c, 0x0 },
{ 0x1218c, 0x0 },
{ 0x11218c, 0x0 },
{ 0x21218c, 0x0 },
{ 0x1308c, 0x0 },
{ 0x11308c, 0x0 },
{ 0x21308c, 0x0 },
{ 0x1318c, 0x0 },
{ 0x11318c, 0x0 },
{ 0x21318c, 0x0 },
{ 0x1008d, 0x0 },
{ 0x11008d, 0x0 },
{ 0x21008d, 0x0 },
{ 0x1018d, 0x0 },
{ 0x11018d, 0x0 },
{ 0x21018d, 0x0 },
{ 0x1108d, 0x0 },
{ 0x11108d, 0x0 },
{ 0x21108d, 0x0 },
{ 0x1118d, 0x0 },
{ 0x11118d, 0x0 },
{ 0x21118d, 0x0 },
{ 0x1208d, 0x0 },
{ 0x11208d, 0x0 },
{ 0x21208d, 0x0 },
{ 0x1218d, 0x0 },
{ 0x11218d, 0x0 },
{ 0x21218d, 0x0 },
{ 0x1308d, 0x0 },
{ 0x11308d, 0x0 },
{ 0x21308d, 0x0 },
{ 0x1318d, 0x0 },
{ 0x11318d, 0x0 },
{ 0x21318d, 0x0 },
{ 0x100c0, 0x0 },
{ 0x1100c0, 0x0 },
{ 0x2100c0, 0x0 },
{ 0x101c0, 0x0 },
{ 0x1101c0, 0x0 },
{ 0x2101c0, 0x0 },
{ 0x102c0, 0x0 },
{ 0x1102c0, 0x0 },
{ 0x2102c0, 0x0 },
{ 0x103c0, 0x0 },
{ 0x1103c0, 0x0 },
{ 0x2103c0, 0x0 },
{ 0x104c0, 0x0 },
{ 0x1104c0, 0x0 },
{ 0x2104c0, 0x0 },
{ 0x105c0, 0x0 },
{ 0x1105c0, 0x0 },
{ 0x2105c0, 0x0 },
{ 0x106c0, 0x0 },
{ 0x1106c0, 0x0 },
{ 0x2106c0, 0x0 },
{ 0x107c0, 0x0 },
{ 0x1107c0, 0x0 },
{ 0x2107c0, 0x0 },
{ 0x108c0, 0x0 },
{ 0x1108c0, 0x0 },
{ 0x2108c0, 0x0 },
{ 0x110c0, 0x0 },
{ 0x1110c0, 0x0 },
{ 0x2110c0, 0x0 },
{ 0x111c0, 0x0 },
{ 0x1111c0, 0x0 },
{ 0x2111c0, 0x0 },
{ 0x112c0, 0x0 },
{ 0x1112c0, 0x0 },
{ 0x2112c0, 0x0 },
{ 0x113c0, 0x0 },
{ 0x1113c0, 0x0 },
{ 0x2113c0, 0x0 },
{ 0x114c0, 0x0 },
{ 0x1114c0, 0x0 },
{ 0x2114c0, 0x0 },
{ 0x115c0, 0x0 },
{ 0x1115c0, 0x0 },
{ 0x2115c0, 0x0 },
{ 0x116c0, 0x0 },
{ 0x1116c0, 0x0 },
{ 0x2116c0, 0x0 },
{ 0x117c0, 0x0 },
{ 0x1117c0, 0x0 },
{ 0x2117c0, 0x0 },
{ 0x118c0, 0x0 },
{ 0x1118c0, 0x0 },
{ 0x2118c0, 0x0 },
{ 0x120c0, 0x0 },
{ 0x1120c0, 0x0 },
{ 0x2120c0, 0x0 },
{ 0x121c0, 0x0 },
{ 0x1121c0, 0x0 },
{ 0x2121c0, 0x0 },
{ 0x122c0, 0x0 },
{ 0x1122c0, 0x0 },
{ 0x2122c0, 0x0 },
{ 0x123c0, 0x0 },
{ 0x1123c0, 0x0 },
{ 0x2123c0, 0x0 },
{ 0x124c0, 0x0 },
{ 0x1124c0, 0x0 },
{ 0x2124c0, 0x0 },
{ 0x125c0, 0x0 },
{ 0x1125c0, 0x0 },
{ 0x2125c0, 0x0 },
{ 0x126c0, 0x0 },
{ 0x1126c0, 0x0 },
{ 0x2126c0, 0x0 },
{ 0x127c0, 0x0 },
{ 0x1127c0, 0x0 },
{ 0x2127c0, 0x0 },
{ 0x128c0, 0x0 },
{ 0x1128c0, 0x0 },
{ 0x2128c0, 0x0 },
{ 0x130c0, 0x0 },
{ 0x1130c0, 0x0 },
{ 0x2130c0, 0x0 },
{ 0x131c0, 0x0 },
{ 0x1131c0, 0x0 },
{ 0x2131c0, 0x0 },
{ 0x132c0, 0x0 },
{ 0x1132c0, 0x0 },
{ 0x2132c0, 0x0 },
{ 0x133c0, 0x0 },
{ 0x1133c0, 0x0 },
{ 0x2133c0, 0x0 },
{ 0x134c0, 0x0 },
{ 0x1134c0, 0x0 },
{ 0x2134c0, 0x0 },
{ 0x135c0, 0x0 },
{ 0x1135c0, 0x0 },
{ 0x2135c0, 0x0 },
{ 0x136c0, 0x0 },
{ 0x1136c0, 0x0 },
{ 0x2136c0, 0x0 },
{ 0x137c0, 0x0 },
{ 0x1137c0, 0x0 },
{ 0x2137c0, 0x0 },
{ 0x138c0, 0x0 },
{ 0x1138c0, 0x0 },
{ 0x2138c0, 0x0 },
{ 0x100c1, 0x0 },
{ 0x1100c1, 0x0 },
{ 0x2100c1, 0x0 },
{ 0x101c1, 0x0 },
{ 0x1101c1, 0x0 },
{ 0x2101c1, 0x0 },
{ 0x102c1, 0x0 },
{ 0x1102c1, 0x0 },
{ 0x2102c1, 0x0 },
{ 0x103c1, 0x0 },
{ 0x1103c1, 0x0 },
{ 0x2103c1, 0x0 },
{ 0x104c1, 0x0 },
{ 0x1104c1, 0x0 },
{ 0x2104c1, 0x0 },
{ 0x105c1, 0x0 },
{ 0x1105c1, 0x0 },
{ 0x2105c1, 0x0 },
{ 0x106c1, 0x0 },
{ 0x1106c1, 0x0 },
{ 0x2106c1, 0x0 },
{ 0x107c1, 0x0 },
{ 0x1107c1, 0x0 },
{ 0x2107c1, 0x0 },
{ 0x108c1, 0x0 },
{ 0x1108c1, 0x0 },
{ 0x2108c1, 0x0 },
{ 0x110c1, 0x0 },
{ 0x1110c1, 0x0 },
{ 0x2110c1, 0x0 },
{ 0x111c1, 0x0 },
{ 0x1111c1, 0x0 },
{ 0x2111c1, 0x0 },
{ 0x112c1, 0x0 },
{ 0x1112c1, 0x0 },
{ 0x2112c1, 0x0 },
{ 0x113c1, 0x0 },
{ 0x1113c1, 0x0 },
{ 0x2113c1, 0x0 },
{ 0x114c1, 0x0 },
{ 0x1114c1, 0x0 },
{ 0x2114c1, 0x0 },
{ 0x115c1, 0x0 },
{ 0x1115c1, 0x0 },
{ 0x2115c1, 0x0 },
{ 0x116c1, 0x0 },
{ 0x1116c1, 0x0 },
{ 0x2116c1, 0x0 },
{ 0x117c1, 0x0 },
{ 0x1117c1, 0x0 },
{ 0x2117c1, 0x0 },
{ 0x118c1, 0x0 },
{ 0x1118c1, 0x0 },
{ 0x2118c1, 0x0 },
{ 0x120c1, 0x0 },
{ 0x1120c1, 0x0 },
{ 0x2120c1, 0x0 },
{ 0x121c1, 0x0 },
{ 0x1121c1, 0x0 },
{ 0x2121c1, 0x0 },
{ 0x122c1, 0x0 },
{ 0x1122c1, 0x0 },
{ 0x2122c1, 0x0 },
{ 0x123c1, 0x0 },
{ 0x1123c1, 0x0 },
{ 0x2123c1, 0x0 },
{ 0x124c1, 0x0 },
{ 0x1124c1, 0x0 },
{ 0x2124c1, 0x0 },
{ 0x125c1, 0x0 },
{ 0x1125c1, 0x0 },
{ 0x2125c1, 0x0 },
{ 0x126c1, 0x0 },
{ 0x1126c1, 0x0 },
{ 0x2126c1, 0x0 },
{ 0x127c1, 0x0 },
{ 0x1127c1, 0x0 },
{ 0x2127c1, 0x0 },
{ 0x128c1, 0x0 },
{ 0x1128c1, 0x0 },
{ 0x2128c1, 0x0 },
{ 0x130c1, 0x0 },
{ 0x1130c1, 0x0 },
{ 0x2130c1, 0x0 },
{ 0x131c1, 0x0 },
{ 0x1131c1, 0x0 },
{ 0x2131c1, 0x0 },
{ 0x132c1, 0x0 },
{ 0x1132c1, 0x0 },
{ 0x2132c1, 0x0 },
{ 0x133c1, 0x0 },
{ 0x1133c1, 0x0 },
{ 0x2133c1, 0x0 },
{ 0x134c1, 0x0 },
{ 0x1134c1, 0x0 },
{ 0x2134c1, 0x0 },
{ 0x135c1, 0x0 },
{ 0x1135c1, 0x0 },
{ 0x2135c1, 0x0 },
{ 0x136c1, 0x0 },
{ 0x1136c1, 0x0 },
{ 0x2136c1, 0x0 },
{ 0x137c1, 0x0 },
{ 0x1137c1, 0x0 },
{ 0x2137c1, 0x0 },
{ 0x138c1, 0x0 },
{ 0x1138c1, 0x0 },
{ 0x2138c1, 0x0 },
{ 0x10020, 0x0 },
{ 0x110020, 0x0 },
{ 0x210020, 0x0 },
{ 0x11020, 0x0 },
{ 0x111020, 0x0 },
{ 0x211020, 0x0 },
{ 0x12020, 0x0 },
{ 0x112020, 0x0 },
{ 0x212020, 0x0 },
{ 0x13020, 0x0 },
{ 0x113020, 0x0 },
{ 0x213020, 0x0 },
{ 0x20072, 0x0 },
{ 0x20073, 0x0 },
{ 0x20074, 0x0 },
{ 0x100aa, 0x0 },
{ 0x110aa, 0x0 },
{ 0x120aa, 0x0 },
{ 0x130aa, 0x0 },
{ 0x20010, 0x0 },
{ 0x120010, 0x0 },
{ 0x220010, 0x0 },
{ 0x20011, 0x0 },
{ 0x120011, 0x0 },
{ 0x220011, 0x0 },
{ 0x100ae, 0x0 },
{ 0x1100ae, 0x0 },
{ 0x2100ae, 0x0 },
{ 0x100af, 0x0 },
{ 0x1100af, 0x0 },
{ 0x2100af, 0x0 },
{ 0x110ae, 0x0 },
{ 0x1110ae, 0x0 },
{ 0x2110ae, 0x0 },
{ 0x110af, 0x0 },
{ 0x1110af, 0x0 },
{ 0x2110af, 0x0 },
{ 0x120ae, 0x0 },
{ 0x1120ae, 0x0 },
{ 0x2120ae, 0x0 },
{ 0x120af, 0x0 },
{ 0x1120af, 0x0 },
{ 0x2120af, 0x0 },
{ 0x130ae, 0x0 },
{ 0x1130ae, 0x0 },
{ 0x2130ae, 0x0 },
{ 0x130af, 0x0 },
{ 0x1130af, 0x0 },
{ 0x2130af, 0x0 },
{ 0x20020, 0x0 },
{ 0x120020, 0x0 },
{ 0x220020, 0x0 },
{ 0x100a0, 0x0 },
{ 0x100a1, 0x0 },
{ 0x100a2, 0x0 },
{ 0x100a3, 0x0 },
{ 0x100a4, 0x0 },
{ 0x100a5, 0x0 },
{ 0x100a6, 0x0 },
{ 0x100a7, 0x0 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x0 },
{ 0x110a2, 0x0 },
{ 0x110a3, 0x0 },
{ 0x110a4, 0x0 },
{ 0x110a5, 0x0 },
{ 0x110a6, 0x0 },
{ 0x110a7, 0x0 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x0 },
{ 0x120a2, 0x0 },
{ 0x120a3, 0x0 },
{ 0x120a4, 0x0 },
{ 0x120a5, 0x0 },
{ 0x120a6, 0x0 },
{ 0x120a7, 0x0 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x0 },
{ 0x130a2, 0x0 },
{ 0x130a3, 0x0 },
{ 0x130a4, 0x0 },
{ 0x130a5, 0x0 },
{ 0x130a6, 0x0 },
{ 0x130a7, 0x0 },
{ 0x2007c, 0x0 },
{ 0x12007c, 0x0 },
{ 0x22007c, 0x0 },
{ 0x2007d, 0x0 },
{ 0x12007d, 0x0 },
{ 0x22007d, 0x0 },
{ 0x400fd, 0x0 },
{ 0x400c0, 0x0 },
{ 0x90201, 0x0 },
{ 0x190201, 0x0 },
{ 0x290201, 0x0 },
{ 0x90202, 0x0 },
{ 0x190202, 0x0 },
{ 0x290202, 0x0 },
{ 0x90203, 0x0 },
{ 0x190203, 0x0 },
{ 0x290203, 0x0 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
{ 0x90205, 0x0 },
{ 0x190205, 0x0 },
{ 0x290205, 0x0 },
{ 0x90206, 0x0 },
{ 0x190206, 0x0 },
{ 0x290206, 0x0 },
{ 0x90207, 0x0 },
{ 0x190207, 0x0 },
{ 0x290207, 0x0 },
{ 0x90208, 0x0 },
{ 0x190208, 0x0 },
{ 0x290208, 0x0 },
{ 0x10062, 0x0 },
{ 0x10162, 0x0 },
{ 0x10262, 0x0 },
{ 0x10362, 0x0 },
{ 0x10462, 0x0 },
{ 0x10562, 0x0 },
{ 0x10662, 0x0 },
{ 0x10762, 0x0 },
{ 0x10862, 0x0 },
{ 0x11062, 0x0 },
{ 0x11162, 0x0 },
{ 0x11262, 0x0 },
{ 0x11362, 0x0 },
{ 0x11462, 0x0 },
{ 0x11562, 0x0 },
{ 0x11662, 0x0 },
{ 0x11762, 0x0 },
{ 0x11862, 0x0 },
{ 0x12062, 0x0 },
{ 0x12162, 0x0 },
{ 0x12262, 0x0 },
{ 0x12362, 0x0 },
{ 0x12462, 0x0 },
{ 0x12562, 0x0 },
{ 0x12662, 0x0 },
{ 0x12762, 0x0 },
{ 0x12862, 0x0 },
{ 0x13062, 0x0 },
{ 0x13162, 0x0 },
{ 0x13262, 0x0 },
{ 0x13362, 0x0 },
{ 0x13462, 0x0 },
{ 0x13562, 0x0 },
{ 0x13662, 0x0 },
{ 0x13762, 0x0 },
{ 0x13862, 0x0 },
{ 0x20077, 0x0 },
{ 0x10001, 0x0 },
{ 0x11001, 0x0 },
{ 0x12001, 0x0 },
{ 0x13001, 0x0 },
{ 0x10040, 0x0 },
{ 0x10140, 0x0 },
{ 0x10240, 0x0 },
{ 0x10340, 0x0 },
{ 0x10440, 0x0 },
{ 0x10540, 0x0 },
{ 0x10640, 0x0 },
{ 0x10740, 0x0 },
{ 0x10840, 0x0 },
{ 0x10030, 0x0 },
{ 0x10130, 0x0 },
{ 0x10230, 0x0 },
{ 0x10330, 0x0 },
{ 0x10430, 0x0 },
{ 0x10530, 0x0 },
{ 0x10630, 0x0 },
{ 0x10730, 0x0 },
{ 0x10830, 0x0 },
{ 0x11040, 0x0 },
{ 0x11140, 0x0 },
{ 0x11240, 0x0 },
{ 0x11340, 0x0 },
{ 0x11440, 0x0 },
{ 0x11540, 0x0 },
{ 0x11640, 0x0 },
{ 0x11740, 0x0 },
{ 0x11840, 0x0 },
{ 0x11030, 0x0 },
{ 0x11130, 0x0 },
{ 0x11230, 0x0 },
{ 0x11330, 0x0 },
{ 0x11430, 0x0 },
{ 0x11530, 0x0 },
{ 0x11630, 0x0 },
{ 0x11730, 0x0 },
{ 0x11830, 0x0 },
{ 0x12040, 0x0 },
{ 0x12140, 0x0 },
{ 0x12240, 0x0 },
{ 0x12340, 0x0 },
{ 0x12440, 0x0 },
{ 0x12540, 0x0 },
{ 0x12640, 0x0 },
{ 0x12740, 0x0 },
{ 0x12840, 0x0 },
{ 0x12030, 0x0 },
{ 0x12130, 0x0 },
{ 0x12230, 0x0 },
{ 0x12330, 0x0 },
{ 0x12430, 0x0 },
{ 0x12530, 0x0 },
{ 0x12630, 0x0 },
{ 0x12730, 0x0 },
{ 0x12830, 0x0 },
{ 0x13040, 0x0 },
{ 0x13140, 0x0 },
{ 0x13240, 0x0 },
{ 0x13340, 0x0 },
{ 0x13440, 0x0 },
{ 0x13540, 0x0 },
{ 0x13640, 0x0 },
{ 0x13740, 0x0 },
{ 0x13840, 0x0 },
{ 0x13030, 0x0 },
{ 0x13130, 0x0 },
{ 0x13230, 0x0 },
{ 0x13330, 0x0 },
{ 0x13430, 0x0 },
{ 0x13530, 0x0 },
{ 0x13630, 0x0 },
{ 0x13730, 0x0 },
{ 0x13830, 0x0 },
};
uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr);

86
drivers/ddr/imx/imx8m/ddrphy_train.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
void ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
unsigned int num;
int i = 0;
int j = 0;
/* initialize PHY configuration */
dram_cfg = dram_timing->ddrphy_cfg;
num = dram_timing->ddrphy_cfg_num;
for (i = 0; i < num; i++) {
/* config phy reg */
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
/* load the frequency setpoint message block config */
fsp_msg = dram_timing->fsp_msg;
for (i = 0; i < dram_timing->fsp_msg_num; i++) {
debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
/* set dram PHY input clocks to desired frequency */
ddrphy_init_set_dfi_clk(fsp_msg->drate);
/* load the dram training firmware image */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddr_load_train_firmware(fsp_msg->fw_type);
/* load the frequency set point message block parameter */
dram_cfg = fsp_msg->fsp_cfg;
num = fsp_msg->fsp_cfg_num;
for (j = 0; j < num; j++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
/*
* -------------------- excute the firmware --------------------
* Running the firmware is a simply process to taking the
* PMU out of reset and stall, then the firwmare will be run
* 1. reset the PMU;
* 2. begin the excution;
* 3. wait for the training done;
* 4. read the message block result.
* -------------------------------------------------------------
*/
dwc_ddrphy_apb_wr(0xd0000, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x9);
dwc_ddrphy_apb_wr(0xd0099, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x0);
/* Wait for the training firmware to complete */
wait_ddrphy_training_complete();
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
/* Read the Message Block results */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddrphy_init_read_msg_block(fsp_msg->fw_type);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
fsp_msg++;
}
/* Load PHY Init Engine Image */
dram_cfg = dram_timing->ddrphy_pie;
num = dram_timing->ddrphy_pie_num;
for (i = 0; i < num; i++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
/* save the ddr PHY trained CSR in memory for low power use */
ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
}

186
drivers/ddr/imx/imx8m/ddrphy_utils.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
static inline void poll_pmu_message_ready(void)
{
unsigned int reg;
do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
} while (reg & 0x1);
}
static inline void ack_pmu_message_receive(void)
{
unsigned int reg;
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
} while (!(reg & 0x1));
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
}
static inline unsigned int get_mail(void)
{
unsigned int reg;
poll_pmu_message_ready();
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
ack_pmu_message_receive();
return reg;
}
static inline unsigned int get_stream_message(void)
{
unsigned int reg, reg2;
poll_pmu_message_ready();
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
reg2 = (reg2 << 16) | reg;
ack_pmu_message_receive();
return reg2;
}
static inline void decode_major_message(unsigned int mail)
{
debug("[PMU Major message = 0x%08x]\n", mail);
}
static inline void decode_streaming_message(void)
{
unsigned int string_index, arg __maybe_unused;
int i = 0;
string_index = get_stream_message();
debug("PMU String index = 0x%08x\n", string_index);
while (i < (string_index & 0xffff)) {
arg = get_stream_message();
debug("arg[%d] = 0x%08x\n", i, arg);
i++;
}
debug("\n");
}
void wait_ddrphy_training_complete(void)
{
unsigned int mail;
while (1) {
mail = get_mail();
decode_major_message(mail);
if (mail == 0x08) {
decode_streaming_message();
} else if (mail == 0x07) {
debug("Training PASS\n");
break;
} else if (mail == 0xff) {
printf("Training FAILED\n");
break;
}
}
}
void ddrphy_init_set_dfi_clk(unsigned int drate)
{
switch (drate) {
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
break;
case 3000:
dram_pll_init(MHZ(750));
dram_disable_bypass();
break;
case 2400:
dram_pll_init(MHZ(600));
dram_disable_bypass();
break;
case 1600:
dram_pll_init(MHZ(400));
dram_disable_bypass();
break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
break;
case 400:
dram_enable_bypass(MHZ(400));
break;
case 100:
dram_enable_bypass(MHZ(100));
break;
default:
return;
}
}
void ddrphy_init_read_msg_block(enum fw_type type)
{
}
void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
unsigned int mr_data)
{
unsigned int tmp;
/*
* 1. Poll MRSTAT.mr_wr_busy until it is 0.
* This checks that there is no outstanding MR transaction.
* No writes should be performed to MRCTRL0 and MRCTRL1 if
* MRSTAT.mr_wr_busy = 1.
*/
do {
tmp = reg32_read(DDRC_MRSTAT(0));
} while (tmp & 0x1);
/*
* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
* (for MRWs) MRCTRL1.mr_data to define the MR transaction.
*/
reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
reg32setbit(DDRC_MRCTRL0(0), 31);
}
unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
{
unsigned int tmp;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
do {
tmp = reg32_read(DDRC_MRSTAT(0));
} while (tmp & 0x1);
reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
reg32setbit(DDRC_MRCTRL0(0), 31);
do {
tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
} while ((tmp & 0x8) == 0);
tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
tmp = tmp & 0xff;
reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
return tmp;
}

170
drivers/ddr/imx/imx8m/helper.c Normal file
View File

@ -0,0 +1,170 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
#define IMEM_LEN 32768 /* byte */
#define DMEM_LEN 16384 /* byte */
#define IMEM_2D_OFFSET 49152
#define IMEM_OFFSET_ADDR 0x00050000
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
u32 tmp32, i;
u32 error = 0;
unsigned long pr_to32, pr_from32;
unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
unsigned long imem_start = (unsigned long)&_end + fw_offset;
unsigned long dmem_start = imem_start + IMEM_LEN;
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
for (i = 0x0; i < IMEM_LEN; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x0000ffff, pr_to32);
pr_to32 += 4;
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
pr_to32 += 4;
pr_from32 += 4;
i += 4;
}
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
for (i = 0x0; i < DMEM_LEN; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x0000ffff, pr_to32);
pr_to32 += 4;
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
pr_to32 += 4;
pr_from32 += 4;
i += 4;
}
debug("check ddr4_pmu_train_imem code\n");
pr_from32 = imem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
for (i = 0x0; i < IMEM_LEN; ) {
tmp32 = (readw(pr_to32) & 0x0000ffff);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
if (tmp32 != readl(pr_from32)) {
debug("%lx %lx\n", pr_from32, pr_to32);
error++;
}
pr_from32 += 4;
pr_to32 += 4;
i += 4;
}
if (error)
printf("check ddr4_pmu_train_imem code fail=%d\n", error);
else
debug("check ddr4_pmu_train_imem code pass\n");
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
for (i = 0x0; i < DMEM_LEN;) {
tmp32 = (readw(pr_to32) & 0x0000ffff);
pr_to32 += 4;
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
if (tmp32 != readl(pr_from32)) {
debug("%lx %lx\n", pr_from32, pr_to32);
error++;
}
pr_from32 += 4;
pr_to32 += 4;
i += 4;
}
if (error)
printf("check ddr4_pmu_train_dmem code fail=%d", error);
else
debug("check ddr4_pmu_train_dmem code pass\n");
}
void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
unsigned int num)
{
int i = 0;
/* enable the ddrphy apb */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
dwc_ddrphy_apb_wr(0xc0080, 0x3);
for (i = 0; i < num; i++) {
ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
ddrphy_csr++;
}
/* disable the ddrphy apb */
dwc_ddrphy_apb_wr(0xc0080, 0x2);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
}
void dram_config_save(struct dram_timing_info *timing_info,
unsigned long saved_timing_base)
{
int i = 0;
struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
struct dram_cfg_param *cfg;
saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
/* save the fsp table */
for (i = 0; i < 4; i++)
saved_timing->fsp_table[i] = timing_info->fsp_table[i];
cfg = (struct dram_cfg_param *)(saved_timing_base +
sizeof(*timing_info));
/* save ddrc config */
saved_timing->ddrc_cfg = cfg;
for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
cfg->reg = timing_info->ddrc_cfg[i].reg;
cfg->val = timing_info->ddrc_cfg[i].val;
cfg++;
}
/* save ddrphy config */
saved_timing->ddrphy_cfg = cfg;
for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
cfg->reg = timing_info->ddrphy_cfg[i].reg;
cfg->val = timing_info->ddrphy_cfg[i].val;
cfg++;
}
/* save the ddrphy csr */
saved_timing->ddrphy_trained_csr = cfg;
for (i = 0; i < ddrphy_trained_csr_num; i++) {
cfg->reg = ddrphy_trained_csr[i].reg;
cfg->val = ddrphy_trained_csr[i].val;
cfg++;
}
/* save the ddrphy pie */
saved_timing->ddrphy_pie = cfg;
for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
cfg->reg = timing_info->ddrphy_pie[i].reg;
cfg->val = timing_info->ddrphy_pie[i].val;
cfg++;
}
}

188
drivers/ddr/imx/imx8m/lpddr4_init.c Normal file
View File

@ -0,0 +1,188 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/arch/sys_proto.h>
void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
{
int i = 0;
for (i = 0; i < num; i++) {
reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
ddrc_cfg++;
}
}
void ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp;
debug("DDRINFO: start lpddr4 ddr init\n");
/* step 1: reset */
if (is_imx8mq()) {
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
} else {
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
}
mdelay(100);
debug("DDRINFO: reset done\n");
/*
* change the clock source of dram_apb_clk_root:
* source 4 800MHz /4 = 200MHz
*/
clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(4) |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
/* disable iso */
reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
debug("DDRINFO: cfg clk\n");
dram_pll_init(MHZ(750));
/*
* release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
* [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
*/
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
/*step2 Configure uMCTL2's registers */
debug("DDRINFO: ddrc config start\n");
lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
debug("DDRINFO: ddrc config done\n");
/*
* step3 de-assert all reset
* RESET: <core_ddrc_rstn> DEASSERTED
* RESET: <aresetn> for Port 0 DEASSERT(0)ED
*/
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
reg32_write(DDRC_DBG1(0), 0x00000000);
/* step4 */
/* [0]dis_auto_refresh=1 */
reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
/* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */
reg32_write(DDRC_PWRCTL(0), 0x000000a8);
do {
tmp = reg32_read(DDRC_STAT(0));
} while ((tmp & 0x33f) != 0x223);
reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
/* step5 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* step6 */
tmp = reg32_read(DDRC_MSTR2(0));
if (tmp == 0x2)
reg32_write(DDRC_DFIMISC(0), 0x00000210);
else if (tmp == 0x1)
reg32_write(DDRC_DFIMISC(0), 0x00000110);
else
reg32_write(DDRC_DFIMISC(0), 0x00000010);
/* step7 [0]--1: disable quasi-dynamic programming */
reg32_write(DDRC_SWCTL(0), 0x00000001);
/* step8 Configure LPDDR4 PHY's registers */
debug("DDRINFO:ddrphy config start\n");
ddr_cfg_phy(dram_timing);
debug("DDRINFO: ddrphy config done\n");
/*
* step14 CalBusy.0 =1, indicates the calibrator is actively
* calibrating. Wait Calibrating done.
*/
do {
tmp = reg32_read(DDRPHY_CalBusy(0));
} while ((tmp & 0x1));
debug("DDRINFO:ddrphy calibration done\n");
/* step15 [0]--0: to enable quasi-dynamic programming */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* step16 */
tmp = reg32_read(DDRC_MSTR2(0));
if (tmp == 0x2)
reg32_write(DDRC_DFIMISC(0), 0x00000230);
else if (tmp == 0x1)
reg32_write(DDRC_DFIMISC(0), 0x00000130);
else
reg32_write(DDRC_DFIMISC(0), 0x00000030);
/* step17 [0]--1: disable quasi-dynamic programming */
reg32_write(DDRC_SWCTL(0), 0x00000001);
/* step18 wait DFISTAT.dfi_init_complete to 1 */
do {
tmp = reg32_read(DDRC_DFISTAT(0));
} while ((tmp & 0x1) == 0x0);
/* step19 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
/* step20~22 */
tmp = reg32_read(DDRC_MSTR2(0));
if (tmp == 0x2) {
reg32_write(DDRC_DFIMISC(0), 0x00000210);
/* set DFIMISC.dfi_init_complete_en again */
reg32_write(DDRC_DFIMISC(0), 0x00000211);
} else if (tmp == 0x1) {
reg32_write(DDRC_DFIMISC(0), 0x00000110);
/* set DFIMISC.dfi_init_complete_en again */
reg32_write(DDRC_DFIMISC(0), 0x00000111);
} else {
/* clear DFIMISC.dfi_init_complete_en */
reg32_write(DDRC_DFIMISC(0), 0x00000010);
/* set DFIMISC.dfi_init_complete_en again */
reg32_write(DDRC_DFIMISC(0), 0x00000011);
}
/* step23 [5]selfref_sw=0; */
reg32_write(DDRC_PWRCTL(0), 0x00000008);
/* step24 sw_done=1 */
reg32_write(DDRC_SWCTL(0), 0x00000001);
/* step25 wait SWSTAT.sw_done_ack to 1 */
do {
tmp = reg32_read(DDRC_SWSTAT(0));
} while ((tmp & 0x1) == 0x0);
#ifdef DFI_BUG_WR
reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
#endif
/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
do {
tmp = reg32_read(DDRC_STAT(0));
} while ((tmp & 0x3) != 0x1);
/* step26 */
reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
debug("DDRINFO: ddrmix config done\n");
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
}

18
drivers/gpio/mxc_gpio.c
View File

@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = {
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
defined(CONFIG_ARCH_IMX8)
[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
defined(CONFIG_ARCH_IMX8)
[4] = GPIO5_BASE_ADDR,
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
[5] = GPIO6_BASE_ADDR,
#endif
#endif
@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
#ifndef CONFIG_MX8M
#ifndef CONFIG_IMX8M
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
#endif
@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = {
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[3] },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[4] },
#ifndef CONFIG_MX8M
#ifndef CONFIG_IMX8M
{ "gpio_mxc", &mxc_plat[5] },
#endif
#endif

6
drivers/misc/mxc_ocotp.c
View File

@ -34,7 +34,7 @@
#define BM_OUT_STATUS_DED 0x00000400
#define BM_OUT_STATUS_LOCKED 0x00000800
#define BM_OUT_STATUS_PROGFAIL 0x00001000
#elif defined(CONFIG_MX8M)
#elif defined(CONFIG_IMX8M)
#define BM_CTRL_ADDR 0x000000ff
#else
#define BM_CTRL_ADDR 0x0000007f
@ -80,7 +80,7 @@
#elif defined(CONFIG_MX7ULP)
#define FUSE_BANK_SIZE 0x80
#define FUSE_BANKS 31
#elif defined(CONFIG_MX8M)
#elif defined(CONFIG_IMX8M)
#define FUSE_BANK_SIZE 0x40
#define FUSE_BANKS 64
#else
@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
#ifdef CONFIG_MX7
u32 addr = bank;
#elif defined CONFIG_MX8M
#elif defined CONFIG_IMX8M
u32 addr = bank << 2 | word;
#else
u32 addr;

8
drivers/mmc/fsl_esdhc.c
View File

@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
int timeout;
struct fsl_esdhc *regs = priv->esdhc_regs;
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
#endif
uint wml_value;
@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));

11
drivers/mtd/nand/raw/Kconfig
View File

@ -88,6 +88,15 @@ config NAND_VF610_NFC
The driver supports a maximum 2k page size. The driver
currently does not support hardware ECC.
if NAND_VF610_NFC
config NAND_VF610_NFC_DT
bool "Support Vybrid's vf610 NAND controller as a DT device"
depends on OF_CONTROL && MTD
help
Enable the driver for Vybrid's vf610 NAND flash on platforms
using device tree.
choice
prompt "Hardware ECC strength"
depends on NAND_VF610_NFC
@ -103,6 +112,8 @@ config SYS_NAND_VF610_NFC_60_ECC_BYTES
endchoice
endif
config NAND_PXA3XX
bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
select SYS_NAND_SELF_INIT

49
drivers/mtd/nand/raw/vf610_nfc.c
View File

@ -31,6 +31,11 @@
#include <nand.h>
#include <errno.h>
#include <asm/io.h>
#if CONFIG_NAND_VF610_NFC_DT
#include <dm.h>
#include <linux/io.h>
#include <linux/ioport.h>
#endif
/* Register Offsets */
#define NFC_FLASH_CMD1 0x3F00
@ -641,7 +646,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
.flash_bbt = 1,
};
nfc = malloc(sizeof(*nfc));
nfc = calloc(1, sizeof(*nfc));
if (!nfc) {
printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
return -ENOMEM;
@ -760,9 +765,51 @@ error:
return err;
}
#if CONFIG_NAND_VF610_NFC_DT
static const struct udevice_id vf610_nfc_dt_ids[] = {
{
.compatible = "fsl,vf610-nfc",
},
{ /* sentinel */ }
};
static int vf610_nfc_dt_probe(struct udevice *dev)
{
struct resource res;
int ret;
ret = dev_read_resource(dev, 0, &res);
if (ret)
return ret;
return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start,
resource_size(&res)));
}
U_BOOT_DRIVER(vf610_nfc_dt) = {
.name = "vf610-nfc-dt",
.id = UCLASS_MTD,
.of_match = vf610_nfc_dt_ids,
.probe = vf610_nfc_dt_probe,
};
void board_nand_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MTD,
DM_GET_DRIVER(vf610_nfc_dt),
&dev);
if (ret && ret != -ENODEV)
pr_err("Failed to initialize NAND controller. (error %d)\n",
ret);
}
#else
void board_nand_init(void)
{
int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
if (err)
printf("VF610 NAND init failed (err %d)\n", err);
}
#endif /* CONFIG_NAND_VF610_NFC_DT */

2
drivers/net/fec_mxc.c
View File

@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register */
if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);

14
drivers/pinctrl/nxp/Kconfig
View File

@ -74,3 +74,17 @@ config PINCTRL_IMX8
is different from the linux one, this is a simple implementation,
only parses the 'fsl,pins' property and configures related
registers.
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
select DEVRES
select PINCTRL_IMX
help
Say Y here to enable the Vybrid (vf610) pinctrl driver
This provides a simple pinctrl driver for Vybrid SoC familiy,
vf610. This feature depends on device tree
configuration. This driver is different from the linux one,
this is a simple implementation, only parses the 'fsl,pins'
property and configure related registers.

1
drivers/pinctrl/nxp/Makefile
View File

@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o

40
drivers/pinctrl/nxp/pinctrl-vf610.c Normal file
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 DENX Software Engineering
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include "pinctrl-imx.h"
static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = {
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
};
static int vf610_pinctrl_probe(struct udevice *dev)
{
struct imx_pinctrl_soc_info *info =
(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
return imx_pinctrl_probe(dev, info);
}
static const struct udevice_id vf610_pinctrl_match[] = {
{ .compatible = "fsl,vf610-iomuxc",
.data = (ulong)&vf610_pinctrl_soc_info },
{ /* sentinel */ }
};
U_BOOT_DRIVER(vf610_pinctrl) = {
.name = "vf610-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(vf610_pinctrl_match),
.probe = vf610_pinctrl_probe,
.remove = imx_pinctrl_remove,
.priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};

14
drivers/w1/Kconfig
View File

@ -20,6 +20,20 @@ config W1_GPIO
help
Emulate a 1-wire bus using a GPIO.
config W1_MXC
bool "Enable 1-wire controller on i.MX processors"
default no
depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
help
Support the one wire controller found in some members of the NXP
i.MX SoC family.
There are currently two silicon variants:
V1: i.MX21, i.MX27, i.MX31, i.MX51
V2: i.MX25, i.MX35, i.MX50, i.MX53
Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
The driver supports both silicon variants.
endif
endmenu

1
drivers/w1/Makefile
View File

@ -1,3 +1,4 @@
obj-$(CONFIG_W1) += w1-uclass.o
obj-$(CONFIG_W1_GPIO) += w1-gpio.o
obj-$(CONFIG_W1_MXC) += mxc_w1.o

232
drivers/w1/mxc_w1.c Normal file
View File

@ -0,0 +1,232 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for one wire controller in some i.MX Socs
*
* There are currently two silicon variants:
* V1: i.MX21, i.MX27, i.MX31, i.MX51
* V2: i.MX25, i.MX35, i.MX50, i.MX53
* Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
*
* The V1 controller only supports single bit operations.
* The V2 controller is backwards compatible on the register level but adds
* byte size operations and a "search ROM accelerator mode"
*
* This driver does not currently support the search ROM accelerator
*
* Copyright (c) 2018 Flowbird
* Martin Fuzzey <martin.fuzzey@flowbird.group>
*/
#include <asm/arch/clock.h>
#include <common.h>
#include <dm.h>
#include <linux/io.h>
#include <w1.h>
struct mxc_w1_regs {
u16 control;
#define MXC_W1_CONTROL_RPP BIT(7)
#define MXC_W1_CONTROL_PST BIT(6)
#define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
#define MXC_W1_CONTROL_RDST BIT(3)
u16 time_divider;
u16 reset;
/* Registers below on V2 silicon only */
u16 command;
u16 tx_rx;
u16 interrupt;
#define MXC_W1_INTERRUPT_TBE BIT(2)
#define MXC_W1_INTERRUPT_TSRE BIT(3)
#define MXC_W1_INTERRUPT_RBF BIT(4)
#define MXC_W1_INTERRUPT_RSRF BIT(5)
u16 interrupt_en;
};
struct mxc_w1_pdata {
struct mxc_w1_regs *regs;
};
/*
* this is the low level routine to read/write a bit on the One Wire
* interface on the hardware. It does write 0 if parameter bit is set
* to 0, otherwise a write 1/read.
*/
static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
{
u16 *ctrl_addr = &pdata->regs->control;
u16 mask = MXC_W1_CONTROL_WR(bit);
unsigned int timeout_cnt = 400; /* Takes max. 120us according to
* datasheet.
*/
writew(mask, ctrl_addr);
while (timeout_cnt--) {
if (!(readw(ctrl_addr) & mask))
break;
udelay(1);
}
return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
}
static u8 mxc_w1_read_byte(struct udevice *dev)
{
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
struct mxc_w1_regs *regs = pdata->regs;
u16 status;
if (dev_get_driver_data(dev) < 2) {
int i;
u8 ret = 0;
for (i = 0; i < 8; i++)
ret |= (mxc_w1_touch_bit(pdata, 1) << i);
return ret;
}
readw(&regs->tx_rx);
writew(0xFF, &regs->tx_rx);
do {
udelay(1); /* Without this bytes are sometimes duplicated... */
status = readw(&regs->interrupt);
} while (!(status & MXC_W1_INTERRUPT_RBF));
return (u8)readw(&regs->tx_rx);
}
static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
{
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
struct mxc_w1_regs *regs = pdata->regs;
u16 status;
if (dev_get_driver_data(dev) < 2) {
int i;
for (i = 0; i < 8; i++)
mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
return;
}
readw(&regs->tx_rx);
writew(byte, &regs->tx_rx);
do {
udelay(1);
status = readw(&regs->interrupt);
} while (!(status & MXC_W1_INTERRUPT_TSRE));
}
static bool mxc_w1_reset(struct udevice *dev)
{
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
u16 reg_val;
writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
do {
reg_val = readw(&pdata->regs->control);
} while (reg_val & MXC_W1_CONTROL_RPP);
return !(reg_val & MXC_W1_CONTROL_PST);
}
static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
{
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
u8 id_bit = mxc_w1_touch_bit(pdata, 1);
u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
u8 retval;
if (id_bit && comp_bit)
return 0x03; /* error */
if (!id_bit && !comp_bit) {
/* Both bits are valid, take the direction given */
retval = bdir ? 0x04 : 0;
} else {
/* Only one bit is valid, take that direction */
bdir = id_bit;
retval = id_bit ? 0x05 : 0x02;
}
mxc_w1_touch_bit(pdata, bdir);
return retval;
}
static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
{
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
fdt_addr_t addr;
addr = devfdt_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
pdata->regs = (struct mxc_w1_regs *)addr;
return 0;
};
static int mxc_w1_probe(struct udevice *dev)
{
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
unsigned int clkdiv;
if (clkrate < 10000000) {
dev_err(dev, "input clock frequency (%u Hz) too low\n",
clkrate);
return -EINVAL;
}
clkdiv = clkrate / 1000000;
clkrate /= clkdiv;
if (clkrate < 980000 || clkrate > 1020000) {
dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
return -EINVAL;
}
writew(clkdiv - 1, &pdata->regs->time_divider);
return 0;
}
static const struct w1_ops mxc_w1_ops = {
.read_byte = mxc_w1_read_byte,
.reset = mxc_w1_reset,
.triplet = mxc_w1_triplet,
.write_byte = mxc_w1_write_byte,
};
static const struct udevice_id mxc_w1_id[] = {
{ .compatible = "fsl,imx21-owire", .data = 1 },
{ .compatible = "fsl,imx27-owire", .data = 1 },
{ .compatible = "fsl,imx31-owire", .data = 1 },
{ .compatible = "fsl,imx51-owire", .data = 1 },
{ .compatible = "fsl,imx25-owire", .data = 2 },
{ .compatible = "fsl,imx35-owire", .data = 2 },
{ .compatible = "fsl,imx50-owire", .data = 2 },
{ .compatible = "fsl,imx53-owire", .data = 2 },
{ },
};
U_BOOT_DRIVER(mxc_w1_drv) = {
.id = UCLASS_W1,
.name = "mxc_w1_drv",
.of_match = mxc_w1_id,
.ofdata_to_platdata = mxc_w1_ofdata_to_platdata,
.ops = &mxc_w1_ops,
.platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata),
.probe = mxc_w1_probe,
};

6
drivers/watchdog/Kconfig
View File

@ -11,6 +11,12 @@ config WATCHDOG
config HW_WATCHDOG
bool
config WATCHDOG_RESET_DISABLE
bool "Disable reset watchdog"
help
Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
that the watchdog will not be fed in u-boot.
config BCM2835_WDT
bool "Enable BCM2835/2836 watchdog driver"
select HW_WATCHDOG

2
drivers/watchdog/Makefile
View File

@ -7,6 +7,8 @@ obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
obj-y += imx_watchdog.o
else
obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o
endif
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o

9
drivers/watchdog/imx_watchdog.c
View File

@ -8,15 +8,20 @@
#include <asm/io.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_FSL_LSCH2
#include <asm/arch/immap_lsch2.h>
#endif
#include <fsl_wdog.h>
#ifdef CONFIG_IMX_WATCHDOG
void hw_watchdog_reset(void)
{
#ifndef CONFIG_WATCHDOG_RESET_DISABLE
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
writew(0x5555, &wdog->wsr);
writew(0xaaaa, &wdog->wsr);
#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
}
void hw_watchdog_init(void)
@ -33,8 +38,12 @@ void hw_watchdog_init(void)
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
#endif
timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
#ifdef CONFIG_FSL_LSCH2
writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
#else
writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
#endif /* CONFIG_FSL_LSCH2*/
hw_watchdog_reset();
}
#endif

13
include/configs/embestmx6boards.h
View File

@ -109,6 +109,19 @@
#include "mx6_common.h"
#ifdef CONFIG_SPL
#include "imx6_spl.h"
/* RiOTboard */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb"
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */
#endif
/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end */
#define MEM_LAYOUT_ENV_SETTINGS \

252
include/configs/imx8mq_evk.h Normal file
View File

@ -0,0 +1,252 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __IMX8M_EVK_H
#define __IMX8M_EVK_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
#endif
#define CONFIG_SPL_TEXT_BASE 0x7E1000
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x187FF0
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_BSS_START_ADDR 0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
#undef CONFIG_DM_PMIC
#undef CONFIG_DM_PMIC_PFUZE100
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#endif
#define CONFIG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
"rdinit=/linuxrc " \
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
"g_mass_storage.iSerialNumber=\"\" "\
"clk_ignore_unused "\
"\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffff\0" \
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image\0" \
"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8mq-evk.dtb\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"echo wait for boot; " \
"fi;\0" \
"netargs=setenv bootargs console=${console} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"booti; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
#define CONFIG_LOADADDR 0x40480000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(PHYS_SDRAM_SIZE >> 1))
#define CONFIG_BAUDRATE 115200
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "u-boot=> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_IMX_BOOTAUX
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE
/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_OF_SYSTEM_SETUP
#ifndef CONFIG_SPL_BUILD
#define CONFIG_DM_PMIC
#endif
#endif

1
include/configs/pcm058.h
View File

@ -55,6 +55,7 @@
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#endif
/* DMA stuff, needed for GPMI/MXS NAND support */

14
include/configs/pico-imx7d.h
View File

@ -134,7 +134,19 @@
/* FLASH and environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
/* Environment starts at 768k = 768 * 1024 = 786432 */
#define CONFIG_ENV_OFFSET 786432
/*
* Detect overlap between U-Boot image and environment area in build-time
*
* CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
* CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
*
* Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
* write the direct value here
*/
#define CONFIG_BOARD_SIZE_LIMIT 715776
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_MMC_ENV_DEV 0

17
include/imximage.h
View File

@ -33,6 +33,7 @@
#define FLASH_OFFSET_NOR 0x1000
#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_QSPI 0x1000
#define FLASH_OFFSET_FLEXSPI 0x1000
/* Initial Load Region Size */
#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
@ -48,6 +49,7 @@
/* Command tags and parameters */
#define IVT_HEADER_TAG 0xD1
#define IVT_VERSION 0x40
#define IVT_VERSION_V3 0x41
#define DCD_HEADER_TAG 0xD2
#define DCD_VERSION 0x40
#define DCD_WRITE_DATA_COMMAND_TAG 0xCC
@ -71,6 +73,12 @@ enum imximage_cmd {
CMD_CHECK_BITS_CLR,
CMD_CSF,
CMD_PLUGIN,
/* Follwoing on i.MX8MQ/MM */
CMD_FIT,
CMD_SIGNED_HDMI,
CMD_LOADER,
CMD_SECOND_LOADER,
CMD_DDR_FW,
};
enum imximage_fld_types {
@ -84,7 +92,8 @@ enum imximage_fld_types {
enum imximage_version {
IMXIMAGE_VER_INVALID = -1,
IMXIMAGE_V1 = 1,
IMXIMAGE_V2
IMXIMAGE_V2,
IMXIMAGE_V3
};
typedef struct {
@ -177,6 +186,12 @@ typedef struct {
} data;
} imx_header_v2_t;
typedef struct {
flash_header_v2_t fhdr;
boot_data_t boot_data;
uint32_t padding[5];
} imx_header_v3_t;
/* The header must be aligned to 4k on MX53 for NAND boot */
struct imx_header {
union {

13
include/spl.h
View File

@ -118,6 +118,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fdt);
#define SPL_COPY_PAYLOAD_ONLY 1
#define SPL_FIT_FOUND 2
/* SPL common functions */
void preloader_console_init(void);
@ -352,6 +353,18 @@ void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
*/
void board_return_to_bootrom(void);
/**
* board_spl_fit_post_load - allow process images after loading finished
*
*/
void board_spl_fit_post_load(ulong load_addr, size_t length);
/**
* board_spl_fit_size_align - specific size align before processing payload
*
*/
ulong board_spl_fit_size_align(ulong size);
/**
* spl_perform_fixups() - arch/board-specific callback before processing
* the boot-payload

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