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armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Priyanka Jain
Prabhakar Kushwaha
parent
2e53759dc6
commit
58c3e62040
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@ -1083,6 +1083,19 @@ config TARGET_LS2081ARDB
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development platform that supports the QorIQ LS2081A/LS2041A
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Layerscape Architecture processor.
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config TARGET_LX2160ARDB
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bool "Support lx2160ardb"
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select ARCH_LX2160A
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select ARCH_MISC_INIT
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select ARM64
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select ARMV8_MULTIENTRY
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select BOARD_LATE_INIT
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help
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Support for NXP LX2160ARDB platform.
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The lx2160ardb (LX2160A Reference design board (RDB)
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is a high-performance development platform that supports the
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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config TARGET_HIKEY
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bool "Support HiKey 96boards Consumer Edition Platform"
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select ARM64
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@ -1555,6 +1568,7 @@ source "board/freescale/ls1046ardb/Kconfig"
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source "board/freescale/ls1012aqds/Kconfig"
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source "board/freescale/ls1012ardb/Kconfig"
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source "board/freescale/ls1012afrdm/Kconfig"
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source "board/freescale/lx2160a/Kconfig"
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source "board/freescale/mx35pdk/Kconfig"
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source "board/freescale/s32v234evb/Kconfig"
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source "board/grinn/chiliboard/Kconfig"
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@ -106,7 +106,7 @@ config PSCI_RESET
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!TARGET_LS1012AFRWY && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS2081ARDB && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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help
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Most armv8 systems have PSCI support enabled in EL3, either through
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@ -246,7 +246,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls2081a-rdb.dtb \
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fsl-ls2088a-rdb-qspi.dtb \
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fsl-ls1088a-rdb.dtb \
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fsl-ls1088a-qds.dtb
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fsl-ls1088a-qds.dtb \
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fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1043a-qds-lpuart.dtb \
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fsl-ls1043a-rdb.dtb \
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44
arch/arm/dts/fsl-lx2160a-rdb.dts
Normal file
44
arch/arm/dts/fsl-lx2160a-rdb.dts
Normal file
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160ARDB device tree source
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*
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* Author: Priyanka Jain <priyanka.jain@nxp.com>
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* Sriram Dash <sriram.dash@nxp.com>
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*
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* Copyright 2018 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160ARDB Board";
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compatible = "fsl,lx2160ardb", "fsl,lx2160a";
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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};
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&sata0 {
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status = "okay";
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};
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&sata1 {
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status = "okay";
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};
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&sata2 {
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status = "okay";
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};
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&sata3 {
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status = "okay";
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};
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@ -89,7 +89,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <0 240 0x4>; /* Level high type */
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interrupts = <0 26 0x4>; /* Level high type */
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num-cs = <6>;
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};
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@ -115,4 +115,65 @@
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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};
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esdhc0: esdhc@2140000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>; /* Level high type */
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clocks = <&clockgen 4 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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little-endian;
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bus-width = <4>;
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status = "disabled";
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};
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esdhc1: esdhc@2150000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2150000 0x0 0x10000>;
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interrupts = <0 63 0x4>; /* Level high type */
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clocks = <&clockgen 4 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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non-removable;
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little-endian;
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bus-width = <4>;
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status = "disabled";
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};
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sata0: sata@3200000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>;
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interrupts = <0 133 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata1: sata@3210000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3210000 0x0 0x10000>;
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interrupts = <0 136 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata2: sata@3220000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3220000 0x0 0x10000>;
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interrupts = <0 97 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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sata3: sata@3230000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3230000 0x0 0x10000>;
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interrupts = <0 100 4>;
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clocks = <&clockgen 4 3>;
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status = "disabled";
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};
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};
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@ -227,8 +227,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
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#ifdef QIXIS_LBMAP_SD
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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#ifdef NON_EXTENDED_DUTCFG
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QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
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#else
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set_lbmap(QIXIS_LBMAP_SD);
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set_rcw_src(QIXIS_RCW_SRC_SD);
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#endif
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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#else
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16
board/freescale/lx2160a/Kconfig
Normal file
16
board/freescale/lx2160a/Kconfig
Normal file
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@ -0,0 +1,16 @@
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if TARGET_LX2160ARDB
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config SYS_BOARD
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default "lx2160a"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "lx2160ardb"
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source "board/freescale/common/Kconfig"
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endif
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8
board/freescale/lx2160a/MAINTAINERS
Normal file
8
board/freescale/lx2160a/MAINTAINERS
Normal file
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@ -0,0 +1,8 @@
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LX2160ARDB BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/lx2160a/
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F: include/configs/lx2160a_common.h
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F: include/configs/lx2160ardb.h
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F: configs/lx2160ardb_tfa_defconfig
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F: arch/arm/dts/fsl-lx2160a-rdb.dts
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9
board/freescale/lx2160a/Makefile
Normal file
9
board/freescale/lx2160a/Makefile
Normal file
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@ -0,0 +1,9 @@
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#
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# Copyright 2018 Freescale Semiconductor
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += lx2160a.o
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obj-y += ddr.o
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obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
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79
board/freescale/lx2160a/README
Normal file
79
board/freescale/lx2160a/README
Normal file
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@ -0,0 +1,79 @@
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Overview
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--------
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The LX2160A Reference Design (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LX2160A
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Layerscape Architecture processor and its personalities.
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LX2160A SoC Overview
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--------------------------------------
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For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
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LX2160ARDB board Overview
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----------------------
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DDR Memory
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Two ports of 72-bits (8-bits ECC) DDR4.
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Each port supports four chip-selects and two DIMM
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connectors. Data rate upto 3.2 GT/s.
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SERDES ports
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Thress serdes controllers (24 lanes)
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Serdes1: Supports two USXGMII connectors, each connected through
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Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
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IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
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CS4223 phy.
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Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0
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connectors
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Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector
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eSDHC
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eSDHC1: Supports a SD connector for connecting SD cards
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eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
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Octal SPI (XSPI)
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Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
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for off-board emulation
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I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer
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Serial Ports
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USB 3.0
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Two high speed USB 3.0 ports. First USB 3.0 port configured as
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Host with Type-A connector, second USB 3.0 port configured as OTG
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with micro-AB connector
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Serial Ports Two UART ports
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Ethernet Two RGMII interfaces
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Debug ARM JTAG support
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Booting Options
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---------------
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a) Flexspi boot
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b) SD boot
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Memory map for Flexspi flash
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----------------------------
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Image Flash Offset
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bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000
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fip.bin (bl31 + bl33(u-boot) +
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header for Secure-boot(secure-boot only)) 0x00100000
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Boot firmware Environment 0x00500000
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DDR PHY Firmware (fip_ddr_all.bin) 0x00800000
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DPAA2 MC Firmware 0x00A00000
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DPAA2 DPL 0x00D00000
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DPAA2 DPC 0x00E00000
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Kernel.itb 0x01000000
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Memory map for sd card
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----------------------------
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Image SD card Offset
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bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008
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fip.bin (bl31 + bl33(u-boot) +
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header for Secure-boot(secure-boot only)) 0x00800
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Boot firmware Environment 0x02800
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DDR PHY Firmware (fip_ddr_all.bin) 0x04000
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DPAA2 MC Firmware 0x05000
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DPAA2 DPL 0x06800
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DPAA2 DPC 0x07000
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Kernel.itb 0x08000
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20
board/freescale/lx2160a/ddr.c
Normal file
20
board/freescale/lx2160a/ddr.c
Normal file
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@ -0,0 +1,20 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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DECLARE_GLOBAL_DATA_PTR;
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int fsl_initdram(void)
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{
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size)
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gd->ram_size = fsl_ddr_sdram_size();
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return 0;
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}
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210
board/freescale/lx2160a/eth_lx2160ardb.c
Normal file
210
board/freescale/lx2160a/eth_lx2160ardb.c
Normal file
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@ -0,0 +1,210 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <exports.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/ldpaa_wriop.h>
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DECLARE_GLOBAL_DATA_PTR;
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static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
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{
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int phy_reg;
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u32 phy_id;
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phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
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phy_id = (phy_reg & 0xffff) << 16;
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phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
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phy_id |= (phy_reg & 0xffff);
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if (phy_id == PHY_UID_IN112525_S03)
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return true;
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else
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return false;
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FSL_MC_ENET)
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struct memac_mdio_info mdio_info;
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struct memac_mdio_controller *reg;
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int i, interface;
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struct mii_dev *dev;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 srds_s1;
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srds_s1 = in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
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/* Register the EMI 1 */
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fm_memac_mdio_init(bis, &mdio_info);
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
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/* Register the EMI 2 */
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fm_memac_mdio_init(bis, &mdio_info);
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
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switch (srds_s1) {
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case 19:
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wriop_set_phy_address(WRIOP1_DPMAC2, 0,
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CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC3, 0,
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AQR107_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC4, 0,
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AQR107_PHY_ADDR2);
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if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
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wriop_set_phy_address(WRIOP1_DPMAC5, 0,
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INPHI_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC6, 0,
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INPHI_PHY_ADDR1);
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}
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wriop_set_phy_address(WRIOP1_DPMAC17, 0,
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RGMII_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC18, 0,
|
||||
RGMII_PHY_ADDR2);
|
||||
break;
|
||||
|
||||
case 18:
|
||||
wriop_set_phy_address(WRIOP1_DPMAC7, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC8, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC9, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC10, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
|
||||
AQR107_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
|
||||
AQR107_PHY_ADDR2);
|
||||
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
|
||||
INPHI_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
|
||||
INPHI_PHY_ADDR1);
|
||||
}
|
||||
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
|
||||
RGMII_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
|
||||
RGMII_PHY_ADDR2);
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
|
||||
srds_s1);
|
||||
goto next;
|
||||
}
|
||||
|
||||
for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
|
||||
interface = wriop_get_enet_if(i);
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_25G_AUI:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_XLAUI:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
|
||||
interface = wriop_get_enet_if(i);
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
next:
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FSL_MC_ENET */
|
||||
|
||||
#ifdef CONFIG_PHY_AQUANTIA
|
||||
/*
|
||||
* Export functions to be used by AQ firmware
|
||||
* upload application
|
||||
*/
|
||||
gd->jt->strcpy = strcpy;
|
||||
gd->jt->mdelay = mdelay;
|
||||
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
|
||||
gd->jt->phy_find_by_mask = phy_find_by_mask;
|
||||
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
|
||||
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
|
||||
#endif
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
mc_env_boot();
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
|
||||
int fdt_fixup_board_phy(void *fdt)
|
||||
{
|
||||
int mdio_offset;
|
||||
int ret;
|
||||
struct mii_dev *dev;
|
||||
|
||||
ret = 0;
|
||||
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
|
||||
mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
|
||||
|
||||
if (mdio_offset < 0)
|
||||
mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
|
||||
|
||||
if (mdio_offset < 0) {
|
||||
printf("mdio@0x8B9700 node not found in dts\n");
|
||||
return mdio_offset;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_string(fdt, mdio_offset, "status",
|
||||
"disabled");
|
||||
if (ret) {
|
||||
printf("Could not set disable mdio@0x8B97000 %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
279
board/freescale/lx2160a/lx2160a.c
Normal file
279
board/freescale/lx2160a/lx2160a.c
Normal file
|
|
@ -0,0 +1,279 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/platform_data/serial_pl01x.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_ddr.h>
|
||||
#include <fsl_sec.h>
|
||||
#include <asm/io.h>
|
||||
#include <fdt_support.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <environment.h>
|
||||
#include <efi_loader.h>
|
||||
#include <asm/arch/mmu.h>
|
||||
#include <hwconfig.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include "../common/qixis.h"
|
||||
#include "../common/vid.h"
|
||||
#include <fsl_immap.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct pl01x_serial_platdata serial0 = {
|
||||
#if CONFIG_CONS_INDEX == 0
|
||||
.base = CONFIG_SYS_SERIAL0,
|
||||
#elif CONFIG_CONS_INDEX == 1
|
||||
.base = CONFIG_SYS_SERIAL1,
|
||||
#else
|
||||
#error "Unsupported console index value."
|
||||
#endif
|
||||
.type = TYPE_PL011,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(nxp_serial0) = {
|
||||
.name = "serial_pl01x",
|
||||
.platdata = &serial0,
|
||||
};
|
||||
|
||||
static struct pl01x_serial_platdata serial1 = {
|
||||
.base = CONFIG_SYS_SERIAL1,
|
||||
.type = TYPE_PL011,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(nxp_serial1) = {
|
||||
.name = "serial_pl01x",
|
||||
.platdata = &serial1,
|
||||
};
|
||||
|
||||
int select_i2c_ch_pca9547(u8 ch)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
|
||||
if (ret) {
|
||||
puts("PCA: failed to select proper channel\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uart_get_clock(void)
|
||||
{
|
||||
serial0.clock = get_serial_clock();
|
||||
serial1.clock = get_serial_clock();
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_I2C_EARLY_INIT
|
||||
i2c_early_init_f();
|
||||
#endif
|
||||
/* get required clock for UART IP */
|
||||
uart_get_clock();
|
||||
|
||||
fsl_lsch3_early_init_f();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int esdhc_status_fixup(void *blob, const char *compat)
|
||||
{
|
||||
/* Enable both esdhc DT nodes for LX2160ARDB */
|
||||
do_fixup_by_compat(blob, compat, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_VID)
|
||||
int i2c_multiplexer_select_vid_channel(u8 channel)
|
||||
{
|
||||
return select_i2c_ch_pca9547(channel);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
enum boot_src src = get_boot_src();
|
||||
char buf[64];
|
||||
u8 sw;
|
||||
|
||||
cpu_name(buf);
|
||||
printf("Board: %s-RDB, ", buf);
|
||||
|
||||
sw = QIXIS_READ(arch);
|
||||
printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
|
||||
|
||||
if (src == BOOT_SOURCE_SD_MMC) {
|
||||
puts("SD\n");
|
||||
} else {
|
||||
sw = QIXIS_READ(brdcfg[0]);
|
||||
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
|
||||
switch (sw) {
|
||||
case 0:
|
||||
case 4:
|
||||
puts("FlexSPI DEV#0\n");
|
||||
break;
|
||||
case 1:
|
||||
puts("FlexSPI DEV#1\n");
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
puts("FlexSPI EMU\n");
|
||||
break;
|
||||
default:
|
||||
printf("invalid setting, xmap: %d\n", sw);
|
||||
break;
|
||||
}
|
||||
}
|
||||
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
||||
|
||||
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
|
||||
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
return 100000000;
|
||||
}
|
||||
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
return 100000000;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE
|
||||
gd->env_addr = (ulong)&default_environment[0];
|
||||
#endif
|
||||
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
int i;
|
||||
u64 ddr_size = 0;
|
||||
|
||||
puts("\nDDR ");
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||
ddr_size += gd->bd->bi_dram[i].size;
|
||||
print_size(ddr_size, "");
|
||||
print_ddr_info(0);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_MISC_INIT)
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
extern int fdt_fixup_board_phy(void *fdt);
|
||||
|
||||
void fdt_fixup_board_enet(void *fdt)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = fdt_path_offset(fdt, "/soc/fsl-mc");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/fsl-mc");
|
||||
|
||||
if (offset < 0) {
|
||||
printf("%s: fsl-mc node not found in device tree (error %d)\n",
|
||||
__func__, offset);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
|
||||
fdt_status_okay(fdt, offset);
|
||||
fdt_fixup_board_phy(fdt);
|
||||
} else {
|
||||
fdt_status_fail(fdt, offset);
|
||||
}
|
||||
}
|
||||
|
||||
void board_quiesce_devices(void)
|
||||
{
|
||||
fsl_mc_ldpaa_exit(gd->bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int i;
|
||||
u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* fixup DT for the three GPP DDR banks */
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||
base[i] = gd->bd->bi_dram[i].start;
|
||||
size[i] = gd->bd->bi_dram[i].size;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESV_RAM
|
||||
/* reduce size if reserved memory is within this bank */
|
||||
if (gd->arch.resv_ram >= base[0] &&
|
||||
gd->arch.resv_ram < base[0] + size[0])
|
||||
size[0] = gd->arch.resv_ram - base[0];
|
||||
else if (gd->arch.resv_ram >= base[1] &&
|
||||
gd->arch.resv_ram < base[1] + size[1])
|
||||
size[1] = gd->arch.resv_ram - base[1];
|
||||
else if (gd->arch.resv_ram >= base[2] &&
|
||||
gd->arch.resv_ram < base[2] + size[2])
|
||||
size[2] = gd->arch.resv_ram - base[2];
|
||||
#endif
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
fdt_fsl_mc_fixup_iommu_map_entry(blob);
|
||||
fdt_fixup_board_enet(blob);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void qixis_dump_switch(void)
|
||||
{
|
||||
int i, nr_of_cfgsw;
|
||||
|
||||
QIXIS_WRITE(cms[0], 0x00);
|
||||
nr_of_cfgsw = QIXIS_READ(cms[1]);
|
||||
|
||||
puts("DIP switch settings dump:\n");
|
||||
for (i = 1; i <= nr_of_cfgsw; i++) {
|
||||
QIXIS_WRITE(cms[0], i);
|
||||
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
|
||||
}
|
||||
}
|
||||
51
configs/lx2160ardb_tfa_defconfig
Normal file
51
configs/lx2160ardb_tfa_defconfig
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160ARDB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
214
include/configs/lx2160a_common.h
Normal file
214
include/configs/lx2160a_common.h
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_COMMON_H
|
||||
#define __LX2_COMMON_H
|
||||
|
||||
#include <asm/arch/stream_id_lsch3.h>
|
||||
#include <asm/arch/config.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_FSL_TZPC_BP147
|
||||
#define CONFIG_FSL_MEMAC
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
|
||||
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
||||
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
|
||||
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
|
||||
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#define SPD_EEPROM_ADDRESS1 0x51
|
||||
#define SPD_EEPROM_ADDRESS2 0x52
|
||||
#define SPD_EEPROM_ADDRESS3 0x53
|
||||
#define SPD_EEPROM_ADDRESS4 0x54
|
||||
#define SPD_EEPROM_ADDRESS5 0x55
|
||||
#define SPD_EEPROM_ADDRESS6 0x56
|
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
||||
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
|
||||
#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
|
||||
|
||||
/* SMP Definitinos */
|
||||
#define CPU_RELEASE_ADDR secondary_boot_func
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
/*
|
||||
* This is not an accurate number. It is used in start.S. The frequency
|
||||
* will be udpated later when get_bus_freq(0) is available.
|
||||
*/
|
||||
|
||||
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_PL01X_SERIAL
|
||||
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
|
||||
#define CONFIG_SYS_SERIAL0 0x21c0000
|
||||
#define CONFIG_SYS_SERIAL1 0x21d0000
|
||||
#define CONFIG_SYS_SERIAL2 0x21e0000
|
||||
#define CONFIG_SYS_SERIAL3 0x21f0000
|
||||
/*below might needs to be removed*/
|
||||
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
|
||||
(void *)CONFIG_SYS_SERIAL1, \
|
||||
(void *)CONFIG_SYS_SERIAL2, \
|
||||
(void *)CONFIG_SYS_SERIAL3 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/* MC firmware */
|
||||
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
|
||||
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
|
||||
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
|
||||
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
|
||||
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
|
||||
|
||||
/* Define phy_reset function to boot the MC based on mcinitcmd.
|
||||
* This happens late enough to properly fixup u-boot env MAC addresses.
|
||||
*/
|
||||
#define CONFIG_RESET_PHY_R
|
||||
|
||||
/*
|
||||
* Carve out a DDR region which will not be used by u-boot/Linux
|
||||
*
|
||||
* It will be used by MC and Debug Server. The MC region must be
|
||||
* 512MB aligned, so the min size to hide is 512MB.
|
||||
*/
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
|
||||
/* RTC */
|
||||
#define RTC
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* Qixis */
|
||||
#define CONFIG_FSL_QIXIS
|
||||
#define CONFIG_QIXIS_I2C_ACCESS
|
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
|
||||
/* PCI */
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_SYS_PCI_64BIT
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
|
||||
#ifdef CONFIG_SCSI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
|
||||
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_USB
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
/* FlexSPI */
|
||||
#ifdef CONFIG_NXP_FSPI
|
||||
#define NXP_FSPI_FLASH_SIZE SZ_64M
|
||||
#define NXP_FSPI_FLASH_NUM 1
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned long get_board_sys_clk(void);
|
||||
unsigned long get_board_ddr_clk(void);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
#define HWCONFIG_BUFFER_SIZE 128
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_OFFSET 0x500000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
CONFIG_ENV_OFFSET)
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_SYS_MAXARGS 64 /* max command args */
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
/* Initial environment variables */
|
||||
#define XSPI_NOR_BOOTCOMMAND "fsl_mc apply dpl 0x20d00000;" \
|
||||
"sf probe 0:0;" \
|
||||
"sf read 0xa0000000 0x1000000 0x3000000;" \
|
||||
"bootm 0xa0000000"
|
||||
|
||||
#define SD_BOOTCOMMAND "mmc read 0xa0000000 0x6800 0xA0;" \
|
||||
"fsl_mc apply dpl 0xa0000000;" \
|
||||
"mmc read 0xb0000000 0x8000 0x1d000;" \
|
||||
"bootm 0xb0000000"
|
||||
|
||||
#define XSPI_MC_INIT_CMD \
|
||||
"fsl_mc start mc 0x20a00000 0x20e00000\0"
|
||||
|
||||
#define SD_MC_INIT_CMD \
|
||||
"mmc read 0x80000000 0x5000 0x800;" \
|
||||
"mmc read 0x80100000 0x7000 0x800;" \
|
||||
"fsl_mc start mc 0x80000000 0x80100000\0"
|
||||
|
||||
#endif /* __LX2_COMMON_H */
|
||||
102
include/configs/lx2160ardb.h
Normal file
102
include/configs/lx2160ardb.h
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_RDB_H
|
||||
#define __LX2_RDB_H
|
||||
|
||||
#include "lx2160a_common.h"
|
||||
|
||||
/* Qixis */
|
||||
#define QIXIS_XMAP_MASK 0x07
|
||||
#define QIXIS_XMAP_SHIFT 5
|
||||
#define QIXIS_RST_CTL_RESET_EN 0x30
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x20
|
||||
#define QIXIS_LBMAP_QSPI 0x00
|
||||
#define QIXIS_RCW_SRC_QSPI 0xff
|
||||
#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
#define QIXIS_LBMAP_MASK 0x0f
|
||||
#define QIXIS_LBMAP_SD
|
||||
#define QIXIS_RCW_SRC_SD 0x08
|
||||
#define NON_EXTENDED_DUTCFG
|
||||
|
||||
/* VID */
|
||||
|
||||
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
||||
/* Voltage monitor on channel 2*/
|
||||
#define I2C_VOL_MONITOR_ADDR 0x63
|
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
||||
#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
|
||||
#define CONFIG_VID
|
||||
|
||||
/* The lowest and highest voltage allowed*/
|
||||
#define VDD_MV_MIN 775
|
||||
#define VDD_MV_MAX 855
|
||||
|
||||
/* PM Bus commands code for LTC3882*/
|
||||
#define PMBUS_CMD_PAGE 0x0
|
||||
#define PMBUS_CMD_READ_VOUT 0x8B
|
||||
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
||||
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
||||
#define PWM_CHANNEL0 0x0
|
||||
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 4
|
||||
|
||||
/* MAC/PHY configuration */
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
|
||||
|
||||
#define AQR107_PHY_ADDR1 0x04
|
||||
#define AQR107_PHY_ADDR2 0x05
|
||||
|
||||
#define CORTINA_NO_FW_UPLOAD
|
||||
#define CORTINA_PHY_ADDR1 0x0
|
||||
#define INPHI_PHY_ADDR1 0x0
|
||||
|
||||
#define RGMII_PHY_ADDR1 0x01
|
||||
#define RGMII_PHY_ADDR2 0x02
|
||||
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"scriptaddr=0x80800000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"pxefile_addr_r=0x81000000\0" \
|
||||
"fdt_addr_r=0x88000000\0" \
|
||||
"ramdisk_addr_r=0x89000000\0" \
|
||||
"loadaddr=0x80100000\0" \
|
||||
"kernel_addr=0x100000\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xa0000000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"kernel_start=0x21000000\0" \
|
||||
"lx2160ardb_vdd_mv=800\0" \
|
||||
"mcmemsize=0x40000000\0"
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LX2_RDB_H */
|
||||
Loading…
Reference in New Issue
Block a user