mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ARM: mvebu: add support for Allied Telesis x530
This is a range of stackable network switches. The SoC is Armada-385 and there are a number of variants with differing network port configurations. The DP variants are intended for a harsher operating environment so they use a different i2c mux and fit industrial-temp parts. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
Stefan Roese
parent
0e62072968
commit
0e31666dfa
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@ -109,7 +109,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-xp-maxbcm.dtb \
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armada-xp-synology-ds414.dtb \
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armada-xp-theadorable.dtb \
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armada-38x-controlcenterdc.dtb
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armada-38x-controlcenterdc.dtb \
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armada-385-atl-x530.dtb \
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armada-385-atl-x530DP.dtb
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dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
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uniphier-ld11-global.dtb \
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13
arch/arm/dts/armada-385-atl-x530-u-boot.dtsi
Normal file
13
arch/arm/dts/armada-385-atl-x530-u-boot.dtsi
Normal file
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@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0
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&spi1 {
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u-boot,dm-pre-reloc;
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spi-flash@0 {
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u-boot,dm-pre-reloc;
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};
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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50
arch/arm/dts/armada-385-atl-x530.dts
Normal file
50
arch/arm/dts/armada-385-atl-x530.dts
Normal file
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@ -0,0 +1,50 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "armada-385-atl-x530.dtsi"
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#include "armada-385-atl-x530-u-boot.dtsi"
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/ {
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model = "Allied Telesis x530";
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compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
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nand-protect {
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compatible = "atl,nand-protect";
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protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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usb-enable {
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compatible = "atl,usb-enable";
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enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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};
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boot-board {
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compatible = "atl,boot-board";
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present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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};
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phy-reset {
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compatible = "atl,phy-reset";
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reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
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<&gpio1 21 GPIO_ACTIVE_HIGH>;
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};
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led-enable {
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compatible = "atl,led-enable";
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enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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};
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led_7seg {
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compatible = "atl,of-led-7seg";
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segment-gpios = <
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&led_7seg_gpio 0 0
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&led_7seg_gpio 1 0
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&led_7seg_gpio 2 0
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&led_7seg_gpio 3 0
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&led_7seg_gpio 4 0
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&led_7seg_gpio 5 0
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&led_7seg_gpio 6 0
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&led_7seg_gpio 7 0>;
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};
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};
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266
arch/arm/dts/armada-385-atl-x530.dtsi
Normal file
266
arch/arm/dts/armada-385-atl-x530.dtsi
Normal file
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@ -0,0 +1,266 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-385.dtsi"
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/ {
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model = "Allied Telesis x530";
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compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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aliases {
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spi1 = &spi1;
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i2c0 = &i2c0;
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};
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memory {
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device_type = "memory";
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reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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pcie-mem-aperture = <0xa0000000 0x40000000>;
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};
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eco-button-interrupt {
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compatible = "atl,eco-button-interrupt";
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eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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board-reset {
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compatible = "atl,phy_reset";
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/* Physical board layout of reset pin is active-low but for the
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* current driver we have to set it to active-high here.
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*/
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phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
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<&gpio1 21 GPIO_ACTIVE_HIGH>;
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};
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phy-int {
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compatible = "linux,uio-pdrv-genirq";
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interrupt-parent = <&gpio0>;
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interrupts = <6 IRQ_TYPE_EDGE_BOTH>;
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};
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led-enable {
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compatible = "atl,led-enable";
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led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
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};
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led_7seg {
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compatible = "atl,of-led-7seg";
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segment-gpios = <
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&led_7seg_gpio 0 0
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&led_7seg_gpio 1 0
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&led_7seg_gpio 2 0
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&led_7seg_gpio 3 0
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&led_7seg_gpio 4 0
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&led_7seg_gpio 5 0
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&led_7seg_gpio 6 0
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&led_7seg_gpio 7 0>;
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};
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poe {
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compatible = "atl,periph-poe";
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poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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interrupt-parent = <&gpio0>;
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interrupts = <20 IRQ_TYPE_EDGE_BOTH>;
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie1 {
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status = "okay";
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};
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&devbus_cs1 {
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compatible = "marvell,mvebu-devbus";
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status = "okay";
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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nvs@0 {
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status = "okay";
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compatible = "mtd-ram";
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reg = <0 0x00080000>;
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bank-width = <1>;
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label = "nvs";
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};
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};
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&gpio0 {
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poe-disable {
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gpio-hog;
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gpios = <16 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-disable";
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};
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};
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&gpio1 {
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poe-mezz-reset {
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gpio-hog;
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gpios = <15 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-mezz-reset";
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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mux@71 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9544";
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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i2c@0 { /* POE devices MUX */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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rng@3b {
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compatible = "maxim,ds2476";
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reg = <0x3b>;
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};
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hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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hwmon@2d {
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compatible = "adi,adt7476";
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reg = <0x2d>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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rtc@68 {
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compatible = "dallas,ds1340";
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reg = <0x68>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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led_7seg_gpio: gpio@20 {
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compatible = "nxp,pca9554";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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};
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sfpgpio: gpio@27 { /* I2C to GPIO */
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x27>;
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interrupt-parent = <&gpio0>;
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interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
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};
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sfpmux: mux@77 { /* SFP I2C MUX */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9544";
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reg = <0x77>;
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i2c-mux-idle-disconnect;
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};
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};
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};
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};
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&spi1 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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partition@u-boot {
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reg = <0x00000000 0x00100000>;
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label = "u-boot";
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};
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partition@u-boot-env {
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reg = <0x00100000 0x00040000>;
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label = "u-boot-env";
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};
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partition@unused {
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reg = <0x00140000 0x00e80000>;
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label = "unused";
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};
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partition@idprom {
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reg = <0x00fc0000 0x00040000>;
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label = "idprom";
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};
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <25000000>;
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};
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&nand_controller { /* 256 MB */
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status = "okay";
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num-cs = <1>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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};
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51
arch/arm/dts/armada-385-atl-x530DP.dts
Normal file
51
arch/arm/dts/armada-385-atl-x530DP.dts
Normal file
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "armada-385-atl-x530.dtsi"
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#include "armada-385-atl-x530-u-boot.dtsi"
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#include "armada-385-atl-x530DP.dtsi"
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/ {
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model = "Allied Telesis x530DP";
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compatible = "alliedtelesis,x530DP", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
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nand-protect {
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compatible = "atl,nand-protect";
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protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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usb-enable {
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compatible = "atl,usb-enable";
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enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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};
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boot-board {
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compatible = "atl,boot-board";
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present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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};
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phy-reset {
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compatible = "atl,phy-reset";
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reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>,
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<&gpio1 21 GPIO_ACTIVE_HIGH>;
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};
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led-enable {
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compatible = "atl,led-enable";
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enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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};
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led_7seg {
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compatible = "atl,of-led-7seg";
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segment-gpios = <
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&led_7seg_gpio 0 0
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&led_7seg_gpio 1 0
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&led_7seg_gpio 2 0
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&led_7seg_gpio 3 0
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&led_7seg_gpio 4 0
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&led_7seg_gpio 5 0
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&led_7seg_gpio 6 0
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&led_7seg_gpio 7 0>;
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};
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};
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149
arch/arm/dts/armada-385-atl-x530DP.dtsi
Normal file
149
arch/arm/dts/armada-385-atl-x530DP.dtsi
Normal file
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@ -0,0 +1,149 @@
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// SPDX-License-Identifier: GPL-2.0
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&i2c0 {
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mux@71 {
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compatible = "nxp,pca9548";
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i2c@1 {
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hwmon@2c {
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compatible = "ti,lm87";
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reg = <0x2c>;
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};
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hwmon@2d {
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compatible = "ti,lm87";
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reg = <0x2d>;
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};
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hwmon@2e {
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pwm-polarity = <1>;
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};
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};
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psu_a_adapter: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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};
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psu_b_adapter: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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misc_gpio: gpio@26 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x26>;
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interrupt-parent = <&gpio0>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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status = "okay";
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interrupt-controller;
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#interrupt-cells = <2>;
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psu_bank2 {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "psu-bank2";
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};
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};
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};
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};
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};
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/ {
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psu_slot_a {
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compatible = "atl,dts-overlay-gpio-psu-slot";
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slot-name = "PSU Bay A";
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board-index = <1>;
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present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>;
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output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
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interrupt-parent = <&misc_gpio>;
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interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
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overlay = <&psu_a_overlay>;
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};
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psu_slot_b {
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compatible = "atl,dts-overlay-gpio-psu-slot";
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slot-name = "PSU Bay B";
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board-index = <2>;
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present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>;
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output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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interrupt-parent = <&misc_gpio>;
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interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
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overlay = <&psu_b_overlay>;
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};
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fan_slot_a {
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compatible = "atl,fan05-slot";
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slot-name = "Fan Bay A";
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board-index = <3>;
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present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>;
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fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&misc_gpio>;
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interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
|
||||
overlay = <&fan_a_overlay>;
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
psu_a_overlay: psu_a {
|
||||
fragment@0 {
|
||||
target = <&psu_a_adapter>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
psu@51 {
|
||||
compatible = "atl,atl-pwr-gen2";
|
||||
reg = <0x51>;
|
||||
board-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
psu_b_overlay: psu_b {
|
||||
fragment@0 {
|
||||
target = <&psu_b_adapter>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
psu@51 {
|
||||
compatible = "atl,atl-pwr-gen2";
|
||||
reg = <0x51>;
|
||||
board-index = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
fan_a_overlay:fan_a {
|
||||
fragment@1 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
fan@1 {
|
||||
compatible = "atl,fan05";
|
||||
board-index = <3>;
|
||||
module-id-gpios =
|
||||
<&misc_gpio 4 GPIO_ACTIVE_HIGH>,
|
||||
<&misc_gpio 5 GPIO_ACTIVE_HIGH>,
|
||||
<&misc_gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -132,6 +132,10 @@ config TARGET_CONTROLCENTERDC
|
|||
bool "Support CONTROLCENTERDC"
|
||||
select 88F6820
|
||||
|
||||
config TARGET_X530
|
||||
bool "Support Allied Telesis x530"
|
||||
select 88F6820
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_BOARD
|
||||
|
|
@ -149,6 +153,7 @@ config SYS_BOARD
|
|||
default "maxbcm" if TARGET_MAXBCM
|
||||
default "theadorable" if TARGET_THEADORABLE
|
||||
default "a38x" if TARGET_CONTROLCENTERDC
|
||||
default "x530" if TARGET_X530
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "clearfog" if TARGET_CLEARFOG
|
||||
|
|
@ -165,6 +170,7 @@ config SYS_CONFIG_NAME
|
|||
default "turris_omnia" if TARGET_TURRIS_OMNIA
|
||||
default "turris_mox" if TARGET_TURRIS_MOX
|
||||
default "controlcenterdc" if TARGET_CONTROLCENTERDC
|
||||
default "x530" if TARGET_X530
|
||||
|
||||
config SYS_VENDOR
|
||||
default "Marvell" if TARGET_DB_MV784MP_GP
|
||||
|
|
@ -179,6 +185,7 @@ config SYS_VENDOR
|
|||
default "CZ.NIC" if TARGET_TURRIS_OMNIA
|
||||
default "CZ.NIC" if TARGET_TURRIS_MOX
|
||||
default "gdsys" if TARGET_CONTROLCENTERDC
|
||||
default "alliedtelesis" if TARGET_X530
|
||||
|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
|
|
|||
36
board/alliedtelesis/common/gpio_hog.c
Normal file
36
board/alliedtelesis/common/gpio_hog.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2018 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
|
||||
const char *node_name, const char *gpio_name, int value)
|
||||
{
|
||||
int node;
|
||||
int count;
|
||||
int i;
|
||||
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
|
||||
if (node < 0)
|
||||
return -ENODEV;
|
||||
|
||||
if (!dm_gpio_is_valid(gpiod)) {
|
||||
count =
|
||||
gpio_request_list_by_name_nodev(offset_to_ofnode(node),
|
||||
gpio_name, gpiod, max_count,
|
||||
GPIOD_IS_OUT);
|
||||
if (count < 0)
|
||||
return count;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
dm_gpio_set_value(&gpiod[i], value);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
13
board/alliedtelesis/common/gpio_hog.h
Normal file
13
board/alliedtelesis/common/gpio_hog.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2017 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
|
||||
const char *gpio_name, int value);
|
||||
|
||||
static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
|
||||
const char *gpio_name, int value)
|
||||
{
|
||||
return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
|
||||
}
|
||||
12
board/alliedtelesis/x530/MAINTAINERS
Normal file
12
board/alliedtelesis/x530/MAINTAINERS
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
x530 BOARD
|
||||
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
S: Maintained
|
||||
F: board/alliedtelesis/x530/
|
||||
F: board/alliedtelesis/common/gpio_hog.c
|
||||
F: board/alliedtelesis/common/gpio_hog.h
|
||||
F: arch/arm/dts/armada-385-atl-x530.dts
|
||||
F: arch/arm/dts/armada-385-atl-x530.dtsi
|
||||
F: arch/arm/dts/armada-385-atl-x530DP.dts
|
||||
F: arch/arm/dts/armada-385-atl-x530DP.dtsi
|
||||
F: include/configs/x530.h
|
||||
F: configs/x530_defconfig
|
||||
9
board/alliedtelesis/x530/Makefile
Normal file
9
board/alliedtelesis/x530/Makefile
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2017 Allied Telesis Labs
|
||||
#
|
||||
|
||||
obj-y := $(BOARD).o
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
obj-y += ../common/gpio_hog.o
|
||||
endif
|
||||
12
board/alliedtelesis/x530/kwbimage.cfg
Normal file
12
board/alliedtelesis/x530/kwbimage.cfg
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright (C) 2017 Allied Telesis Labs
|
||||
#
|
||||
|
||||
# Armada XP uses version 1 image format
|
||||
VERSION 1
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
|
||||
161
board/alliedtelesis/x530/x530.c
Normal file
161
board/alliedtelesis/x530/x530.c
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2017 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include "../common/gpio_hog.h"
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
|
||||
|
||||
#define CONFIG_NVS_LOCATION 0xf4800000
|
||||
#define CONFIG_NVS_SIZE (512 << 10)
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR3 init code in the SPL U-Boot version to configure
|
||||
* the DDR3 controller.
|
||||
*/
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866M, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
|
||||
MV_DDR_DIE_CAP_4GBIT, /* die capacity */
|
||||
MV_DDR_FREQ_933, /* frequency */
|
||||
0, 0, /* cas_l cas_wl */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_2T} }, /* timing */
|
||||
BUS_MASK_32BIT_ECC, /* subphys mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(0x00001111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x55000000, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x55555555, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x00100565, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x40000000, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
/* window for NVS */
|
||||
mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
|
||||
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
|
||||
|
||||
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
|
||||
writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int led_7seg_init(unsigned int segments)
|
||||
{
|
||||
int node;
|
||||
int ret;
|
||||
int i;
|
||||
struct gpio_desc desc[8];
|
||||
|
||||
node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
|
||||
"atl,of-led-7seg");
|
||||
if (node < 0)
|
||||
return -ENODEV;
|
||||
|
||||
ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
|
||||
"segment-gpios", desc,
|
||||
ARRAY_SIZE(desc), GPIOD_IS_OUT);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(desc); i++) {
|
||||
ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
|
||||
led_en = {};
|
||||
|
||||
gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
|
||||
gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
|
||||
gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
|
||||
gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
|
||||
|
||||
#ifdef MTDPARTS_MTDOOPS
|
||||
env_set("mtdoops", MTDPARTS_MTDOOPS);
|
||||
#endif
|
||||
|
||||
led_7seg_init(0xff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: " CONFIG_SYS_BOARD "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
71
configs/x530_defconfig
Normal file
71
configs/x530_defconfig
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00800000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_X530=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xd0012000
|
||||
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_SILENT_U_BOOT_ONLY=y
|
||||
CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MVTWSI=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_PXA3XX=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_DS1307=y
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_KIRKWOOD_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
134
include/configs/x530.h
Normal file
134
include/configs/x530.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2018 Allied Telesis Labs
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_X530_H
|
||||
#define _CONFIG_X530_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
|
||||
#if !defined(CONFIG_DM_SERIAL)
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial Port configuration
|
||||
* The following definitions let you select what serial you want to use
|
||||
* for your console driver.
|
||||
*/
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
/* NAND */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
#define BBT_CUSTOM_SCAN
|
||||
#define BBT_CUSTOM_SCAN_PAGE 0
|
||||
#define BBT_CUSTOM_SCAN_POSITION 2048
|
||||
|
||||
/* SPI NOR flash default params, used by sf commands */
|
||||
#define CONFIG_SF_DEFAULT_BUS 1
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
||||
|
||||
#define MTDIDS_DEFAULT "nand0=nand"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
|
||||
#define MTDPARTS_MTDOOPS "errlog"
|
||||
|
||||
/* Partition support */
|
||||
|
||||
/* Additional FS support/configuration */
|
||||
|
||||
/* USB/EHCI configuration */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
|
||||
/* Environment in SPI NOR flash */
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
|
||||
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
|
||||
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
|
||||
#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
|
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
/* PCIe support */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_PCI_MVEBU
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#endif
|
||||
|
||||
/* NAND */
|
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_LZO
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20)
|
||||
|
||||
#include <asm/arch/config.h>
|
||||
|
||||
/*
|
||||
* Other required minimal configurations
|
||||
*/
|
||||
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
|
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
/* Keep device tree and initrd in low memory so the kernel can access them */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0"
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x1000000
|
||||
#define CONFIG_UBI_PART user
|
||||
#define CONFIG_UBIFS_VOLUME user
|
||||
|
||||
/* SPL */
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_SIZE (140 << 10)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40000030
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MALLOC_SIMPLE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
||||
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
|
||||
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
|
||||
|
||||
#endif /* _CONFIG_X530_H */
|
||||
Loading…
Reference in New Issue
Block a user