mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Various axp209 fixes - Fixes for OLinuXino-A20-Lime2 / OLinuXino-A20-Lime2-eMMC
This commit is contained in:
Tom Rini
commit
c49aff3e66
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@ -101,6 +101,9 @@ int pmic_bus_setbits(u8 reg, u8 bits)
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if (ret)
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return ret;
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if ((val & bits) == bits)
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return 0;
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val |= bits;
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return pmic_bus_write(reg, val);
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}
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@ -114,6 +117,9 @@ int pmic_bus_clrbits(u8 reg, u8 bits)
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if (ret)
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return ret;
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if (!(val & bits))
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return 0;
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val &= ~bits;
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return pmic_bus_write(reg, val);
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}
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@ -12,8 +12,13 @@ file describes how to make full use of the 64-bit capabilities.
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Quick Start / Overview
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======================
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- Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below)
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$ cd /src/arm-trusted-firmware
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$ make PLAT=sun50i_a64 DEBUG=1 bl31
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- Build U-Boot (see "SPL/U-Boot" below)
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$ export BL31=/path/to/bl31.bin
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$ make pine64_plus_defconfig && make -j5
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- Transfer to an uSD card (see "microSD card" below)
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$ dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
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- Boot and enjoy!
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Building the firmware
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@ -29,14 +34,18 @@ to build it first.
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ARM Trusted Firmware (ATF)
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----------------------------
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Checkout the "allwinner" branch from the github repository [1] and build it:
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Checkout the latest master branch from the official ATF repository [1] and
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build it:
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$ export CROSS_COMPILE=aarch64-linux-gnu-
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$ make PLAT=sun50iw1p1 DEBUG=1 bl31
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The resulting binary is build/sun50iw1p1/debug/bl31.bin. Either put the
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$ make PLAT=sun50i_a64 DEBUG=1 bl31
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The resulting binary is build/sun50i_a64/debug/bl31.bin. Either put the
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location of this file into the BL31 environment variable or copy this to
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the root of your U-Boot build directory (or create a symbolic link).
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$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
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$ export BL31=/src/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin
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(adjust the actual path accordingly)
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The platform target "sun50i_a64" covers all boards with either an Allwinner
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A64 or H5 SoC (since they are very similar). For boards with an Allwinner H6
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SoC use "sun50i_h6".
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If you run into size issues with the resulting U-Boot image file, it might
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help to use a release build, by using "DEBUG=0" when building bl31.bin.
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@ -59,7 +68,8 @@ $ make pine64_plus_defconfig
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$ make
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This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb,
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which contains the rest of the firmware.
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which contains the rest of the firmware. u-boot-sunxi-with-spl.bin joins those
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two components in one convenient image file.
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Boot process
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@ -91,6 +101,9 @@ by using the USB-OTG interface and a host port on another computer.
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As the FEL mode is controlled by the boot ROM, it expects to be running in
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AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the
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feature is disabled in the configuration at the moment.
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The repository in [3] contains FEL capable SPL binaries, built using an
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off-tree branch to generate 32-bit ARM code (along with instructions
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how to re-create them).
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microSD card
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------------
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@ -165,6 +178,6 @@ Then write this image to a microSD card, replacing /dev/sdx with the right
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device file (see above):
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$ dd if=firmware.img of=/dev/sdx bs=8k seek=1
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[1] https://github.com/apritzel/arm-trusted-firmware.git
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[1] https://github.com/ARM-software/arm-trusted-firmware.git
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[2] git://github.com/linux-sunxi/sunxi-tools.git
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[3] https://github.com/apritzel/pine64/
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@ -637,13 +637,6 @@ void sunxi_board_init(void)
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power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
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#endif
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#endif
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printf("DRAM:");
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gd->ram_size = sunxi_dram_init();
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printf(" %d MiB\n", (int)(gd->ram_size >> 20));
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if (!gd->ram_size)
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hang();
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sunxi_spl_store_dram_size(gd->ram_size);
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/*
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* Only clock up the CPU to full speed if we are reasonably
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@ -652,7 +645,16 @@ void sunxi_board_init(void)
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if (!power_failed)
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clock_set_pll1(CONFIG_SYS_CLK_FREQ);
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else
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printf("Failed to set core voltage! Can't set CPU frequency\n");
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printf("Error setting up the power controller.\n"
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"CPU frequency not set.\n");
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printf("DRAM:");
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gd->ram_size = sunxi_dram_init();
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printf(" %d MiB\n", (int)(gd->ram_size >> 20));
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if (!gd->ram_size)
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hang();
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sunxi_spl_store_dram_size(gd->ram_size);
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}
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#endif
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@ -26,7 +26,9 @@ CONFIG_ETH_DESIGNWARE=y
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CONFIG_RGMII=y
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CONFIG_MII=y
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CONFIG_SUN7I_GMAC=y
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CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
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CONFIG_AXP_ALDO3_VOLT=2800
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CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
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CONFIG_AXP_ALDO4_VOLT=2800
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CONFIG_SCSI=y
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CONFIG_USB_EHCI_HCD=y
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@ -25,7 +25,9 @@ CONFIG_ETH_DESIGNWARE=y
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CONFIG_RGMII=y
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CONFIG_MII=y
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CONFIG_SUN7I_GMAC=y
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CONFIG_AXP_ALDO3_INRUSH_QUIRK=y
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CONFIG_AXP_ALDO3_VOLT=2800
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CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
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CONFIG_AXP_ALDO4_VOLT=2800
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CONFIG_SCSI=y
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CONFIG_USB_EHCI_HCD=y
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@ -197,6 +197,49 @@ config AXP_ALDO3_VOLT
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On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
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3.0V.
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choice
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prompt "axp pmic (a)ldo3 voltage rate control"
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depends on AXP209_POWER
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default AXP_ALDO3_VOLT_SLOPE_NONE
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---help---
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The AXP can slowly ramp up voltage to reduce the inrush current when
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changing voltages.
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Note, this does not apply when enabling/disabling LDO3. See
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"axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit
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inrush current on broken board designs.
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config AXP_ALDO3_VOLT_SLOPE_NONE
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bool "No voltage slope"
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---help---
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Tries to reach the next voltage setting near instantaneously. Measurements
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indicate that this is about 0.0167 V/uS.
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config AXP_ALDO3_VOLT_SLOPE_16
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bool "1.6 mV per uS"
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---help---
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Increases the voltage by 1.6 mV per uS until the final voltage has
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been reached. Note that the scaling is in 25 mV steps and thus
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the slew rate in reality is about 25 mV/31.250 uS.
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config AXP_ALDO3_VOLT_SLOPE_08
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bool "0.8 mV per uS"
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---help---
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Increases the voltage by 0.8 mV per uS until the final voltage has
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been reached. Note that the scaling is in 25 mV steps however and thus
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the slew rate in reality is about 25 mV/15.625 uS.
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This is the slowest supported rate.
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endchoice
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config AXP_ALDO3_INRUSH_QUIRK
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bool "axp pmic (a)ldo3 inrush quirk"
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depends on AXP209_POWER
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default n
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---help---
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The reference design denotes a value of 4.7 uF for the output capacitor
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of LDO3. Some boards have too high capacitance causing an inrush current
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and resulting an AXP209 shutdown.
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config AXP_ALDO4_VOLT
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int "axp pmic (a)ldo4 voltage"
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depends on AXP209_POWER
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@ -9,6 +9,16 @@
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#include <asm/arch/pmic_bus.h>
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#include <axp_pmic.h>
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#ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_08
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# define AXP209_VRC_SLOPE AXP209_VRC_LDO3_800uV_uS
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#endif
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#ifdef CONFIG_AXP_ALDO3_VOLT_SLOPE_16
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# define AXP209_VRC_SLOPE AXP209_VRC_LDO3_1600uV_uS
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#endif
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#if defined CONFIG_AXP_ALDO3_VOLT_SLOPE_NONE || !defined AXP209_VRC_SLOPE
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# define AXP209_VRC_SLOPE 0x00
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#endif
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static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
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{
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if (mvolt < min)
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@ -81,8 +91,7 @@ int axp_set_aldo2(unsigned int mvolt)
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if (rc)
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return rc;
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/* LDO2 configuration is in upper 4 bits */
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reg = (reg & 0x0f) | (cfg << 4);
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reg |= AXP209_LDO24_LDO2_SET(reg, cfg);
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rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg);
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if (rc)
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return rc;
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@ -99,10 +108,49 @@ int axp_set_aldo3(unsigned int mvolt)
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return pmic_bus_clrbits(AXP209_OUTPUT_CTRL,
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AXP209_OUTPUT_CTRL_LDO3);
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if (mvolt == -1)
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cfg = 0x80; /* determined by LDO3IN pin */
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else
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/*
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* Some boards have trouble reaching the target voltage without causing
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* great inrush currents. To prevent this, boards can enable a certain
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* slope to ramp up voltage. Note, this only works when changing an
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* already active power rail. When toggling power on, the AXP ramps up
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* steeply at 0.0167 V/uS.
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*/
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rc = pmic_bus_read(AXP209_VRC_DCDC2_LDO3, &cfg);
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cfg = AXP209_VRC_LDO3_SLOPE_SET(cfg, AXP209_VRC_SLOPE);
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rc |= pmic_bus_write(AXP209_VRC_DCDC2_LDO3, cfg);
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if (rc)
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return rc;
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#ifdef CONFIG_AXP_ALDO3_INRUSH_QUIRK
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/*
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* On some boards, LDO3 has a too big capacitor installed. When
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* turning on LDO3, this causes the AXP209 to shutdown on
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* voltages over 1.9 volt. As a workaround, we enable LDO3
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* first with the lowest possible voltage. If this still causes
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* high inrush currents, the voltage slope should be increased.
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*/
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rc = pmic_bus_read(AXP209_OUTPUT_CTRL, &cfg);
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if (rc)
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return rc;
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if (!(cfg & AXP209_OUTPUT_CTRL_LDO3)) {
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rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, 0x0); /* 0.7 Volt */
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mdelay(1);
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rc |= pmic_bus_setbits(AXP209_OUTPUT_CTRL,
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AXP209_OUTPUT_CTRL_LDO3);
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if (rc)
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return rc;
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}
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#endif
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if (mvolt == -1) {
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cfg = AXP209_LDO3_VOLTAGE_FROM_LDO3IN;
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} else {
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cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
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cfg = AXP209_LDO3_VOLTAGE_SET(cfg);
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}
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rc = pmic_bus_write(AXP209_LDO3_VOLTAGE, cfg);
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if (rc)
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|
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@ -131,8 +179,7 @@ int axp_set_aldo4(unsigned int mvolt)
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if (rc)
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return rc;
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||||
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/* LDO4 configuration is in lower 4 bits */
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reg = (reg & 0xf0) | (cfg << 0);
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reg |= AXP209_LDO24_LDO4_SET(reg, cfg);
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||||
rc = pmic_bus_write(AXP209_LDO24_VOLTAGE, reg);
|
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if (rc)
|
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return rc;
|
||||
|
|
@ -153,10 +200,7 @@ int axp_init(void)
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if (rc)
|
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return rc;
|
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|
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/* Low 4 bits is chip version */
|
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ver &= 0x0f;
|
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|
||||
if (ver != 0x1)
|
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if ((ver & AXP209_CHIP_VERSION_MASK) != 0x1)
|
||||
return -EINVAL;
|
||||
|
||||
/* Mask all interrupts */
|
||||
|
|
|
|||
|
|
@ -3,11 +3,14 @@
|
|||
* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
|
||||
*/
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
enum axp209_reg {
|
||||
AXP209_POWER_STATUS = 0x00,
|
||||
AXP209_CHIP_VERSION = 0x03,
|
||||
AXP209_OUTPUT_CTRL = 0x12,
|
||||
AXP209_DCDC2_VOLTAGE = 0x23,
|
||||
AXP209_VRC_DCDC2_LDO3 = 0x25,
|
||||
AXP209_DCDC3_VOLTAGE = 0x27,
|
||||
AXP209_LDO24_VOLTAGE = 0x28,
|
||||
AXP209_LDO3_VOLTAGE = 0x29,
|
||||
|
|
@ -20,29 +23,64 @@ enum axp209_reg {
|
|||
AXP209_SHUTDOWN = 0x32,
|
||||
};
|
||||
|
||||
#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
|
||||
#define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4)
|
||||
#define AXP209_POWER_STATUS_ON_BY_DC BIT(0)
|
||||
#define AXP209_POWER_STATUS_VBUS_USABLE BIT(4)
|
||||
|
||||
#define AXP209_OUTPUT_CTRL_EXTEN (1 << 0)
|
||||
#define AXP209_OUTPUT_CTRL_DCDC3 (1 << 1)
|
||||
#define AXP209_OUTPUT_CTRL_LDO2 (1 << 2)
|
||||
#define AXP209_OUTPUT_CTRL_LDO4 (1 << 3)
|
||||
#define AXP209_OUTPUT_CTRL_DCDC2 (1 << 4)
|
||||
#define AXP209_OUTPUT_CTRL_LDO3 (1 << 6)
|
||||
#define AXP209_CHIP_VERSION_MASK 0x0f
|
||||
|
||||
#define AXP209_IRQ5_PEK_UP (1 << 6)
|
||||
#define AXP209_IRQ5_PEK_DOWN (1 << 5)
|
||||
#define AXP209_OUTPUT_CTRL_EXTEN BIT(0)
|
||||
#define AXP209_OUTPUT_CTRL_DCDC3 BIT(1)
|
||||
#define AXP209_OUTPUT_CTRL_LDO2 BIT(2)
|
||||
#define AXP209_OUTPUT_CTRL_LDO4 BIT(3)
|
||||
#define AXP209_OUTPUT_CTRL_DCDC2 BIT(4)
|
||||
#define AXP209_OUTPUT_CTRL_LDO3 BIT(6)
|
||||
|
||||
#define AXP209_POWEROFF (1 << 7)
|
||||
/*
|
||||
* AXP209 datasheet contains wrong information about LDO3 VRC:
|
||||
* - VRC is actually enabled when BIT(1) is True
|
||||
* - VRC is actually not enabled by default (BIT(3) = 0 after reset)
|
||||
*/
|
||||
#define AXP209_VRC_LDO3_EN BIT(3)
|
||||
#define AXP209_VRC_DCDC2_EN BIT(2)
|
||||
#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN)
|
||||
#define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN
|
||||
#define AXP209_VRC_DCDC2_800uV_uS (BIT(0) | AXP209_VRC_DCDC2_EN)
|
||||
#define AXP209_VRC_DCDC2_1600uV_uS AXP209_VRC_DCDC2_EN
|
||||
#define AXP209_VRC_LDO3_MASK 0xa
|
||||
#define AXP209_VRC_DCDC2_MASK 0x5
|
||||
#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \
|
||||
(((reg) & ~AXP209_VRC_DCDC2_MASK) | \
|
||||
((cfg) & AXP209_VRC_DCDC2_MASK))
|
||||
#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \
|
||||
(((reg) & ~AXP209_VRC_LDO3_MASK) | \
|
||||
((cfg) & AXP209_VRC_LDO3_MASK))
|
||||
|
||||
#define AXP209_LDO24_LDO2_MASK 0xf0
|
||||
#define AXP209_LDO24_LDO4_MASK 0x0f
|
||||
#define AXP209_LDO24_LDO2_SET(reg, cfg) \
|
||||
(((reg) & ~AXP209_LDO24_LDO2_MASK) | \
|
||||
(((cfg) << 4) & AXP209_LDO24_LDO2_MASK))
|
||||
#define AXP209_LDO24_LDO4_SET(reg, cfg) \
|
||||
(((reg) & ~AXP209_LDO24_LDO4_MASK) | \
|
||||
(((cfg) << 0) & AXP209_LDO24_LDO4_MASK))
|
||||
|
||||
#define AXP209_LDO3_VOLTAGE_FROM_LDO3IN BIT(7)
|
||||
#define AXP209_LDO3_VOLTAGE_MASK 0x7f
|
||||
#define AXP209_LDO3_VOLTAGE_SET(x) ((x) & AXP209_LDO3_VOLTAGE_MASK)
|
||||
|
||||
#define AXP209_IRQ5_PEK_UP BIT(6)
|
||||
#define AXP209_IRQ5_PEK_DOWN BIT(5)
|
||||
|
||||
#define AXP209_POWEROFF BIT(7)
|
||||
|
||||
/* For axp_gpio.c */
|
||||
#define AXP_POWER_STATUS 0x00
|
||||
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
|
||||
#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5)
|
||||
#define AXP_GPIO0_CTRL 0x90
|
||||
#define AXP_GPIO1_CTRL 0x92
|
||||
#define AXP_GPIO2_CTRL 0x93
|
||||
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
|
||||
#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
|
||||
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
|
||||
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
|
||||
#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
|
||||
#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
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||||
#define AXP_GPIO_STATE 0x94
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||||
#define AXP_GPIO_STATE_OFFSET 4
|
||||
#define AXP_GPIO_STATE_OFFSET 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user