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configs: fsl: move DDR specific defines to Kconfig 

Moves below DDR specific defines to Kconfig:

CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Rajesh Bhagat 2019-02-01 05:22:01 +00:00 committed by Prabhakar Kushwaha
parent 31a1c951ef
commit 32413125b3
43 changed files with 40 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/Kconfig
View File

@ -1005,6 +1005,7 @@ config TARGET_LS2080A_EMU
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select FSL_DDR_SYNC_REFRESH
help
Support for Freescale LS2080A_EMU platform
The LS2080A Development System (EMULATOR) is a pre silicon
@ -1031,6 +1032,7 @@ config TARGET_LS1088AQDS
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
help
Support for NXP LS1088AQDS platform
The LS1088A Development System (QDS) is a high-performance
@ -1047,6 +1049,8 @@ config TARGET_LS2080AQDS
select SUPPORT_SPL
imply SCSI
imply SCSI_AHCI
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
help
Support for Freescale LS2080AQDS platform
The LS2080A Development System (QDS) is a high-performance
@ -1061,6 +1065,8 @@ config TARGET_LS2080ARDB
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
imply SCSI
imply SCSI_AHCI
help
@ -1205,6 +1211,7 @@ config TARGET_LS1088ARDB
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
help
Support for NXP LS1088ARDB platform.
The LS1088A Reference design board (RDB) is a high-performance
@ -1223,6 +1230,7 @@ config TARGET_LS1021AQDS
select LS1_DEEP_SLEEP
select SUPPORT_SPL
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
imply SCSI
config TARGET_LS1021ATWR
@ -1262,6 +1270,7 @@ config TARGET_LS1043AQDS
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SPL
imply SCSI
imply SCSI_AHCI
help
@ -1287,6 +1296,9 @@ config TARGET_LS1046AQDS
select BOARD_LATE_INIT
select DM_SPI_FLASH if DM_SPI
select SUPPORT_SPL
select FSL_DDR_BIST if !SPL
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DDR_INTERACTIVE if !SPL
imply SCSI
help
Support for Freescale LS1046AQDS platform.
@ -1304,6 +1316,8 @@ config TARGET_LS1046ARDB
select DM_SPI_FLASH if DM_SPI
select POWER_MC34VR500
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
imply SCSI
help
Support for Freescale LS1046ARDB platform.

13
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -37,6 +37,7 @@ config TARGET_B4860QDS
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE if !SPL_BUILD
imply PANIC_HANG
config TARGET_BSC9131RDB
@ -51,6 +52,7 @@ config TARGET_BSC9132QDS
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select FSL_DDR_INTERACTIVE
config TARGET_C29XPCIE
bool "Support C29XPCIE"
@ -165,6 +167,7 @@ config TARGET_P1022DS
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply PANIC_HANG
@ -273,6 +276,7 @@ config TARGET_T1023RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply PANIC_HANG
@ -282,6 +286,7 @@ config TARGET_T1024RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply PANIC_HANG
@ -290,6 +295,7 @@ config TARGET_T1040QDS
select ARCH_T1040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
@ -344,6 +350,8 @@ config TARGET_T2080QDS
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
imply CMD_SATA
config TARGET_T2080RDB
@ -360,6 +368,8 @@ config TARGET_T2081QDS
select ARCH_T2081
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
config TARGET_T4160QDS
bool "Support T4160QDS"
@ -383,6 +393,7 @@ config TARGET_T4240QDS
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
imply CMD_SATA
imply PANIC_HANG
@ -391,6 +402,7 @@ config TARGET_T4240RDB
select ARCH_T4240
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
imply CMD_SATA
imply PANIC_HANG
@ -402,6 +414,7 @@ config TARGET_KMP204X
bool "Support kmp204x"
select ARCH_P2041
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_CRAMFS
imply FS_CRAMFS

1
arch/powerpc/cpu/mpc86xx/Kconfig
View File

@ -21,6 +21,7 @@ config TARGET_MPC8610HPCD
config TARGET_MPC8641HPCN
bool "Support MPC8641HPCN"
select ARCH_MPC8641
select FSL_DDR_INTERACTIVE
imply SCSI
config TARGET_XPEDITE517X

12
drivers/ddr/fsl/Kconfig
View File

@ -20,6 +20,18 @@ config SYS_FSL_DDR_LE
help
Access DDR registers in little-endian
config FSL_DDR_BIST
bool
config FSL_DDR_INTERACTIVE
bool
config FSL_DDR_SYNC_REFRESH
bool
config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
bool
menu "Freescale DDR controllers"
depends on SYS_FSL_DDR

3
include/configs/B4860QDS.h
View File

@ -194,9 +194,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE
#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x51

1
include/configs/BSC9132QDS.h
View File

@ -105,7 +105,6 @@
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/MPC8536DS.h
View File

@ -83,7 +83,6 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

1
include/configs/MPC8540ADS.h
View File

@ -67,7 +67,6 @@
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/MPC8541CDS.h
View File

@ -41,7 +41,6 @@ extern unsigned long get_clock_freq(void);
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/MPC8544DS.h
View File

@ -45,7 +45,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

1
include/configs/MPC8548CDS.h
View File

@ -56,7 +56,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD

1
include/configs/MPC8555CDS.h
View File

@ -41,7 +41,6 @@ extern unsigned long get_clock_freq(void);
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/MPC8560ADS.h
View File

@ -66,7 +66,6 @@
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/MPC8568MDS.h
View File

@ -44,7 +44,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */

1
include/configs/MPC8569MDS.h
View File

@ -68,7 +68,6 @@ extern unsigned long get_clock_freq(void);
#endif
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */

1
include/configs/MPC8572DS.h
View File

@ -73,7 +73,6 @@
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

1
include/configs/MPC8610HPCD.h
View File

@ -72,7 +72,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
#define CONFIG_DDR_SPD

1
include/configs/MPC8641HPCN.h
View File

@ -97,7 +97,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* DDR Setup
*/
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

1
include/configs/P1023RDB.h
View File

@ -59,7 +59,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x50

1
include/configs/T102xRDB.h
View File

@ -236,7 +236,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_FSL_DDR_INTERACTIVE
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 0

1
include/configs/T1040QDS.h
View File

@ -140,7 +140,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51

2
include/configs/T208xQDS.h
View File

@ -189,9 +189,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51

1
include/configs/T208xRDB.h
View File

@ -175,7 +175,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51

1
include/configs/T4240RDB.h
View File

@ -112,7 +112,6 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD

1
include/configs/UCP1020.h
View File

@ -133,7 +133,6 @@
#define CONFIG_DDR_SPD
#endif
#define CONFIG_SYS_SPD_BUS_NUM 1
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL 1

1
include/configs/km/kmp204x-common.h
View File

@ -94,7 +94,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54

1
include/configs/ls1021aqds.h
View File

@ -89,7 +89,6 @@ unsigned long get_board_ddr_clk(void);
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif

4
include/configs/ls1043aqds.h
View File

@ -28,10 +28,6 @@ unsigned long get_board_ddr_clk(void);
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER

2
include/configs/ls1043ardb.h
View File

@ -21,8 +21,6 @@
#ifndef CONFIG_SPL
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#define CONFIG_FSL_DDR_BIST
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

4
include/configs/ls1046aqds.h
View File

@ -28,10 +28,6 @@ unsigned long get_board_ddr_clk(void);
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER

4
include/configs/ls1046ardb.h
View File

@ -24,10 +24,6 @@
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg

4
include/configs/ls1088a_common.h
View File

@ -48,10 +48,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#if !defined(CONFIG_SD_BOOT)
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0

3
include/configs/ls2080a_common.h
View File

@ -34,9 +34,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif

2
include/configs/ls2080a_emu.h
View File

@ -24,8 +24,6 @@
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_FSL_DDR_SYNC_REFRESH
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/*

3
include/configs/ls2080aqds.h
View File

@ -42,7 +42,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
@ -64,8 +63,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ENV_SECT_SIZE 0x20000
#endif
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)

2
include/configs/ls2080ardb.h
View File

@ -57,7 +57,6 @@ unsigned long get_board_sys_clk(void);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
@ -80,7 +79,6 @@ unsigned long get_board_sys_clk(void);
#endif
#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)

1
include/configs/p1_p2_rdb_pc.h
View File

@ -266,7 +266,6 @@
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
#undef CONFIG_FSL_DDR_INTERACTIVE
#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G

1
include/configs/sbc8548.h
View File

@ -83,7 +83,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
/*
* A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD

1
include/configs/socrates.h
View File

@ -60,7 +60,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

1
include/configs/t4qds.h
View File

@ -73,7 +73,6 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD

1
include/configs/xpedite520x.h
View File

@ -25,7 +25,6 @@
/*
* DDR config
*/
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/xpedite537x.h
View File

@ -33,7 +33,6 @@
/*
* DDR config
*/
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef

4
scripts/config_whitelist.txt
View File

@ -624,10 +624,6 @@ CONFIG_FSL_CADMUS
CONFIG_FSL_CORENET
CONFIG_FSL_CPLD
CONFIG_FSL_DCU_SII9022A
CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESH
CONFIG_FSL_DEEP_SLEEP
CONFIG_FSL_DEVICE_DISABLE
CONFIG_FSL_DIU_CH7301