rockchip: add support for veyron-speedy (ASUS Chromebook C201)
This adds support for the ASUS C201, a RK3288-based clamshell device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters are for 4GB Samsung LPDDR3, decoded from coreboot's src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Marty E. Plummer
Philipp Tomsich
parent
09056c94a1
commit
8e2e601c5f
|
|
@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
|||
rk3288-veyron-jerry.dtb \
|
||||
rk3288-veyron-mickey.dtb \
|
||||
rk3288-veyron-minnie.dtb \
|
||||
rk3288-veyron-speedy.dtb \
|
||||
rk3288-vyasa.dtb \
|
||||
rk3328-evb.dtb \
|
||||
rk3399-ficus.dtb \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2015 Google, Inc
|
||||
*/
|
||||
|
||||
&dmc {
|
||||
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
|
||||
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
|
||||
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
|
||||
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
|
||||
0x8 0x1f4>;
|
||||
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
|
||||
0x0 0xc3 0x6 0x1>;
|
||||
rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Veyron Speedy Rev 1+ board device tree source
|
||||
*
|
||||
* Copyright 2015 Google, Inc
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3288-veyron-chromebook.dtsi"
|
||||
#include "cros-ec-sbs.dtsi"
|
||||
#include "rk3288-veyron-speedy-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Speedy";
|
||||
compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
|
||||
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
|
||||
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
|
||||
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
||||
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
||||
|
||||
panel_regulator: panel-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_enable_h>;
|
||||
regulator-name = "panel_regulator";
|
||||
startup-delay-us = <100000>;
|
||||
vin-supply = <&vcc33_sys>;
|
||||
};
|
||||
|
||||
vcc18_lcd: vcc18-lcd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&avdd_1v8_disp_en>;
|
||||
regulator-name = "vcc18_lcd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc18_wl>;
|
||||
};
|
||||
|
||||
backlight_regulator: backlight-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bl_pwr_en>;
|
||||
regulator-name = "backlight_regulator";
|
||||
vin-supply = <&vcc33_sys>;
|
||||
startup-delay-us = <15000>;
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
power-supply = <&backlight_regulator>;
|
||||
};
|
||||
|
||||
&cpu_alert0 {
|
||||
temperature = <65000>;
|
||||
};
|
||||
|
||||
&cpu_alert1 {
|
||||
temperature = <70000>;
|
||||
};
|
||||
|
||||
&edp {
|
||||
/delete-property/pinctrl-names;
|
||||
/delete-property/pinctrl-0;
|
||||
|
||||
force-hpd;
|
||||
};
|
||||
|
||||
&panel {
|
||||
power-supply = <&panel_regulator>;
|
||||
};
|
||||
|
||||
&rk808 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
|
||||
&sdmmc_bus4>;
|
||||
};
|
||||
|
||||
&vcc_5v {
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&drv_5v>;
|
||||
};
|
||||
|
||||
&vcc50_hdmi {
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc50_hdmi_en>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
backlight {
|
||||
bl_pwr_en: bl_pwr_en {
|
||||
rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
buck-5v {
|
||||
drv_5v: drv-5v {
|
||||
rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
vcc50_hdmi_en: vcc50-hdmi-en {
|
||||
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd {
|
||||
lcd_enable_h: lcd-en {
|
||||
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
avdd_1v8_disp_en: avdd-1v8-disp-en {
|
||||
rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
dvs_1: dvs-1 {
|
||||
rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
dvs_2: dvs-2 {
|
||||
rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -71,7 +71,8 @@ u32 spl_boot_device(void)
|
|||
fallback:
|
||||
#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
|
||||
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
|
||||
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
|
||||
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
|
||||
defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
|
||||
return BOOT_DEVICE_SPI;
|
||||
#endif
|
||||
return BOOT_DEVICE_MMC1;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE
|
|||
functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
|
||||
internal MMC. The product name is ASUS Chromebook Flip.
|
||||
|
||||
config TARGET_CHROMEBOOK_SPEEDY
|
||||
bool "Google/Rockchip Veyron-Speedy Chromebook"
|
||||
select BOARD_LATE_INIT
|
||||
help
|
||||
Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
|
||||
micro HDMI, an 11.6 inch display, micro-SD card,
|
||||
HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
|
||||
EC (Cortex-M3) to provide access to the keyboard and battery
|
||||
functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
|
||||
The product name is Asus Chromebook C201PA.
|
||||
|
||||
config TARGET_EVB_RK3288
|
||||
bool "Evb-RK3288"
|
||||
select BOARD_LATE_INIT
|
||||
|
|
|
|||
|
|
@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
def_bool y
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_CHROMEBOOK_SPEEDY
|
||||
|
||||
config SYS_BOARD
|
||||
default "veyron"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "google"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "veyron"
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,100 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00100000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ROCKCHIP_RK3288=y
|
||||
# CONFIG_SPL_MMC_SUPPORT is not set
|
||||
CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff690000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_STACK_R_ADDR=0x80000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SF_TEST=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_SPL_PARTITION_UUIDS=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_OF_PLATDATA=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
# CONFIG_SPL_SIMPLE_BUS is not set
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_I2C_CROS_EC_TUNNEL=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_DM_KEYBOARD=y
|
||||
CONFIG_CROS_EC_KEYB=y
|
||||
CONFIG_CROS_EC=y
|
||||
CONFIG_CROS_EC_SPI=y
|
||||
CONFIG_PWRSEQ=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
# CONFIG_SPL_PINCTRL_FULL is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP_RK3288=y
|
||||
CONFIG_DM_PMIC=y
|
||||
# CONFIG_SPL_PMIC_CHILDREN is not set
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_ROCKCHIP_SERIAL=y
|
||||
CONFIG_ROCKCHIP_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x2207
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
|
||||
CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_USB_FUNCTION_MASS_STORAGE=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_CONSOLE_TRUETYPE=y
|
||||
CONFIG_DISPLAY=y
|
||||
CONFIG_VIDEO_ROCKCHIP=y
|
||||
CONFIG_DISPLAY_ROCKCHIP_EDP=y
|
||||
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
# CONFIG_USE_PRIVATE_LIBGCC is not set
|
||||
CONFIG_USE_TINY_PRINTF=y
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
# CONFIG_SPL_OF_LIBFDT is not set
|
||||
Loading…
Reference in New Issue