board: pm9g45: Migrate to CONFIG_DM
Migrate the following options to CONFIG_DM: CONFIG_DM_GPIO CONFIG_DM_MMC CONFIG_DM_ETH CONFIG_DM_SERIAL CONFIG_DM_USB Signed-off-by: Ilko Iliev <iliev@ronetix.at>
This commit is contained in:
Ilko Iliev
Eugen Hristev
parent
7dee1848d7
commit
d9bd42900c
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@ -598,6 +598,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \
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dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb
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dtb-$(CONFIG_TARGET_PM9G45) += at91sam9m10g45ek.dtb
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dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
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at91sam9g15ek.dtb \
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at91sam9g25ek.dtb \
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@ -124,7 +124,7 @@ int board_init(void)
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/* arch number of AT91SAM9M10G45EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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pm9g45_nand_hw_init();
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@ -139,15 +139,15 @@ int board_init(void)
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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@ -2,27 +2,57 @@ CONFIG_ARM=y
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CONFIG_ARCH_AT91=y
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CONFIG_SYS_TEXT_BASE=0x73f00000
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CONFIG_TARGET_PM9G45=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_DEBUG_UART_BASE=0xffffee00
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CONFIG_DEBUG_UART_CLOCK=132000000
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CONFIG_DEBUG_UART=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
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CONFIG_NAND_BOOT=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="fbcon=rotate:3 console=tty0 console=ttyS0,115200 root=/dev/mtdblock4 mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,1664k(env),2M(linux)ro,-(root) rw rootfstype=jffs2"
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="U-Boot> "
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# CONFIG_CMD_BDI is not set
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_JFFS2=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="at91sam9m10g45ek"
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CONFIG_ENV_IS_IN_NAND=y
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# CONFIG_MMC is not set
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CONFIG_NAND=y
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CONFIG_DM=y
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CONFIG_CLK=y
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CONFIG_CLK_AT91=y
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CONFIG_DM_GPIO=y
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CONFIG_AT91_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND_ATMEL=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_AT91=y
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CONFIG_DM_SERIAL=y
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CONFIG_DEBUG_UART_ATMEL=y
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_ATMEL_USART=y
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CONFIG_TIMER=y
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CONFIG_ATMEL_PIT_TIMER=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_STORAGE=y
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@ -15,110 +15,119 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
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#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_ATMEL_USART 1
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_SYS_USE_NANDFLASH 1
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/* LED */
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#define CONFIG_AT91_LED
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#define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */
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#define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_JFFS2_CMDLINE 1
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#define CONFIG_JFFS2_NAND 1
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#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */
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#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* SDRAM */
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#define PHYS_SDRAM 0x70000000
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#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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#define CONFIG_SYS_SDRAM_BASE 0x70000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
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#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3)
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#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3
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#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
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#endif
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/* Ethernet */
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#define CONFIG_MACB 1
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#define CONFIG_RMII 1
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_RESET_PHY_R 1
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#define CONFIG_RESET_PHY_R
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#define CONFIG_AT91_WANTS_COMMON_PHY
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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/* board specific(not enough SRAM) */
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#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */
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#ifdef CONFIG_NAND_BOOT
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/* bootstrap + u-boot + env in nandflash */
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#define CONFIG_ENV_OFFSET 0x140000
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#define CONFIG_ENV_OFFSET_REDUND 0x100000
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
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#define CONFIG_BOOTCOMMAND \
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"nand read 0x70000000 0x200000 0x300000;" \
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"bootm 0x70000000"
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#elif CONFIG_SD_BOOT
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/* bootstrap + u-boot + env + linux in mmc */
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#define CONFIG_ENV_SIZE 0x4000
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/* bootstrap + u-boot + env + linux in nandflash */
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_OFFSET_REDUND 0x80000
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#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
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#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
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#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
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"fatload mmc 0:1 0x72000000 zImage; " \
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"bootz 0x72000000 - 0x71000000"
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#endif
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
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0x1000)
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
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128 * 1024, 0x1000)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x010000
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#define CONFIG_SPL_STACK 0x310000
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_BSS_START_ADDR 0x70000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
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#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#elif CONFIG_NAND_BOOT
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#endif
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#endif
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