arm: dts: Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd]
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones from kernel v4.20 (commit 8fe28cb58bcb2). Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Abel Vesa
Stefano Babic
parent
e72e3549a8
commit
67f165ddfd
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@ -446,7 +446,13 @@ dtb-$(CONFIG_MX6QDL) += \
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imx6q-icore.dtb \
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imx6q-icore-mipi.dtb \
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imx6q-icore-rqs.dtb \
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imx6q-logicpd.dtb
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imx6q-logicpd.dtb \
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imx6q-sabreauto.dtb \
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imx6q-sabresd.dtb \
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imx6dl-sabreauto.dtb \
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imx6dl-sabresd.dtb \
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imx6qp-sabreauto.dtb \
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imx6qp-sabresd.dtb
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dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
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@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2013 Freescale Semiconductor, Inc.
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/dts-v1/;
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#include "imx6dl.dtsi"
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#include "imx6qdl-sabreauto.dtsi"
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/ {
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model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
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compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
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};
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@ -0,0 +1,18 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2013 Freescale Semiconductor, Inc.
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/dts-v1/;
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#include "imx6dl.dtsi"
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#include "imx6qdl-sabresd.dtsi"
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/ {
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model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
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compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
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};
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&ipu1_csi1_from_ipu1_csi1_mux {
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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@ -1,12 +1,6 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2013 Freescale Semiconductor, Inc.
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6dl-pinfunc.h"
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@ -39,6 +33,7 @@
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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#cooling-cells = <2>;
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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@ -56,39 +51,57 @@
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1150000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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};
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soc {
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ocram: sram@00900000 {
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ocram: sram@900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips1: aips-bus@02000000 {
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iomuxc: iomuxc@020e0000 {
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aips1: aips-bus@2000000 {
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iomuxc: iomuxc@20e0000 {
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compatible = "fsl,imx6dl-iomuxc";
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};
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pxp: pxp@020f0000 {
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pxp: pxp@20f0000 {
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reg = <0x020f0000 0x4000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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epdc: epdc@020f4000 {
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epdc: epdc@20f4000 {
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reg = <0x020f4000 0x4000>;
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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lcdif: lcdif@020f8000 {
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reg = <0x020f8000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aips2: aips-bus@02100000 {
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i2c4: i2c@021f8000 {
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aips2: aips-bus@2100000 {
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i2c4: i2c@21f8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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@ -100,14 +113,177 @@
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};
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};
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capture-subsystem {
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compatible = "fsl,imx-capture-subsystem";
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ports = <&ipu1_csi0>, <&ipu1_csi1>;
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu1_di0>, <&ipu1_di1>;
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};
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};
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gpu-subsystem {
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compatible = "fsl,imx-gpu-subsystem";
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cores = <&gpu_2d>, <&gpu_3d>;
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&gpio1 {
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gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
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<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
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<&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
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<&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
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<&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
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<&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
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<&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
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};
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&gpio2 {
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gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
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<&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
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<&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
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<&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
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<&iomuxc 28 113 4>;
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};
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&gpio3 {
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gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
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<&iomuxc 16 81 16>;
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};
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&gpio4 {
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gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
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<&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
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<&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
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<&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
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<&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
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};
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&gpio5 {
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gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
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<&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
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<&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
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<&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
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};
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&gpio6 {
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gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
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<&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
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<&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
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<&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
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<&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
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<&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
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};
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&gpio7 {
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gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
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<&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
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<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
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};
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&gpr {
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ipu1_csi0_mux {
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compatible = "video-mux";
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mux-controls = <&mux 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ipu1_csi0_mux_from_mipi_vc0: endpoint {
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remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
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};
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};
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port@1 {
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reg = <1>;
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ipu1_csi0_mux_from_mipi_vc1: endpoint {
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remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
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};
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};
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port@2 {
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reg = <2>;
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ipu1_csi0_mux_from_mipi_vc2: endpoint {
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remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
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};
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};
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port@3 {
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reg = <3>;
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ipu1_csi0_mux_from_mipi_vc3: endpoint {
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remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
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};
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};
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port@4 {
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reg = <4>;
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ipu1_csi0_mux_from_parallel_sensor: endpoint {
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};
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};
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port@5 {
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reg = <5>;
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ipu1_csi0_mux_to_ipu1_csi0: endpoint {
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remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
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};
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};
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};
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ipu1_csi1_mux {
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compatible = "video-mux";
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mux-controls = <&mux 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ipu1_csi1_mux_from_mipi_vc0: endpoint {
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remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
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};
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};
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port@1 {
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reg = <1>;
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ipu1_csi1_mux_from_mipi_vc1: endpoint {
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remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
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};
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};
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port@2 {
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reg = <2>;
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ipu1_csi1_mux_from_mipi_vc2: endpoint {
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remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
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};
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};
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port@3 {
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reg = <3>;
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ipu1_csi1_mux_from_mipi_vc3: endpoint {
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remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
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};
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};
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port@4 {
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reg = <4>;
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ipu1_csi1_mux_from_parallel_sensor: endpoint {
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};
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};
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port@5 {
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reg = <5>;
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ipu1_csi1_mux_to_ipu1_csi1: endpoint {
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remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
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};
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};
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};
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};
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@ -119,6 +295,12 @@
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compatible = "fsl,imx6dl-hdmi";
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};
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&ipu1_csi1 {
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ipu1_csi1_from_ipu1_csi1_mux: endpoint {
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remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
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};
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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@ -128,6 +310,82 @@
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"di0", "di1";
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};
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&mipi_csi {
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
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};
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mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
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};
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};
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port@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
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};
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mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
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};
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};
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port@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
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};
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mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
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};
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};
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port@4 {
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
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};
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mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
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};
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};
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};
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&mux {
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mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
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<0x34 0x00000038>, /* IPU_CSI1_MUX */
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<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
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<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
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<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
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<0x28 0x00000003>, /* DCIC1_MUX_CTL */
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<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
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};
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&vpu {
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compatible = "fsl,imx6dl-vpu", "cnm,coda960";
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};
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@ -0,0 +1,18 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2012 Freescale Semiconductor, Inc.
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// Copyright 2011 Linaro Ltd.
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/dts-v1/;
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#include "imx6q.dtsi"
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#include "imx6qdl-sabreauto.dtsi"
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/ {
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model = "Freescale i.MX6 Quad SABRE Automotive Board";
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compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
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};
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&sata {
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status = "okay";
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};
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|
|
@ -0,0 +1,23 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Copyright 2012 Freescale Semiconductor, Inc.
|
||||
// Copyright 2011 Linaro Ltd.
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-sabresd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipu1_csi1_from_mipi_vc1 {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
|
|
@ -1,12 +1,6 @@
|
|||
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
//
|
||||
// Copyright 2013 Freescale Semiconductor, Inc.
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6q-pinfunc.h"
|
||||
|
|
@ -44,6 +38,7 @@
|
|||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
|
|
@ -56,38 +51,119 @@
|
|||
soc-supply = <®_soc>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1200000 1275000
|
||||
996000 1250000
|
||||
852000 1250000
|
||||
792000 1175000
|
||||
396000 975000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
1200000 1275000
|
||||
996000 1250000
|
||||
852000 1250000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SW>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
pu-supply = <®_pu>;
|
||||
soc-supply = <®_soc>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
next-level-cache = <&L2>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1200000 1275000
|
||||
996000 1250000
|
||||
852000 1250000
|
||||
792000 1175000
|
||||
396000 975000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
1200000 1275000
|
||||
996000 1250000
|
||||
852000 1250000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SW>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
pu-supply = <®_pu>;
|
||||
soc-supply = <®_soc>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
next-level-cache = <&L2>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1200000 1275000
|
||||
996000 1250000
|
||||
852000 1250000
|
||||
792000 1175000
|
||||
396000 975000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
1200000 1275000
|
||||
996000 1250000
|
||||
852000 1250000
|
||||
792000 1175000
|
||||
396000 1175000
|
||||
>;
|
||||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
clocks = <&clks IMX6QDL_CLK_ARM>,
|
||||
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
|
||||
<&clks IMX6QDL_CLK_STEP>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SW>,
|
||||
<&clks IMX6QDL_CLK_PLL1_SYS>;
|
||||
clock-names = "arm", "pll2_pfd2_396m", "step",
|
||||
"pll1_sw", "pll1_sys";
|
||||
arm-supply = <®_arm>;
|
||||
pu-supply = <®_pu>;
|
||||
soc-supply = <®_soc>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
ocram: sram@00900000 {
|
||||
ocram: sram@900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x40000>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
spba-bus@02000000 {
|
||||
ecspi5: ecspi@02018000 {
|
||||
aips-bus@2000000 { /* AIPS1 */
|
||||
spba-bus@2000000 {
|
||||
ecspi5: spi@2018000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
|
|
@ -96,18 +172,18 @@
|
|||
clocks = <&clks IMX6Q_CLK_ECSPI5>,
|
||||
<&clks IMX6Q_CLK_ECSPI5>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
|
||||
dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
iomuxc: iomuxc@20e0000 {
|
||||
compatible = "fsl,imx6q-iomuxc";
|
||||
};
|
||||
};
|
||||
|
||||
sata: sata@02200000 {
|
||||
sata: sata@2200000 {
|
||||
compatible = "fsl,imx6q-ahci";
|
||||
reg = <0x02200000 0x4000>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -118,17 +194,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu_vg: gpu@02204000 {
|
||||
gpu_vg: gpu@2204000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x02204000 0x4000>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
|
||||
<&clks IMX6QDL_CLK_GPU2D_CORE>;
|
||||
clock-names = "bus", "core";
|
||||
power-domains = <&gpc 1>;
|
||||
power-domains = <&pd_pu>;
|
||||
};
|
||||
|
||||
ipu2: ipu@02800000 {
|
||||
ipu2: ipu@2800000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
|
|
@ -143,10 +219,18 @@
|
|||
|
||||
ipu2_csi0: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
ipu2_csi0_from_mipi_vc2: endpoint {
|
||||
remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu2_csi1: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
ipu2_csi1_from_ipu2_csi1_mux: endpoint {
|
||||
remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu2_di0: port@2 {
|
||||
|
|
@ -154,22 +238,27 @@
|
|||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
ipu2_di0_disp0: disp0-endpoint {
|
||||
ipu2_di0_disp0: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu2_di0_hdmi: hdmi-endpoint {
|
||||
ipu2_di0_hdmi: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&hdmi_mux_2>;
|
||||
};
|
||||
|
||||
ipu2_di0_mipi: mipi-endpoint {
|
||||
ipu2_di0_mipi: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&mipi_mux_2>;
|
||||
};
|
||||
|
||||
ipu2_di0_lvds0: lvds0-endpoint {
|
||||
ipu2_di0_lvds0: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&lvds0_mux_2>;
|
||||
};
|
||||
|
||||
ipu2_di0_lvds1: lvds1-endpoint {
|
||||
ipu2_di0_lvds1: endpoint@4 {
|
||||
reg = <4>;
|
||||
remote-endpoint = <&lvds1_mux_2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -179,33 +268,136 @@
|
|||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
ipu2_di1_hdmi: hdmi-endpoint {
|
||||
ipu2_di1_hdmi: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&hdmi_mux_3>;
|
||||
};
|
||||
|
||||
ipu2_di1_mipi: mipi-endpoint {
|
||||
ipu2_di1_mipi: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&mipi_mux_3>;
|
||||
};
|
||||
|
||||
ipu2_di1_lvds0: lvds0-endpoint {
|
||||
ipu2_di1_lvds0: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint = <&lvds0_mux_3>;
|
||||
};
|
||||
|
||||
ipu2_di1_lvds1: lvds1-endpoint {
|
||||
ipu2_di1_lvds1: endpoint@4 {
|
||||
reg = <4>;
|
||||
remote-endpoint = <&lvds1_mux_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
capture-subsystem {
|
||||
compatible = "fsl,imx-capture-subsystem";
|
||||
ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu-subsystem {
|
||||
compatible = "fsl,imx-gpu-subsystem";
|
||||
cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
|
||||
&gpio1 {
|
||||
gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
|
||||
<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
|
||||
<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
|
||||
<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
|
||||
<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
|
||||
<&iomuxc 22 116 10>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
|
||||
<&iomuxc 31 44 1>;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
|
||||
<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
|
||||
<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
|
||||
<&iomuxc 31 86 1>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
|
||||
};
|
||||
|
||||
&gpr {
|
||||
ipu1_csi0_mux {
|
||||
compatible = "video-mux";
|
||||
mux-controls = <&mux 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
ipu1_csi0_mux_from_mipi_vc0: endpoint {
|
||||
remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
ipu1_csi0_mux_from_parallel_sensor: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
ipu1_csi0_mux_to_ipu1_csi0: endpoint {
|
||||
remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ipu2_csi1_mux {
|
||||
compatible = "video-mux";
|
||||
mux-controls = <&mux 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
ipu2_csi1_mux_from_mipi_vc3: endpoint {
|
||||
remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
ipu2_csi1_mux_from_parallel_sensor: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
ipu2_csi1_mux_to_ipu2_csi1: endpoint {
|
||||
remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -229,6 +421,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ipu1_csi1 {
|
||||
ipu1_csi1_from_mipi_vc1: endpoint {
|
||||
remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
||||
|
|
@ -275,6 +473,40 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mipi_csi {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_vc0_to_ipu1_csi0_mux: endpoint {
|
||||
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
mipi_vc1_to_ipu1_csi1: endpoint {
|
||||
remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
mipi_vc2_to_ipu2_csi0: endpoint {
|
||||
remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
mipi_vc3_to_ipu2_csi1_mux: endpoint {
|
||||
remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
ports {
|
||||
port@2 {
|
||||
|
|
@ -295,6 +527,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
&mux {
|
||||
mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
|
||||
<0x04 0x00100000>, /* MIPI_IPU2_MUX */
|
||||
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
|
||||
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
|
||||
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
|
||||
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
|
||||
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
|
||||
};
|
||||
|
||||
&vpu {
|
||||
compatible = "fsl,imx6q-vpu", "cnm,coda960";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,810 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Copyright 2012 Freescale Semiconductor, Inc.
|
||||
// Copyright 2011 Linaro Ltd.
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart4;
|
||||
};
|
||||
|
||||
memory@10000000 {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
user {
|
||||
label = "debug";
|
||||
gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
home {
|
||||
label = "Home";
|
||||
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_HOME>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_BACK>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
program {
|
||||
label = "Program";
|
||||
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_PROGRAM>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
codec_osc: anaclk2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_audio: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "cs42888_supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound-cs42888 {
|
||||
compatible = "fsl,imx6-sabreauto-cs42888",
|
||||
"fsl,imx-audio-cs42888";
|
||||
model = "imx-cs42888";
|
||||
audio-cpu = <&esai>;
|
||||
audio-asrc = <&asrc>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"Line Out Jack", "AOUT1L",
|
||||
"Line Out Jack", "AOUT1R",
|
||||
"Line Out Jack", "AOUT2L",
|
||||
"Line Out Jack", "AOUT2R",
|
||||
"Line Out Jack", "AOUT3L",
|
||||
"Line Out Jack", "AOUT3R",
|
||||
"Line Out Jack", "AOUT4L",
|
||||
"Line Out Jack", "AOUT4R",
|
||||
"AIN1L", "Line In Jack",
|
||||
"AIN1R", "Line In Jack",
|
||||
"AIN2L", "Line In Jack",
|
||||
"AIN2R", "Line In Jack";
|
||||
};
|
||||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif",
|
||||
"fsl,imx-sabreauto-spdif";
|
||||
model = "imx-spdif";
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-in;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2cmux {
|
||||
compatible = "i2c-mux-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3mux>;
|
||||
mux-gpios = <&gpio5 4 0>;
|
||||
i2c-parent = <&i2c3>;
|
||||
idle-state = <0>;
|
||||
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
adv7180: camera@21 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x21>;
|
||||
powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
port {
|
||||
adv7180_to_ipu1_csi0_mux: endpoint {
|
||||
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
max7310_a: gpio@30 {
|
||||
compatible = "maxim,max7310";
|
||||
reg = <0x30>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
max7310_b: gpio@32 {
|
||||
compatible = "maxim,max7310";
|
||||
reg = <0x32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_max7310>;
|
||||
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
max7310_c: gpio@34 {
|
||||
compatible = "maxim,max7310";
|
||||
reg = <0x34>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
light-sensor@44 {
|
||||
compatible = "isil,isl29023";
|
||||
reg = <0x44>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
magnetometer@e {
|
||||
compatible = "fsl,mag3110";
|
||||
reg = <0x0e>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
accelerometer@1c {
|
||||
compatible = "fsl,mma8451";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_csi0_from_ipu1_csi0_mux {
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&ipu1_csi0_mux_from_parallel_sensor {
|
||||
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&ipu1_csi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu1_csi0>;
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
|
||||
<&clks IMX6QDL_PLL4_BYPASS>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_PLL4_POST_DIV>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
|
||||
<&clks IMX6QDL_PLL4_BYPASS_SRC>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
cs-gpios = <&gpio3 19 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
|
||||
status = "disabled"; /* pin conflict with WEIM NOR */
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&esai {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esai>;
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
|
||||
<&clks IMX6QDL_CLK_ESAI_EXTAL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <0>, <24576000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,err006687-workaround-present;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hdmi_cec>;
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3b_reg: sw3b {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec: cs42888@48 {
|
||||
compatible = "cirrus,cs42888";
|
||||
reg = <0x48>;
|
||||
clocks = <&codec_osc>;
|
||||
clock-names = "mclk";
|
||||
VA-supply = <®_audio>;
|
||||
VD-supply = <®_audio>;
|
||||
VLS-supply = <®_audio>;
|
||||
VLC-supply = <®_audio>;
|
||||
};
|
||||
|
||||
touchscreen@4 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_egalax_int>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-sabreauto {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
|
||||
MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1_cs: ecspi1cs {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_egalax_int: egalax-intgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esai: esaigrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
|
||||
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
|
||||
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
|
||||
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
|
||||
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
|
||||
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
|
||||
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
|
||||
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
|
||||
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
|
||||
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpiokeysgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
|
||||
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpmi_nand: gpminandgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi_cec: hdmicecgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3mux: i2c3muxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu1_csi0: ipu1csi0grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_max7310: max7310grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpt_input_capture0: gptinputcapture0grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpt_input_capture1: gptinputcapture1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif: spdifgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_cs0: weimcs0grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_nor: weimnorgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
||||
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
||||
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
||||
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
||||
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
||||
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
||||
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
||||
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
||||
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
||||
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spdif>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&weim {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
|
||||
ranges = <0 0 0x08000000 0x08000000>;
|
||||
status = "disabled"; /* pin conflict with SPI NOR */
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
|
||||
0x0000c000 0x1404a38e 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,741 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Copyright 2012 Freescale Semiconductor, Inc.
|
||||
// Copyright 2011 Linaro Ltd.
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc1 = &usdhc3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@10000000 {
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usb_otg_vbus: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 22 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 29 0>;
|
||||
enable-active-high;
|
||||
vin-supply = <&swbst_reg>;
|
||||
};
|
||||
|
||||
reg_audio: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "wm8962-supply";
|
||||
gpio = <&gpio4 10 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_pcie: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie_reg>;
|
||||
regulator-name = "MPCIE_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 19 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_POWER>;
|
||||
};
|
||||
|
||||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6q-sabresd-wm8962",
|
||||
"fsl,imx-audio-wm8962";
|
||||
model = "wm8962-audio";
|
||||
ssi-controller = <&ssi2>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"Ext Spk", "SPKOUTL",
|
||||
"Ext Spk", "SPKOUTR",
|
||||
"AMIC", "MICBIAS",
|
||||
"IN3R", "AMIC";
|
||||
mux-int-port = <2>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
|
||||
backlight_lvds: backlight-lvds {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <7>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
red {
|
||||
gpios = <&gpio1 2 0>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "hannstar,hsd100pxn1";
|
||||
backlight = <&backlight_lvds>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipu1_csi0_from_ipu1_csi0_mux {
|
||||
bus-width = <8>;
|
||||
data-shift = <12>; /* Lines 19:12 used */
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
|
||||
&ipu1_csi0_mux_from_parallel_sensor {
|
||||
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
|
||||
};
|
||||
|
||||
&ipu1_csi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ipu1_csi0>;
|
||||
};
|
||||
|
||||
&mipi_csi {
|
||||
status = "okay";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mipi_csi2_in: endpoint {
|
||||
remote-endpoint = <&ov5640_to_mipi_csi2>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
cs-gpios = <&gpio4 9 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32", "jedec,spi-nor";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hdmi_cec>;
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
codec: wm8962@1a {
|
||||
compatible = "wlf,wm8962";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
DCVDD-supply = <®_audio>;
|
||||
DBVDD-supply = <®_audio>;
|
||||
AVDD-supply = <®_audio>;
|
||||
CPVDD-supply = <®_audio>;
|
||||
MICVDD-supply = <®_audio>;
|
||||
PLLVDD-supply = <®_audio>;
|
||||
SPKVDD1-supply = <®_audio>;
|
||||
SPKVDD2-supply = <®_audio>;
|
||||
gpio-cfg = <
|
||||
0x0000 /* 0:Default */
|
||||
0x0000 /* 1:Default */
|
||||
0x0013 /* 2:FN_DMICCLK */
|
||||
0x0000 /* 3:Default */
|
||||
0x8014 /* 4:FN_DMICCDAT */
|
||||
0x0000 /* 5:Default */
|
||||
>;
|
||||
};
|
||||
|
||||
ov5642: camera@3c {
|
||||
compatible = "ovti,ov5642";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ov5642>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
clock-names = "xclk";
|
||||
reg = <0x3c>;
|
||||
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
|
||||
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
|
||||
rev B board is VGEN5 */
|
||||
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
|
||||
powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
ov5642_to_ipu1_csi0_mux: endpoint {
|
||||
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ov5640>;
|
||||
reg = <0x3c>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO>;
|
||||
clock-names = "xclk";
|
||||
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
|
||||
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
|
||||
rev B board is VGEN5 */
|
||||
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
|
||||
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
ov5640_to_mipi_csi2: endpoint {
|
||||
remote-endpoint = <&mipi_csi2_in>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmic: pfuze100@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3b_reg: sw3b {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
egalax_ts@4 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <7 2>;
|
||||
wakeup-gpios = <&gpio6 7 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx6qdl-sabresd {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux: audmuxgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpio_keysgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi_cec: hdmicecgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu1_csi0: ipu1csi0grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
|
||||
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ov5640: ov5640grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
|
||||
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ov5642: ov5642grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
|
||||
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie_reg: pciereggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_leds {
|
||||
pinctrl_gpio_leds: gpioledsgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
|
||||
vpcie-supply = <®_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_arm {
|
||||
vin-supply = <&sw1a_reg>;
|
||||
};
|
||||
|
||||
®_pu {
|
||||
vin-supply = <&sw1c_reg>;
|
||||
};
|
||||
|
||||
®_soc {
|
||||
vin-supply = <&sw1c_reg>;
|
||||
};
|
||||
|
||||
&snvs_poweroff {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <8>;
|
||||
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
bus-width = <8>;
|
||||
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wdog2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
//
|
||||
// Copyright 2016 Freescale Semiconductor, Inc.
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6qp.dtsi"
|
||||
#include "imx6qdl-sabreauto.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
|
||||
compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
max7322: gpio@68 {
|
||||
compatible = "maxim,max7322";
|
||||
reg = <0x68>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-sabreauto {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&vgen3_reg {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
//
|
||||
// Copyright 2016 Freescale Semiconductor, Inc.
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6qp.dtsi"
|
||||
#include "imx6qdl-sabresd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
|
||||
};
|
||||
|
||||
®_arm {
|
||||
vin-supply = <&sw2_reg>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
imx6qdl-sabresd {
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
//
|
||||
// Copyright 2016 Freescale Semiconductor, Inc.
|
||||
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
ocram2: sram@940000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00940000 0x20000>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
ocram3: sram@960000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00960000 0x20000>;
|
||||
clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
||||
};
|
||||
|
||||
aips-bus@2100000 {
|
||||
pre1: pre@21c8000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021c8000 0x1000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE0>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram2>;
|
||||
};
|
||||
|
||||
pre2: pre@21c9000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021c9000 0x1000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE1>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram2>;
|
||||
};
|
||||
|
||||
pre3: pre@21ca000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021ca000 0x1000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE2>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram3>;
|
||||
};
|
||||
|
||||
pre4: pre@21cb000 {
|
||||
compatible = "fsl,imx6qp-pre";
|
||||
reg = <0x021cb000 0x1000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRE3>;
|
||||
clock-names = "axi";
|
||||
fsl,iram = <&ocram3>;
|
||||
};
|
||||
|
||||
prg1: prg@21cc000 {
|
||||
compatible = "fsl,imx6qp-prg";
|
||||
reg = <0x021cc000 0x1000>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
|
||||
<&clks IMX6QDL_CLK_PRG0_AXI>;
|
||||
clock-names = "ipg", "axi";
|
||||
fsl,pres = <&pre1>, <&pre2>, <&pre3>;
|
||||
};
|
||||
|
||||
prg2: prg@21cd000 {
|
||||
compatible = "fsl,imx6qp-prg";
|
||||
reg = <0x021cd000 0x1000>;
|
||||
clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
|
||||
<&clks IMX6QDL_CLK_PRG1_AXI>;
|
||||
clock-names = "ipg", "axi";
|
||||
fsl,pres = <&pre4>, <&pre2>, <&pre3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
/delete-property/interrupts-extended;
|
||||
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
&gpc {
|
||||
compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
|
||||
};
|
||||
|
||||
&ipu1 {
|
||||
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
|
||||
fsl,prg = <&prg1>;
|
||||
};
|
||||
|
||||
&ipu2 {
|
||||
compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
|
||||
fsl,prg = <&prg2>;
|
||||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
|
||||
<&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
|
||||
"di0", "di1";
|
||||
};
|
||||
|
||||
&mmdc0 {
|
||||
compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
|
||||
};
|
||||
Loading…
Reference in New Issue