Values imported from Linux driver, but in correct numeric order.
Khadas VIM3 prints: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
Cc: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Write SoC instead of Soc. The Linux driver is not affected.
Fixes: f41d723b9f ("ARM: meson: display Amlogic SoC Information")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
In Linux meson-g12-common.dtsi was introduced as well as new g12b nodes
and headers, as dependencies of new meson-g12b-a311d-khadas-vim3.dts.
Copied from da0c9ea146cb ("Linux 5.4-rc2")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Like the meson-gx support, add the U-Boot specific bits in DT
to support graphics on G12A SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
If VIDEO_MESON is enabled, we need to setup the fdt for the framebuffer.
Call meson_vpu_rsv_fb() which reserves the framebuffer memory region for
EFI, and sets up simple-framebuffer nodes if simplefb support is
enabled.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
The released Linux boot image header in v5.3 is different from the
one present in U-Boot. Align the header with the new version. The
changes in Linux are backward compatible. Previous U-Boot releases
with older header will continue to work as well. As v5.3 kernel is
the first one to support image header, there is no compatibility
issue between new U-Boot (with this patch) and older kernel.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.
This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra <wesley@sifive.com> and/or Atish Patra
<atish.patra@wdc.com> (many thanks !!). The linux driver can be referred
here [1]
[1]: https://lkml.org/lkml/2018/10/9/1103
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Dropping some test Elf files and building them from source instead
- Refactoring of x86 16-bit entries
- Support for SPL symbols within sections
- Handle the 'notes' sections and hidden symbols in recent binutils
- Improved error reporting with a tool fails
libfdt and documentation fixes
vboot required-key test
driver model power-domain controls
patman Message-Id enhancement
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Merge tag 'dm-pull-15oct19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
binman enhancements:
- Dropping some test Elf files and building them from source instead
- Refactoring of x86 16-bit entries
- Support for SPL symbols within sections
- Handle the 'notes' sections and hidden symbols in recent binutils
- Improved error reporting with a tool fails
libfdt and documentation fixes
vboot required-key test
driver model power-domain controls
patman Message-Id enhancement
U-Boot cannot be built for h2200_defconfig with CONFIG_DM=y.
The maintainer Lukasz Dalek suggested to remove the board.
https://lists.denx.de/pipermail/u-boot/2019-August/380685.html
Cc: Lukasz Dalek <luk0104@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
[trini: As this is the last non-toradex PXA board, update travis too]
Signed-off-by: Tom Rini <trini@konsulko.com>
Without this patch, compiling may potentially fail.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
When I tried to run some new efi tests with pytest, efi_smbios_register()
triggered a segmentation fault. Here is the location where it happened:
efi_init_obj_list()
efi_smbios_register()
write_smbios_table()
smbios_write_type4()
smbios_write_type4_dm()
where dev_get_parent_platdata() should return a pointer to struct
cpu_platdata, but it is actually NULL because any cpu device on
sandbox is attached to "root_driver."
With this patch, this issue will be fixed by moving all the definitions
of cpus under "cpus" node so that they have a "cpu_bus" parent.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present these two sections of code are linked together into a single
2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware
Interface Table) in the ROM and the pointer for this needs to go at
0xffffffc0 which is in the middle of these two sections.
Make use of the new 'reset' entry and change the existing 16-bit entry to
include just the 16-bit data.
Signed-off-by: Simon Glass <sjg@chromium.org>
-------------------
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
- logicpd pinmux
- i.MX7ULP: imx_ddr_size
- fixes Toradex i.MX6/i.MX7
- pico-imx7d
- tpc70 converted to DM
- New Board: meerkat96
- add HAB version command
- i.MX8 :
imx8: Jump from alias to OCRAM address at SPL init
imx8qm/qxp: Set SPL TEXT base to OCRAM base
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Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191014
-------------------
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
- logicpd pinmux
- i.MX7ULP: imx_ddr_size
- fixes Toradex i.MX6/i.MX7
- pico-imx7d
- tpc70 converted to DM
- New Board: meerkat96
- add HAB version command
- i.MX8 :
imx8: Jump from alias to OCRAM address at SPL init
imx8qm/qxp: Set SPL TEXT base to OCRAM base
- Add sdhci driver for Broadcom iProc platform
- Add a driver callback for power-cycle for mmc
- Implement host_power_cycle callback for stm32_sdmmc2
- spl: dm_mmc: Initialize only the required mmc device
THe RVT data includes a major and minor version in its header
parameter. Add a new command to print this out.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
i.MX7ULP uses the same MMDC controller IP as found on i.MX53
and i.MX6, so build mmdc_size.c for i.MX7ULP as well.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
The original imx_ddr_size() implementation had some
issues reported by checkpatch like this:
CHECK: Prefer kernel type 'u32' over 'uint32_t'
#127: FILE: arch/arm/mach-imx/mmdc_size.c:16:
+ uint32_t ctl;
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
#151: FILE: arch/arm/mach-imx/mmdc_size.c:40:
+ unsigned ctl = readl(&mem->ctl);
Fix all of them.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Place imx_ddr_size() into a separate file.
The motivation for doing this is to be able to easily reuse
imx_ddr_size() on i.MX7ULP.
Currently imx_ddr_size() is inside arch/arm/mach-imx/cpu.c, which
is not built for i.MX7ULP.
Changing the logic to allow building cpu.c for i.MX7UP would
require adding several ifdef's, leading to a not a very elegant
solution.
To allow better reuse, just place imx_ddr_size() into a common
mmdc_size.c file.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
The new class dsi host allows the management of the bridge DPI to DSI.
This bridge is embedded in the chipset mp1 (come from synopsys company).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
The new class dsi host allows the management of the bridge DPI to DSI.
This bridge is embedded in the chipset mp1 (come from synopsys company).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Display Serial Interface (DSI) host can usefully be modelled
as their own uclass.
DSI defines a serial bus and a communication protocol
between the host and the device (panel, bridge).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
When running SPL on iMX8, the A core starts at address 0
which is a alias to OCRAM 0x100000.
The alias only map first 96KB of OCRAM, so this require the
SPL size can't beyond 96KB. But when using SPL DM, the size increase
significantly and may exceed 96KB.
So to fix the problem, we will change SPL linker address to OCRAM
address 0x100000. And then jump to the absolute address not the PC relative
address for entering OCRAM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
This patch converts the TPC70 to use driver model and device tree
description in both SPL and u-boot proper.
Notable changes (DM/DTS conversion):
- PINCTRL{_IMX6}
- DM_I2C
- enable 'regulator' and 'pmic' commands
- DM_MMC and BLK (USDHC)
- DM_ETH
- DM WDT (including SYSRESET)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit adds new file - imx6q-kp-u-boot.dtsi with a set of u-boot
specific properties for imx6q KP device.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
With the 256KB of OCRAM available to SPL now, there should be
enough room to enable the pinmuxing in SPL from the device tree.
This patch enables SPL_PINCTRL et al and adds the serial and
usdhc pin mux references to the -u-boot.dtsi file so the pins can be
configured from the device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The Meerkat96 board, based on the NXP i.MX7D SoC, is a member of
96Boards community and complies with all Consumer Edition board
specifications.
https://www.novtech.com/products/meerkat96.htmlhttps://www.96boards.org/product/imx7-96/
The initial supported/tested devices include:
- Debug serial
- SD
- USB Host (with Ethernet)
With these support, it's good enough for loading Linux Kernel from SD or
Ethernet over USB.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
If an exception occurs in a loaded image and the relocation offset is
unknown, it is helpful to know the instructions pointed to by the
program counter. This patch adds the missing output.
A possible output is:
Code: 910c4021 aa1303e0 f9400662 d63f0040 (e7f7defb)
The parentheses indicate the instruction causing the exception.
The output can be disassembled using scripts/decodecode:
echo 'Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)' | \
ARCH=arm64 scripts/decodecode
Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)
All code
========
0: 90000360 adrp x0, 0x6c000
4: 9100b800 add x0, x0, #0x2e
8: 94002782 bl 0x9e10
c: 17ffff8f b 0xfffffffffffffe48
10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction
Code starting with the faulting instruction
===========================================
0: e7f7defb .inst 0xe7f7defb ; undefined
We already have implemented the same for armv7.
For testing command 'exception undefined' can be used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
readb is unconditionally defined earlier in io.h, so there's no point
checking whether it's undefined.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
No ARM board seems to define __mem_pci - and if it did, one would get tons of
./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined
warnings, because readl and friends are unconditionally defined
earlier in io.h. Moreover, the redefinitions lack the memory barriers
that the first definitions have. So I'm guessing this is practically
dead code.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
If there is any failure during IOdelay recalibration sequence, IOs are
not guaranteed to behave as expected. So hang on any failure during the
sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When an error is reported in __recalibrate_iodelay_start(), de-isolation
of IO doesn't happen. Because of this, undefined behaviour is observed
on many peripherals without any error. So make sure io is out of isolation
at the end of iodelay recalibration.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Main uart0 is used as debug console by both R5SPL and A72 bootloader and
Linux. So mark it as shared device so that power-domain request is
successful by both cores.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM335x-ICE boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM57xx-IDK boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
- add BOARD_LATE_INIT function calls in board.c
- add swi_status detection in board.c
- mux: add guardian interfaces to single pinmux structure
- am33xx, kconfig: add BOARD_LATE_INIT for GUARDIAN board
Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Before the priming begins, we need to disable RMW (Read Modify Write)
and disable ECC verification for read accesses. By default, the EMIF
tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
If ECC is enabled, we need to ensure interleaving is disabled for higher
address space.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr driver is assuming the register
contains the start address and size of the DDR address space. Because
of this the ecc enabling is failing for the 2nd range of ecc addresses.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This follows the linux header rules to avoid conflict bitfields.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This adds PCIe and its PHY nodes for MT7623.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This commit add a spi-nor device in the bcm96850xref device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
This commit add a hsspi controller in the bcm6858 device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
This change adds a spi nor flash device to the bcm963158 board.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
This change adds the hsspi controller to the 63158 dtsi.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. In order to view the code loaded by the U-Boot by
remote cores, U-Boot should configure the memory region with right
memory attributes. Right now U-Boot carves out a memory region which
is not sufficient for all the images to be loaded. So, increase this
carve out region by 256MB.
Signed-off-by: Kedar Chitnis <kedarc@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The A53 U-Boot code can load and boot the MCU domain R5F cores (either a
single core in LockStep mode or 2 cores in Split mode) to achieve various
early system functionalities. Change the memory attributes for the DDR
regions used by the remote processors so that the cores can see and
execute the proper code loaded by U-Boot.
These regions are currently limited to 0xa0000000 to 0xa2100000 as per
the DDR carveouts assigned for these R5F cores in the overall DDR memory
map.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor
subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster
can be configured at boot time to be either run in a LockStep mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5 cores are each added as child nodes to the corresponding
main cluster node. Configure SS0 in split mode an SS1 in lockstep mode,
with the ATCMs enabled to allow the R5 cores to execute code from DDR
with boot-strapping code from ATCM.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Although we currently use the MAIN_UART0 for R5 SPL console output there
are cases where we require access to the MCU_UART0 as well for example in
case of UART-based Y-Modem boot. To support these scenarios add related
DTS definitions to be able to use that UART early on.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
In order to allow booting TI K3 family SoCs via Y-Modem add support for
loading System Firmware by tapping into the associated SPL core loader
function.
In this context also make sure a console is available and if not go
ahead and activate the early console feature which allows bringing up
an alternate full console before the main console is activated. Such
an alternate console is typically setup in a way that the associated
UART can be fully initialized prior to SYSFW services being available.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Implement an early console functionality in SPL that can be used before
the main console is being brought up. This helps in situations where the
main console is dependent on System Firmware (SYSFW) being up and running,
which is usually not the case during the very early stages of boot. Using
this early console functionality will allow for an alternate serial port
to be used to support things like UART-based boot and early diagnostic
messages until the main console is ready to get activated.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
At present this produces a 16-byte file. It is intended to start 16 bytes
before the end of ROM and pads with zeroes to readh the end.
But binman sometimes wants to add an image-header at the very end of ROM.
Furthermore binman automatically pads the data if it is finishes early.
Drop the padding in resetvec and let binman handle it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This is not used anywhere now, so drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Since x86 users binman now, we don't need this compile-time define.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Many of the Kconfig options do not apply to FSP2. Update them to use the
FSP_VERSION1 condition instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Move the code to determine the size of a cache record into a function so
we can use it elsewhere in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present when these fail to boot there is no message, just a hang. Add a
panic so it is obvious that something when wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Pick minor changes from the downstream DT, disable MMC, add GMAC0 node
and adjust PHY skew settings for GMAC1.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
- Rename existing FSP code to fsp1
- Add fsp2 directory in preparation to support FSP 2.0
- Various x86 platform codes update
- Various bug fixes and updates in dm core, sandbox and spl
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Merge tag 'u-boot-atmel-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features and fixes for 2020.01 cycle
The feature set includes support for two new boards from Microchip AT91:
The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2
SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which
is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor,
QSPI, etc
The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the
SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio,
Camera sensor connector, etc.
The full support for sam9x60ek will come at a later time. There are
still missing bits regarding the clock support and power management
controller.
The major corrections in this pull request are:
Fixes for the SetVariable() boot service.
Device path node for NVMe drives.
Disable CONFIG_CMD_NVEDIT by default.
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Merge tag 'efi-2020-01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-01-rc1
The major corrections in this pull request are:
Fixes for the SetVariable() boot service.
Device path node for NVMe drives.
Disable CONFIG_CMD_NVEDIT by default.
Apologies to everyone whose board I broke by attempting to return
MMC1 or MMC2. I misunderstood how the MMC indexing worked.
This reverts commit 14d319b185.
Signed-off-by: Adam Ford <aford173@gmail.com>
Since convert dm_video, unused code introduced, so remove this
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.
Signed-off-by: Stefano Babic <sbabic@denx.de>
To avoid hardcoded offset when adding u-boot.cnt to flash.bin, we use
flexible offset which is calculated based on the size of the container
image generated int the first stage. And pad u-boot.cnt at 1KB
alignment.
So add code to get the offset when SPL loading u-boot.cnt.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Import i.MX8MM pin func from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Import i.MX8MM dtsi from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Because we need to get cpu freq in print_cpuinfo at very early stage,
so we need to make sure the ccm be probed.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When DM_MMC enabled, the USDHC index in U-Boot is the USDHC port.
To directly return devno, we could avoid add board specific code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Set trustzone region 0 to allow both non-secure and secure access
when trust zone is enabled. We found USB controller fails to access
DDR if the default region 0 is secure access only.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and register layout change.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then
we could not reuse imximage.cfg, so create a new one.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fix the FIT image metadata for i.MX8 to result in the intended boot
order (SPL -> ATF -> U-Boot).
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Similar to "spl_sd.cfg", this patch introduces "spl_qspi.cfg" so that
all i.MX6 based boards can use it, when they use SPL and QSPI boot
mode.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch adds the missing boot mode detection for QSPI boot on
i.MX6UL/ULL. Without it, booting with SPL from QSPI NOR does not work.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
The default CSF_SIZE defined in Kconfig is too high and SPL cannot
fit into the OCRAM in certain cases.
The CSF cannot achieve 0x2000 length when using RSA 4K key which is
the largest key size supported by HABv4.
According to AN12056 "Encrypted Boot on HABv4 and CAAM Enabled Devices"
it's recommended to pad CSF binary to 0x2000 and append DEK blob to
deploy encrypted boot images.
As the maximum DEK blob size is 0x58 we can reduce CSF_SIZE to 0x2060
which should cover both CSF and DEK blob length.
Update default_image.c and image.c to align with this change and avoid
a U-Boot proper authentication failure in HAB closed devices:
Authenticate image from DDR location 0x877fffc0...
bad magic magic=0x32 length=0x6131 version=0x38
bad length magic=0x32 length=0x6131 version=0x38
bad version magic=0x32 length=0x6131 version=0x38
spl: ERROR: image authentication fail
Fixes: 96d27fb218 (Revert "habv4: tools: Avoid hardcoded CSF size for SPL targets")
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Add support for the power domain controller that's used on the
i.MX8MQ. This will be needed to be able to power on the PCIe
controller. Bindings taken from Linux, driver implementation
taken from the i.MX8 power domain controller and adjusted for
the i.MX8M SoC.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
After this change it is possible to use imx28-<board>-u-boot.dtsi with
the imx28-u-boot.dtsi explicitly included without breaking setup from
imx28-<board>.dts file.
The problem is that the imx28.dtsi included in a wrong place overrides the
changes made in imx28-<board>.dts. As a result some devices are "disabled"
in the final DTB.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change tries to fix the following problem:
- The board boots (to be more precise - ROM loads SPL) from a slow SPI-NOR
memory.
As a result the spl_boot_device() will return SPI-NOR as a boot device
(which is correct).
- The problem is that in 'falcon boot' the eMMC is used as a boot medium to
load kernel from its partition.
Calling spl_boot_device() will break things as it returns SPI-NOR device.
To fix this issue the new CONFIG_SPL_FORCE_MMC_BOOT Kconfig flag is
introduced to handle this special use case. By default it is not defined,
so there is no change in the legacy code flow.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit enables support for CONFIG_WDT in the U-Boot proper. Moreover,
the SYSRESET_WATCHDOG driver is used to support 'reset' command.
As SPL is not yet ready for DM conversion, the CONFIG_HW_WATCHDOG is
enabled for it. This allows the legacy SPL code to work properly.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The DM/DTS support for SPI is disabled on purpose for SPL, as it is not
supported as of time of this conversion.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After this commit the display5 device would use I2C driver supporting
driver model (DM_I2C).
The 'i2c' and 'eeprom' commands now use DM I2C drivers and initialize
on-bus devices according to device tree description.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add the initial support for the pico-imx6 variants.
DDR initialization is based on the TechNexion's U-Boot code.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Allow enable_ipu_clock() to be built for SPL code. This is done
in preparation for configuring the NoC registers on i.MX6QP in SPL.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Add sc_pm_is_partition_started to check whether a partition
has been started. This will be used to detect M4 partition booted up or
not, then we could choose which dtb to use. If M4 is up, we need
use dtb, such as imx8qm-mek-rpmsg.dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add OP-TEE device tree node for Linux according to args passed from ATF.
If ATF has been built with OP-TEE running, boot_pointer[1] will indicate
that.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX8QM, sid is programmable, so we could program sid according the
value encoded in device tree.
This patch support legacy bindings which are still being used by XEN
and new bindings used by Linux Kernel.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When resource is not assigned to non-secure Linux, if linux continue
to use the node, linux may crash or hang. So need to set the node
status to disabled for not owned resources.
The resource id is in the power-domains property in device tree,
so parse the power-domains property to get the resource id and
use scfw api to check whether it is owned by current partition.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Since SCU MU driver has been bound in dm_init, so we don't need to
bind it again. Just replace by using uclass function to probe it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
To support SPL loading container file, add a new Makefile target,
and introduce a new Kconfig file to source the cfg file which
will be parsed by mkimage.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add parsing i.MX8 Container file support, this is to let
SPL could load images in a container file to destination address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The changes were added by following patch:
commit <9002e735e717> ("imx: mx6sabresd: fix boot hang with video")
commit <f45ec8fcfb86> ("imx6: dts: add 'u-boot, dm-pre-reloc' to soc and ipu nodes")
Let's move the U-Boot specific change to imx6qdl-u-boot.dtsi
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move CONFIG_CSF_SIZE to Kconfig and define default value as 0x4000.
mx8mqevk requires 0x2000 add this configuration in imx8mq_evk_defconfig
file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
The normal target frequency for ULP A7 core is 500Mhz, but now ROM
set the core frequency to 413Mhz. So change it to 500Mhz in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
