Add i.MX7D based Meerkat96 board support
The Meerkat96 board, based on the NXP i.MX7D SoC, is a member of 96Boards community and complies with all Consumer Edition board specifications. https://www.novtech.com/products/meerkat96.html https://www.96boards.org/product/imx7-96/ The initial supported/tested devices include: - Debug serial - SD - USB Host (with Ethernet) With these support, it's good enough for loading Linux Kernel from SD or Ethernet over USB. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Shawn Guo
Stefano Babic
parent
ad61658dd6
commit
6802d7951c
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@ -28,6 +28,15 @@ config TARGET_CL_SOM_IMX7
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select SUPPORT_SPL
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imply CMD_DM
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config TARGET_MEERKAT96
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bool "NovTech Meerkat96 board"
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select BOARD_LATE_INIT
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select DM
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select DM_SERIAL
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select DM_THERMAL
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select MX7D
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imply CMD_DM
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config TARGET_MX7DSABRESD
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bool "mx7dsabresd"
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select BOARD_LATE_INIT
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@ -67,6 +76,7 @@ config SYS_SOC
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source "board/compulab/cl-som-imx7/Kconfig"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/novtech/meerkat96/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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@ -0,0 +1,12 @@
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if TARGET_MEERKAT96
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config SYS_BOARD
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default "meerkat96"
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config SYS_VENDOR
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default "novtech"
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config SYS_CONFIG_NAME
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default "meerkat96"
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endif
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@ -0,0 +1,6 @@
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MEERKAT96 BOARD
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M: Shawn Guo <shawn.guo@kernel.org>
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S: Maintained
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F: board/novtech/meerkat96
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F: include/configs/meerkat96.h
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F: configs/meerkat96_defconfig
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@ -0,0 +1 @@
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obj-y := meerkat96.o
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@ -0,0 +1,18 @@
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* Build U-Boot for Meerkat96 board
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$ make mrproper
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$ make meerkat96_defconfig
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$ make
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It will generate the U-Boot binary called u-boot-dtb.imx
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* Install U-Boot to MicroSD card
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Plug MicroSD card to a Linux machine (with card reader), find the
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device name and replace sd[x] with the name in the following command.
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$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=512 seek=2
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It will install U-Boot to MicroSD card at 1KiB offset. Insert the
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card to Meerkat96 MicroSD slot, power up the board, and U-Boot should
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boot from the card.
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@ -0,0 +1,127 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : sd
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*/
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BOOT_FROM sd
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/*
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* Secure boot support
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*/
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable OCRAM EPDC */
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DATA 4 0x30340004 0x4F400005
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/* =============================================================================
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* DDR Controller Registers
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* =============================================================================
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* Memory type: DDR3
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* Manufacturer: ISSI
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* Device Part Number: IS43TR16256AL-125KBL
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* Clock Freq.: 533MHz
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* Density per CS in Gb: 4
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* Chip Selects used: 1
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* Number of Banks: 8
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* Row address: 15
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* Column address: 10
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* Data bus width: 16
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* ROW-BANK interleave: ENABLED
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* =============================================================================
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*/
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DATA 4 0x30391000 0x00000002 // deassert presetn
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DATA 4 0x307A0000 0x01041001 // DDRC_MSTR
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DATA 4 0x307A0064 0x00400046 // DDRC_RFSHTMG
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DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
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DATA 4 0x307A00D4 0x00690000 // DDRC_INIT1
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DATA 4 0x307A00D0 0x00020083 // DDRC_INIT0
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DATA 4 0x307A00DC 0x09300004 // DDRC_INIT3
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DATA 4 0x307A00E0 0x04080000 // DDRC_INIT4
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DATA 4 0x307A00E4 0x00100004 // DDRC_INIT5
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DATA 4 0x307A00F4 0x0000033F // DDRC_RANKCTL
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DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
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DATA 4 0x307A0104 0x0007020D // DDRC_DRAMTMG1
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DATA 4 0x307A0108 0x03040407 // DDRC_DRAMTMG2
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DATA 4 0x307A010C 0x00002006 // DDRC_DRAMTMG3
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DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
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DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
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DATA 4 0x307A0120 0x00000803 // DDRC_DRAMTMG8
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DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
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DATA 4 0x307A0190 0x02098204 // DDRC_DFITMG0
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DATA 4 0x307A0194 0x00030303 // DDRC_DFITMG1
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DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
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DATA 4 0x307A01A4 0x00100020 // DDRC_DFIUPD1
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DATA 4 0x307A01A8 0x80100004 // DDRC_DFIUPD2
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DATA 4 0x307A0200 0x00000015 // DDRC_ADDRMAP0
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DATA 4 0x307A0204 0x00070707 // DDRC_ADDRMAP1
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DATA 4 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
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DATA 4 0x307A0214 0x06060606 // DDRC_ADDRMAP5
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DATA 4 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
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DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
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DATA 4 0x307A0244 0x00000001 // DDRC_ODTMAP
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/* =============================================================================
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* PHY Control Register
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* =============================================================================
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*/
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DATA 4 0x30391000 0x00000000 // deassert presetn
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DATA 4 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
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DATA 4 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
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DATA 4 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
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DATA 4 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
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DATA 4 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
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DATA 4 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
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DATA 4 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
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DATA 4 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
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DATA 4 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
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DATA 4 0x30790018 0x0000000F // DDR_PHY_LP_CON0
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DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
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DATA 4 0x307900C0 0x0E447304
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DATA 4 0x307900C0 0x0E447306
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DATA 4 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
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DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
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/* =============================================================================
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* Final Initialization start sequence
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* =============================================================================
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*/
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DATA 4 0x30384130 0x00000000 // Disable Clock
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DATA 4 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
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DATA 4 0x30384130 0x00000002 // Enable Clock
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/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
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@ -0,0 +1,71 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Linaro Ltd.
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* Copyright (C) 2016 NXP Semiconductors
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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static iomux_v3_cfg_t const meerkat96_pads[] = {
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/* UART6 as debug serial */
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MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_SD1_WP__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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/* WDOG1 for reset */
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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int board_early_init_f(void)
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{
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imx_iomux_v3_setup_multiple_pads(meerkat96_pads,
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ARRAY_SIZE(meerkat96_pads));
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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char *mode;
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if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
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mode = "secure";
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else
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mode = "non-secure";
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printf("Board: i.MX7D Meerkat96 in %s mode\n", mode);
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return 0;
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}
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int board_late_init(void)
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{
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set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
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return 0;
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}
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@ -0,0 +1,52 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX7=y
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CONFIG_SYS_TEXT_BASE=0x87800000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_TARGET_MEERKAT96=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
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# CONFIG_ARMV7_VIRT is not set
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CONFIG_IMX_RDC=y
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CONFIG_IMX_BOOTAUX=y
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/novtech/meerkat96/imximage.cfg"
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_HUSH_PARSER=y
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# CONFIG_CMD_BOOTD is not set
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PART=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96"
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM_GPIO=y
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CONFIG_MMC_BROKEN_CD=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX7=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_MXC_USB_OTG_HACTIVE=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_ASIX88179=y
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CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_RTL8152=y
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CONFIG_USB_ETHER_SMSC95XX=y
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 Linaro Ltd.
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* Copyright (C) 2016 NXP Semiconductors
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*
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* Configuration settings for Meerkat96 board.
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*/
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#ifndef __MEERKAT96_CONFIG_H
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#define __MEERKAT96_CONFIG_H
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#include "mx7_common.h"
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#include <imximage.h>
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#define PHYS_SDRAM_SIZE SZ_512M
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Environment configs */
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 0
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#define CONFIG_ENV_SIZE SZ_8K
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#define CONFIG_ENV_OFFSET (8 * SZ_64K)
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/* USB configs */
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#endif
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