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u-boot-imx-20191014

Browse Source 
-------------------
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
 
 	- logicpd pinmux
 	- i.MX7ULP: imx_ddr_size
 	- fixes Toradex i.MX6/i.MX7
 	- pico-imx7d
 	- tpc70 converted to DM
 	- New Board: meerkat96
 	- add HAB version command
 	- i.MX8 :
       		imx8: Jump from alias to OCRAM address at SPL init
       		imx8qm/qxp: Set SPL TEXT base to OCRAM base
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Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191014
-------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628

	- logicpd pinmux
	- i.MX7ULP: imx_ddr_size
	- fixes Toradex i.MX6/i.MX7
	- pico-imx7d
	- tpc70 converted to DM
	- New Board: meerkat96
	- add HAB version command
	- i.MX8 :
      		imx8: Jump from alias to OCRAM address at SPL init
      		imx8qm/qxp: Set SPL TEXT base to OCRAM base
This commit is contained in:
Tom Rini 2019-10-14 13:00:51 -04:00
commit 6f1f28b8e1
49 changed files with 1270 additions and 665 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
View File

@ -1260,6 +1260,7 @@ endif
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
else

1
arch/arm/Kconfig
View File

@ -788,6 +788,7 @@ config ARCH_IMX8
select ARM64
select DM
select OF_CONTROL
select ENABLE_ARM_SOC_BOOT0_HOOK
config ARCH_IMX8M
bool "NXP i.MX8M platform"

2
arch/arm/dts/Makefile
View File

@ -580,6 +580,7 @@ dtb-y += \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
imx6q-nitrogen6x.dtb \
imx6q-novena.dtb \
@ -633,6 +634,7 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7-colibri-emmc.dtb \
imx7-colibri-rawnand.dtb \
imx7s-warp.dtb \
imx7d-meerkat96.dtb \
imx7d-pico-pi.dtb \
imx7d-pico-hobbit.dtb

59
arch/arm/dts/imx6q-kp-u-boot.dtsi Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
#include "imx6qdl-u-boot.dtsi"
/ {
clocks {
u-boot,dm-spl;
osc {
u-boot,dm-spl;
};
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
};
&clks {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc4 {
u-boot,dm-spl;
};
&uart1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc4 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

219
arch/arm/dts/imx6q-kp.dts Normal file
View File

@ -0,0 +1,219 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6q.dtsi"
/ {
model = "K+P iMX6Q";
compatible = "kp,imx6-kp", "fsl,imx6";
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc4;
usb1 = &usbh1;
};
chosen {
stdout-path = &uart1;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
green {
label = "green";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "off";
};
red {
label = "red";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "off";
};
};
memory@10000000 {
reg = <0x10000000 0x40000000>;
};
reg_usb_h1_vbus: regulator-usb_h1_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-mode = "rgmii";
fsl,magic-packet;
fsl,enet-loopback-clk; /* anatop reference clk via PAD loopback */
fsl,enet-freq = <1>; /* ENET_25MHZ = 0, ENET_50MHZ = 1 */
/* ENET_100MHZ = 2, ENET_125MHZ = 3 */
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
>;
};
pinctrl_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b0
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17019
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10019
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17019
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17019
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17019
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17019
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x20000
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x20000
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17019
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10019
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17019
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17019
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17019
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17019
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17019
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17019
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17019
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17019
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};

12
arch/arm/dts/imx6q-logicpd-u-boot.dtsi
View File

@ -16,3 +16,15 @@
&usdhc2 {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};
&pinctrl_usdhc1 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};

3
arch/arm/dts/imx6q-tbs2910.dts
View File

@ -24,6 +24,7 @@
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
};
@ -104,7 +105,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
};

375
arch/arm/dts/imx7d-meerkat96.dts Normal file
View File

@ -0,0 +1,375 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Linaro Ltd.
*/
/dts-v1/;
#include "imx7d.dtsi"
/ {
model = "96Boards Meerkat96 Board";
compatible = "novtech,imx7d-meerkat96", "fsl,imx7d";
chosen {
stdout-path = &uart6;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MB */
};
reg_wlreg_on: regulator-wlreg-on {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlreg_on>;
regulator-name = "wlreg_on";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100>;
gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "green:user1";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led2 {
label = "green:user2";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led3 {
label = "green:user3";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc1";
default-state = "off";
};
led4 {
label = "green:user4";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "off";
panic-indicator;
};
led5 {
label = "yellow:wlan";
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
led6 {
label = "blue:bt";
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
default-state = "off";
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
uart-has-rtscts;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>;
assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
uart-has-rtscts;
fsl,dte-mode;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>;
};
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
keep-power-in-suspend;
fsl,tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
no-1-8-v;
broken-cd;
status = "okay";
};
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
no-1-8-v;
no-mmc;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_wlreg_on>;
vqmmc-supply =<&reg_3p3v>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan_irq>;
interrupt-parent = <&gpio6>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&iomuxc {
pinctrl_bt_gpios: btgpiosgrp {
fsl,pins = <
MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59
MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f
MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
MX7D_PAD_LCD_RESET__LCD_RESET 0x79
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79
MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79
MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79
MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79
MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79
MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79
MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79
MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x0D
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
>;
};
pinctrl_wlan_irq: wlanirqgrp {
fsl,pins = <
MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19
>;
};
pinctrl_wlreg_on: wlregongrp {
fsl,pins = <
MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19
>;
};
};

21
arch/arm/include/asm/arch-imx8/boot0.h Normal file
View File

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#if defined(CONFIG_SPL_BUILD)
/*
* We use absolute address not PC relative address to jump.
* When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000,
* our linker address for SPL is from 0x100000. So using absolute address can jump to
* the OCRAM address from the alias.
* The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB.
* But when using SPL DM, the size increase significantly and may exceed 96KB.
* That's why we have to jump to OCRAM.
*/
ldr x0, =reset
br x0
#else
b reset
#endif

1
arch/arm/include/asm/mach-imx/hab.h
View File

@ -189,6 +189,7 @@ typedef void hapi_clock_init_t(void);
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
#define HAB_TAG_RVT 0xDD /* ROM Vector Table */
#define HAB_CMD_HDR 0xD4 /* CSF Header */
#define HAB_CMD_WRT_DAT 0xCC /* Write Data command tag */
#define HAB_CMD_CHK_DAT 0xCF /* Check Data command tag */

5
arch/arm/mach-imx/Makefile
View File

@ -21,6 +21,9 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += cpu.o speed.o
ifneq ($(CONFIG_MX51),y)
obj-y += mmdc_size.o
endif
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
@ -48,7 +51,7 @@ obj-$(CONFIG_IMX_HAB) += hab.o
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7ulp))
obj-y += cache.o
obj-y += cache.o mmdc_size.o
obj-$(CONFIG_IMX_HAB) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))

53
arch/arm/mach-imx/cpu.c
View File

@ -87,59 +87,6 @@ static char *get_reset_cause(void)
}
#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#else
#define MEMCTL_BASE MMDC_P0_BASE_ADDR
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};
/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
uint32_t ctl;
uint32_t pdc;
uint32_t otc;
uint32_t cfg0;
uint32_t cfg1;
uint32_t cfg2;
uint32_t misc;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
/*
* imx_ddr_size - return size in bytes of DRAM according MMDC config
* The MMDC MDCTL register holds the number of bits for row, col, and data
* width and the MMDC MDMISC register holds the number of banks. Combine
* all these bits to determine the meme size the MMDC has been configured for
*/
unsigned imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
unsigned ctl = readl(&mem->ctl);
unsigned misc = readl(&mem->misc);
int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
bits += ESD_MMDC_CTL_GET_ROW(ctl);
bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
bits += ESD_MMDC_CTL_GET_CS1(ctl);
/* The MX6 can do only 3840 MiB of DRAM */
if (bits == 32)
return 0xf0000000;
return 1 << bits;
}
#endif
#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
const char *get_imx_type(u32 imxtype)

21
arch/arm/mach-imx/hab.c
View File

@ -365,6 +365,21 @@ static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc,
return 0;
}
static int do_hab_version(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
struct hab_hdr *hdr = (struct hab_hdr *)HAB_RVT_BASE;
if (hdr->tag != HAB_TAG_RVT) {
printf("Unexpected header tag: %x\n", hdr->tag);
return CMD_RET_FAILURE;
}
printf("HAB version: %d.%d\n", hdr->par >> 4, hdr->par & 0xf);
return 0;
}
static int do_authenticate_image_or_failover(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
@ -421,6 +436,12 @@ U_BOOT_CMD(
"ivt_offset - hex offset of IVT in the image"
);
U_BOOT_CMD(
hab_version, 1, 0, do_hab_version,
"print HAB major/minor version",
""
);
#endif /* !defined(CONFIG_SPL_BUILD) */
/* Get CSF Header length */

57
arch/arm/mach-imx/mmdc_size.c Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#elif defined(CONFIG_MX6)
#define MEMCTL_BASE MMDC_P0_BASE_ADDR
#elif defined(CONFIG_MX7ULP)
#define MEMCTL_BASE MMDC0_RBASE
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};
/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
u32 ctl;
u32 pdc;
u32 otc;
u32 cfg0;
u32 cfg1;
u32 cfg2;
u32 misc;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
/*
* imx_ddr_size - return size in bytes of DRAM according MMDC config
* The MMDC MDCTL register holds the number of bits for row, col, and data
* width and the MMDC MDMISC register holds the number of banks. Combine
* all these bits to determine the meme size the MMDC has been configured for
*/
unsigned int imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
unsigned int ctl = readl(&mem->ctl);
unsigned int misc = readl(&mem->misc);
int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
bits += ESD_MMDC_CTL_GET_ROW(ctl);
bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
bits += ESD_MMDC_CTL_GET_CS1(ctl);
/* The MX6 can do only 3840 MiB of DRAM */
if (bits == 32)
return 0xf0000000;
return 1 << bits;
}

10
arch/arm/mach-imx/mx6/Kconfig
View File

@ -510,9 +510,19 @@ config TARGET_KP_IMX6Q_TPC
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select SPL_DM if SPL
select DM_THERMAL
select DM_MMC
select DM_ETH
select DM_REGULATOR
select SPL_DM_REGULATOR if SPL
select DM_SERIAL
select DM_I2C
select DM_GPIO
select DM_USB
select MX6QDL
select SUPPORT_SPL
select SPL_SEPARATE_BSS if SPL
imply CMD_DM
imply CMD_SPL

10
arch/arm/mach-imx/mx7/Kconfig
View File

@ -28,6 +28,15 @@ config TARGET_CL_SOM_IMX7
select SUPPORT_SPL
imply CMD_DM
config TARGET_MEERKAT96
bool "NovTech Meerkat96 board"
select BOARD_LATE_INIT
select DM
select DM_SERIAL
select DM_THERMAL
select MX7D
imply CMD_DM
config TARGET_MX7DSABRESD
bool "mx7dsabresd"
select BOARD_LATE_INIT
@ -67,6 +76,7 @@ config SYS_SOC
source "board/compulab/cl-som-imx7/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/novtech/meerkat96/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"

5
board/freescale/imx8mm_evk/imx8mm_evk.c
View File

@ -19,6 +19,11 @@ int board_init(void)
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

2
board/freescale/mx7ulp_evk/mx7ulp_evk.c
View File

@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
gd->ram_size = imx_ddr_size();
return 0;
}

172
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
View File

@ -9,64 +9,18 @@
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <env.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c.h>
#include <miiphy.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include <led.h>
DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define I2C_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -83,56 +37,17 @@ int overwrite_console(void)
}
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8031 PHY Reset */
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void eth_phy_reset(void)
{
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
udelay(100);
}
static int setup_fec_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set gpr1[21] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK,
IOMUXC_GPR1_ENET_CLK_SEL_MASK);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int board_eth_init(bd_t *bis)
{
SETUP_IOMUX_PADS(enet_pads);
setup_fec_clock();
eth_phy_reset();
return cpu_eth_init(bis);
}
static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
@ -167,53 +82,6 @@ int board_phy_config(struct phy_device *phydev)
}
#endif
#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{ USDHC2_BASE_ADDR },
{ USDHC4_BASE_ADDR },
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
return !gpio_get_value(USDHC2_CD_GPIO);
case USDHC4_BASE_ADDR:
return 1; /* eMMC/uSDHC4 is always present */
}
return 0;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 micro SD
* mmc2 eMMC
*/
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
@ -223,30 +91,6 @@ static void setup_usb(void)
*/
imx_iomux_set_gpr_register(1, 13, 1, 0);
}
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return USB_INIT_DEVICE;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
break;
case 1:
gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return -EINVAL;
}
return 0;
}
#endif
int board_early_init_f(void)
@ -255,6 +99,10 @@ int board_early_init_f(void)
setup_usb();
#endif
#ifdef CONFIG_FEC_MXC
setup_fec_clock();
#endif
return 0;
}
@ -268,9 +116,6 @@ int board_init(void)
/* Enable eim_slow clocks */
setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
return 0;
}
@ -290,6 +135,9 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
if (IS_ENABLED(CONFIG_LED))
led_default_state();
env_set("boardname", "kp-tpc");
env_set("boardsoc", "imx6q");
return 0;

137
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
View File

@ -9,30 +9,12 @@
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <errno.h>
#include <fuse.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
#define UART_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL \
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
DECLARE_GLOBAL_DATA_PTR;
static void ccgr_init(void)
@ -48,60 +30,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
/* onboard microSD */
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/* eMMC */
static iomux_v3_cfg_t const usdhc4_pads[] = {
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* SD */
static void setup_iomux_sd(void)
{
SETUP_IOMUX_PADS(usdhc2_pads);
SETUP_IOMUX_PADS(usdhc4_pads);
}
/* UART */
static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
}
/* USB */
static iomux_v3_cfg_t const usb_pads[] = {
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_iomux_usb(void)
{
SETUP_IOMUX_PADS(usb_pads);
}
/* DDR3 */
static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdclk_0 = 0x00000030,
@ -255,57 +183,24 @@ static void spl_dram_init(void)
#endif
}
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC2_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
int board_mmc_getcd(struct mmc *mmc)
void board_boot_order(u32 *spl_boot_list)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
u32 boot_device = spl_boot_device();
u32 reg = imx6_src_get_boot_mode();
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
return ret;
}
debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
if (boot_device == BOOT_DEVICE_MMC1)
if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
boot_device = BOOT_DEVICE_MMC2;
int board_mmc_init(bd_t *bd)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int reg = readl(&psrc->sbmr1) >> 11;
spl_boot_list[0] = boot_device;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1
* 0x3 SD4
* Below boot device is a 'fallback' - it shall always be possible to
* boot from SD card
*/
switch (reg & 0x3) {
case 0x1:
SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x3:
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
}
return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}
void board_init_f(ulong dummy)
@ -319,9 +214,8 @@ void board_init_f(ulong dummy)
/* setup GP timer */
timer_init();
setup_iomux_sd();
setup_iomux_uart();
setup_iomux_usb();
/* Early - pre reloc - driver model setup */
spl_early_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
@ -331,7 +225,4 @@ void board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

85
board/logicpd/imx6/imx6logic.c
View File

@ -42,32 +42,6 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
@ -135,7 +109,6 @@ int overwrite_console(void)
int board_early_init_f(void)
{
setup_iomux_uart();
setup_nand_pins();
return 0;
}
@ -177,36 +150,6 @@ int spl_start_uboot(void)
}
#endif
/* SD interface */
#define USDHC_PAD_CTRL \
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC1_BASE_ADDR}, /* SOM */
{USDHC2_BASE_ADDR} /* Baseboard */
};
void board_boot_order(u32 *spl_boot_list)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
@ -236,34 +179,6 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[2] = BOOT_DEVICE_BOARD;
}
int board_mmc_init(bd_t *bis)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1-SOM
* 0x2 SD2-Baseboard
*/
reg &= 0x3; /* Only care about bottom 2 bits */
switch (reg) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
break;
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
break;
}
return 0;
}
#endif
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

12
board/novtech/meerkat96/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_MEERKAT96
config SYS_BOARD
default "meerkat96"
config SYS_VENDOR
default "novtech"
config SYS_CONFIG_NAME
default "meerkat96"
endif

6
board/novtech/meerkat96/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
MEERKAT96 BOARD
M: Shawn Guo <shawn.guo@kernel.org>
S: Maintained
F: board/novtech/meerkat96
F: include/configs/meerkat96.h
F: configs/meerkat96_defconfig

1
board/novtech/meerkat96/Makefile Normal file
View File

@ -0,0 +1 @@
obj-y := meerkat96.o

18
board/novtech/meerkat96/README Normal file
View File

@ -0,0 +1,18 @@
* Build U-Boot for Meerkat96 board
$ make mrproper
$ make meerkat96_defconfig
$ make
It will generate the U-Boot binary called u-boot-dtb.imx
* Install U-Boot to MicroSD card
Plug MicroSD card to a Linux machine (with card reader), find the
device name and replace sd[x] with the name in the following command.
$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=512 seek=2
It will install U-Boot to MicroSD card at 1KiB offset. Insert the
card to Meerkat96 MicroSD slot, power up the board, and U-Boot should
boot from the card.

127
board/novtech/meerkat96/imximage.cfg Normal file
View File

@ -0,0 +1,127 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : sd
*/
BOOT_FROM sd
/*
* Secure boot support
*/
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable OCRAM EPDC */
DATA 4 0x30340004 0x4F400005
/* =============================================================================
* DDR Controller Registers
* =============================================================================
* Memory type: DDR3
* Manufacturer: ISSI
* Device Part Number: IS43TR16256AL-125KBL
* Clock Freq.: 533MHz
* Density per CS in Gb: 4
* Chip Selects used: 1
* Number of Banks: 8
* Row address: 15
* Column address: 10
* Data bus width: 16
* ROW-BANK interleave: ENABLED
* =============================================================================
*/
DATA 4 0x30391000 0x00000002 // deassert presetn
DATA 4 0x307A0000 0x01041001 // DDRC_MSTR
DATA 4 0x307A0064 0x00400046 // DDRC_RFSHTMG
DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
DATA 4 0x307A00D4 0x00690000 // DDRC_INIT1
DATA 4 0x307A00D0 0x00020083 // DDRC_INIT0
DATA 4 0x307A00DC 0x09300004 // DDRC_INIT3
DATA 4 0x307A00E0 0x04080000 // DDRC_INIT4
DATA 4 0x307A00E4 0x00100004 // DDRC_INIT5
DATA 4 0x307A00F4 0x0000033F // DDRC_RANKCTL
DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
DATA 4 0x307A0104 0x0007020D // DDRC_DRAMTMG1
DATA 4 0x307A0108 0x03040407 // DDRC_DRAMTMG2
DATA 4 0x307A010C 0x00002006 // DDRC_DRAMTMG3
DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
DATA 4 0x307A0120 0x00000803 // DDRC_DRAMTMG8
DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
DATA 4 0x307A0190 0x02098204 // DDRC_DFITMG0
DATA 4 0x307A0194 0x00030303 // DDRC_DFITMG1
DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
DATA 4 0x307A01A4 0x00100020 // DDRC_DFIUPD1
DATA 4 0x307A01A8 0x80100004 // DDRC_DFIUPD2
DATA 4 0x307A0200 0x00000015 // DDRC_ADDRMAP0
DATA 4 0x307A0204 0x00070707 // DDRC_ADDRMAP1
DATA 4 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
DATA 4 0x307A0214 0x06060606 // DDRC_ADDRMAP5
DATA 4 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
DATA 4 0x307A0244 0x00000001 // DDRC_ODTMAP
/* =============================================================================
* PHY Control Register
* =============================================================================
*/
DATA 4 0x30391000 0x00000000 // deassert presetn
DATA 4 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
DATA 4 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
DATA 4 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
DATA 4 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
DATA 4 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
DATA 4 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
DATA 4 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
DATA 4 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790018 0x0000000F // DDR_PHY_LP_CON0
DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
DATA 4 0x307900C0 0x0E447304
DATA 4 0x307900C0 0x0E447306
DATA 4 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
/* =============================================================================
* Final Initialization start sequence
* =============================================================================
*/
DATA 4 0x30384130 0x00000000 // Disable Clock
DATA 4 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
DATA 4 0x30384130 0x00000002 // Enable Clock
/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */

71
board/novtech/meerkat96/meerkat96.c Normal file
View File

@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2016 NXP Semiconductors
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
static iomux_v3_cfg_t const meerkat96_pads[] = {
/* UART6 as debug serial */
MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_SD1_WP__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/* WDOG1 for reset */
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(meerkat96_pads,
ARRAY_SIZE(meerkat96_pads));
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int checkboard(void)
{
char *mode;
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
mode = "secure";
else
mode = "non-secure";
printf("Board: i.MX7D Meerkat96 in %s mode\n", mode);
return 0;
}
int board_late_init(void)
{
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
return 0;
}

92
board/tbs/tbs2910/tbs2910.c
View File

@ -14,25 +14,16 @@
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_SLOW)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
@ -43,55 +34,12 @@ static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8035 PHY Reset */
MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const pcie_pads[] = {
/* W_DISABLE# */
MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
/* PERST# */
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int dram_init(void)
{
gd->ram_size = 2048ul * 1024 * 1024;
return 0;
}
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset AR8035 PHY */
gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
static void setup_pcie(void)
{
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@ -200,46 +148,6 @@ static void setup_display(void)
}
#endif /* CONFIG_VIDEO_IPUV3 */
static int ar8035_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
/* introduce tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
val |= 0x0100;
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
ar8035_phy_fixup(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
setup_pcie();
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
setup_iomux_uart();

4
board/toradex/colibri_imx7/colibri_imx7.c
View File

@ -274,7 +274,7 @@ int power_init_board(void)
int ret;
ret = pmic_get("rn5t567", &dev);
ret = pmic_get("rn5t567@33", &dev);
if (ret)
return ret;
ver = pmic_reg_read(dev, RN5T567_LSIVER);
@ -308,7 +308,7 @@ void reset_cpu(ulong addr)
{
struct udevice *dev;
pmic_get("rn5t567", &dev);
pmic_get("rn5t567@33", &dev);
/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
pmic_reg_write(dev, RN5T567_REPCNT, 0x1);

2
configs/imx6q_logic_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_MX6LOGICPD=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
@ -77,6 +78,7 @@ CONFIG_PHY_ATHEROS=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y

4
configs/imx6qdl_icore_mmc_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_DEBUG_UART_BASE=0x021f0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_CMD_NANDBCB=y
CONFIG_DEBUG_UART=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_FIT=y
@ -58,6 +59,9 @@ CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_NAND=y
CONFIG_NAND_MXS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),8m(kernel),1m(dtb),-(rootfs)"
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y

1
configs/imx8qm_mek_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y

1
configs/imx8qxp_mek_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y

30
configs/kp_imx6q_tpc_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2200
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KP_IMX6Q_TPC=y
CONFIG_SPL_MMC_SUPPORT=y
@ -14,11 +15,14 @@ CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="."
@ -33,14 +37,38 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-kp"
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents interrupts dmas dma-names"
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLOCK_CACHE is not set
CONFIG_SPL_CLK_IMX6Q=y
CONFIG_CLK_IMX6Q=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_OF_LIBFDT=y

52
configs/meerkat96_defconfig Normal file
View File

@ -0,0 +1,52 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_MEERKAT96=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/novtech/meerkat96/imximage.cfg"
CONFIG_BOUNCE_BUFFER=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-meerkat96"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_MMC_BROKEN_CD=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y

1
configs/pico-imx7d_bl33_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y

7
configs/tbs2910_defconfig
View File

@ -9,7 +9,7 @@ CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_PREBOOT="echo PCI:; pci enum; pci 1; usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
@ -52,8 +52,13 @@ CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
# CONFIG_PCI_PNP is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_RTC=y

11
drivers/i2c/imx_lpi2c.c
View File

@ -471,6 +471,17 @@ static int imx_lpi2c_probe(struct udevice *bus)
dev_err(bus, "Failed to enable per clk\n");
return ret;
}
ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
if (ret) {
dev_err(bus, "Failed to get ipg clk\n");
return ret;
}
ret = clk_enable(&i2c_bus->ipg_clk);
if (ret) {
dev_err(bus, "Failed to enable ipg clk\n");
return ret;
}
} else {
/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
ret = enable_i2c_clk(1, bus->seq);

19
include/configs/apalis_imx6.h
View File

@ -158,24 +158,6 @@
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define SD_BOOTCMD \
"set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} ro,noatime " \
"rootfstype=ext4 rootwait\0" \
"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card; " \
"run sddtbload; load mmc ${sddev}:${sdbootpart} " \
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
"sdbootpart=1\0" \
"sddev=1\0" \
"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
"${fdt_addr_r} " \
"${fdt_file} && setenv dtbparam \" - " \
"${fdt_addr_r}\" && true\0" \
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
#define FDT_FILE "imx6q-apalis-eval.dtb"
#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
@ -196,7 +178,6 @@
"fdt_fixup=;\0" \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \

14
include/configs/colibri-imx6ull.h
View File

@ -56,19 +56,6 @@
"tftp ${fdt_addr_r} " FDT_FILE " && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define SD_BOOTCMD \
"set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \
"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} " \
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
"load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " FDT_FILE " && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
"sdbootpart=1\0" \
"sddev=0\0" \
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
"ubi.fm_autoconvert=1\0" \
@ -95,7 +82,6 @@
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
UBI_BOOTCMD \
"console=ttymxc0\0" \
"defargs=user_debug=30\0" \

18
include/configs/colibri_imx6.h
View File

@ -148,23 +148,6 @@
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define SD_BOOTCMD \
"set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \
"rootfstype=ext4 rootwait\0" \
"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card; " \
"run sddtbload; load mmc ${sddev}:${sdbootpart} "\
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
"sdbootpart=1\0" \
"sddev=1\0" \
"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
"${fdt_addr_r} ${fdt_file} && setenv dtbparam \" - " \
"${fdt_addr_r}\" && true\0" \
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
@ -180,7 +163,6 @@
"fdt_fixup=;\0" \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \

23
include/configs/colibri_imx7.h
View File

@ -109,28 +109,6 @@
"ramdisk_addr_r=0x82100000\0" \
"scriptaddr=0x82500000\0"
#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
#define SD_BOOTDEV 0
#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
#define SD_BOOTDEV 1
#endif
#define SD_BOOTCMD \
"set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \
"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} " \
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"run m4boot && " \
"load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
"load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \
"${soc}-colibri-${fdt_board}.dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
"sdbootpart=1\0" \
"sddev=" __stringify(SD_BOOTDEV) "\0" \
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
@ -184,7 +162,6 @@
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
MODULE_EXTRA_ENV_SETTINGS \
"boot_file=zImage\0" \
"console=ttymxc0\0" \

1
include/configs/imx8qm_mek.h
View File

@ -10,7 +10,6 @@
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR

52
include/configs/kp_imx6q_tpc.h
View File

@ -25,30 +25,10 @@
#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
/* FEC ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_ARP_TIMEOUT 200UL
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@ -81,14 +61,42 @@
"rdinit=/sbin/init\0" \
"addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
"fit_config=mx6q_tpc70_conf\0" \
"uboot_file=u-boot.img\0" \
"SPL_file=SPL\0" \
"wic_file=kp-image-kpimx6qtpc.wic\0" \
"upd_image=st.4k\0" \
"updargs=setenv bootargs console=${console} ${smp}"\
"rdinit=${rdinit} ${debug} ${displayargs}\0" \
"updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \
"initrd_ram_dev=/dev/ram\0" \
"addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \
"loadusb=usb start; " \
"fatload usb 0 ${loadaddr} ${upd_image}\0" \
"upd_uboot_sd=" \
"if tftp ${loadaddr} ${uboot_file}; then " \
"setexpr blkc ${filesize} / 0x200;" \
"setexpr blkc ${blkc} + 1;" \
"mmc write ${loadaddr} 0x8A ${blkc};" \
"fi;\0" \
"upd_SPL_sd=" \
"if tftp ${loadaddr} ${SPL_file}; then " \
"setexpr blkc ${filesize} / 0x200;" \
"setexpr blkc ${blkc} + 1;" \
"mmc write ${loadaddr} 0x2 ${blkc};" \
"fi;\0" \
"upd_SPL_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_SPL_sd\0" \
"upd_uboot_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_uboot_sd\0" \
"up_mmc=run upd_SPL_mmc; run upd_uboot_mmc\0" \
"up_sd=run upd_SPL_sd; run upd_uboot_sd\0" \
"upd_wic=" \
"if tftp ${loadaddr} ${wic_file}; then " \
"setexpr blkc ${filesize} / 0x200;" \
"setexpr blkc ${blkc} + 1;" \
"mmc write ${loadaddr} 0x0 ${blkc};" \
"fi;\0" \
"usbupd=echo Booting update from usb ...; " \
"setenv bootargs; " \
"run updargs; " \
"run addinitrd; " \
"run addswupdate; " \
"run loadusb; " \
"bootm ${loadaddr}#${fit_config}\0" \
BOOTENV

48
include/configs/meerkat96.h Normal file
View File

@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2016 NXP Semiconductors
*
* Configuration settings for Meerkat96 board.
*/
#ifndef __MEERKAT96_CONFIG_H
#define __MEERKAT96_CONFIG_H
#include "mx7_common.h"
#include <imximage.h>
#define PHYS_SDRAM_SIZE SZ_512M
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Environment configs */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
/* USB configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif

22
include/configs/mx6sabre_common.h
View File

@ -51,7 +51,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"fdt_file=undefined\0" \
"fdtfile=undefined\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
@ -87,7 +87,7 @@
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \
@ -116,7 +116,7 @@
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
@ -129,20 +129,20 @@
"bootz; " \
"fi;\0" \
"findfdt="\
"if test $fdt_file = undefined; then " \
"if test $fdtfile = undefined; then " \
"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
"setenv fdtfile imx6qp-sabreauto.dtb; fi; " \
"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
"setenv fdtfile imx6q-sabreauto.dtb; fi; " \
"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
"setenv fdtfile imx6dl-sabreauto.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
"setenv fdtfile imx6qp-sabresd.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
"setenv fdt_file imx6q-sabresd.dtb; fi; " \
"setenv fdtfile imx6q-sabresd.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
"if test $fdt_file = undefined; then " \
"setenv fdtfile imx6dl-sabresd.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine dtb to use; fi; " \
"fi;\0" \

37
include/configs/pico-imx7d.h
View File

@ -55,17 +55,17 @@
/* When booting with FIT specify the node entry containing boot.scr */
#if defined(CONFIG_FIT)
#define PICO_BOOT_ENV \
"bootscr_fitimage_name=bootscr\0" \
"bootscriptaddr=0x83200000\0" \
"fdtovaddr=0x83100000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"rootwait rw;\0" \
"loadbootscript=" \
"load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${bootscriptaddr}:${bootscr_fitimage_name}\0"
BOOTENV \
"fdtovaddr=0x83100000\0" \
"scriptaddr=0x83200000\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"rootwait rw\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \
"iminfo ${scriptaddr};" \
"if test $? -eq 1; then hab_failsafe; fi;" \
"source ${scriptaddr}:bootscr\0"
#else
#define PICO_BOOT_ENV \
"bootmenu_0=Boot using PICO-Hobbit baseboard=" \
@ -112,21 +112,6 @@
"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
PICO_BOOT_ENV
#if defined(CONFIG_FIT)
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"iminfo ${bootscriptaddr};" \
"if test $? -eq 1; then hab_failsafe; fi;" \
"run bootscript; " \
"else " \
"echo Fail to load fitImage with boot script;" \
"hab_failsafe;" \
"fi; " \
"fi"
#endif
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \

9
include/configs/tbs2910.h
View File

@ -40,15 +40,6 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_BMP_RLE8

1
include/imx_lpi2c.h
View File

@ -18,6 +18,7 @@ struct imx_lpi2c_bus {
struct i2c_pads_info *pads_info;
struct udevice *bus;
struct clk per_clk;
struct clk ipg_clk;
};
struct imx_lpi2c_reg {