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arm: dts: k3-j721e-main: Add C71x DSP node

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The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2019-09-04 16:01:40 +05:30 committed by Tom Rini
parent 293e39780d
commit 1b846fc24d
2 changed files with 12 additions and 0 deletions
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1
arch/arm/dts/k3-j721e-common-proc-board.dts
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@ -22,6 +22,7 @@
remoteproc5 = &main_r5fss1_core1;
remoteproc6 = &c66_0;
remoteproc7 = &c66_1;
remoteproc8 = &c71_0;
};
};

11
arch/arm/dts/k3-j721e-main.dtsi
View File

@ -328,4 +328,15 @@
ti,sci-proc-ids = <0x04 0xFF>;
resets = <&k3_reset 143 1>;
};
c71_0: dsp@64800000 {
compatible = "ti,j721e-c71-dsp";
reg = <0x00 0x64800000 0x00 0x00080000>,
<0x00 0x64e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&dmsc>;
ti,sci-dev-id = <15>;
ti,sci-proc-ids = <0x30 0xFF>;
resets = <&k3_reset 15 1>;
};
};