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arm: omap: emif-common: Fix memory priming for ECC

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Before the priming begins, we need to disable RMW (Read Modify Write)
and disable ECC verification for read accesses. By default, the EMIF
tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG.

Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Krunal Bhargav 2019-09-16 13:47:18 +05:30 committed by Tom Rini
parent d0a37a5e51
commit 2b2e1573cf
1 changed files with 21 additions and 13 deletions
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34
arch/arm/mach-omap2/emif-common.c
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@ -348,7 +348,7 @@ static void dra7_reset_ddr_data(u32 base, u32 size)
static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 rgn, rgn_start, size;
u32 rgn, rgn_start, size, ctrl_reg;
/* ECC available only on dra76x EMIF1 */
if ((base != EMIF1_BASE) || !is_dra76x())
@ -358,11 +358,28 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
/* Disable high-order interleaving */
clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
#ifdef CONFIG_DRA7XX
/* Clear the status flags and other history */
writel(readl(&emif->emif_1b_ecc_err_cnt),
&emif->emif_1b_ecc_err_cnt);
writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
writel(0x2, &emif->emif_1b_ecc_err_addr_log);
writel(0x1, &emif->emif_2b_ecc_err_addr_log);
writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
&emif->emif_irqstatus_sys);
#endif
writel(regs->emif_ecc_address_range_1,
&emif->emif_ecc_address_range_1);
writel(regs->emif_ecc_address_range_2,
&emif->emif_ecc_address_range_2);
writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
/* Disable RMW and ECC verification for read accesses */
ctrl_reg = (regs->emif_ecc_ctrl_reg &
~EMIF_ECC_REG_RMW_EN_MASK) |
EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK;
writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
/* Set region1 memory with 0 */
rgn_start = (regs->emif_ecc_address_range_1 &
@ -386,17 +403,8 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
dra7_reset_ddr_data(rgn, size);
#ifdef CONFIG_DRA7XX
/* Clear the status flags and other history */
writel(readl(&emif->emif_1b_ecc_err_cnt),
&emif->emif_1b_ecc_err_cnt);
writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
writel(0x1, &emif->emif_2b_ecc_err_addr_log);
writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
&emif->emif_irqstatus_sys);
#endif
/* Default value enables RMW and ECC verification */
writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
}
}