Commit Graph

5776 Commits

Author SHA1 Message Date
Simon Glass
91cbd792c4 dm: core: Allow device_bind() to used without CONFIG_OF_CONTROL
The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:30 -06:00
Simon Glass
bf1a86fca0 sf: Add an empty entry to the parameter list
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-23 12:44:30 -06:00
Stefano Babic
42817eb85d Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-22 15:51:01 +02:00
Boris BREZILLON
d357b94041 mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECC
Disable subpage write when using PMECC to prevent buggy partial page write.

This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:22 +02:00
Bo Shen
97b2043da6 USB: ehci-atmel: use pcr to enable or disable clock
If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:21 +02:00
Bo Shen
01c8bf5a6f USB: ohci-at91: use pcr to enable or disable clock
If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:20 +02:00
Wu, Josh
14b3b44eda mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc register
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-19 00:11:13 +02:00
Tom Rini
e38b15b061 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-17 18:01:04 -04:00
Simon Glass
ad6e48e509 net: usb: Add SMSC copyright to smsc95xx driver
This driver was upstreamed without an SMSC copyright, even thought it seems
that SMSC was the original author.

See the kernel version for a code comparison:

http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190

It's not clear who actually moved this code, or whether the kernel was the
original source, or somewhere else, but it probably should still have the
SMSC copyright.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-16 12:23:59 -04:00
maxin.john@enea.com
5da163d665 mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREAD
This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-09-16 12:23:59 -04:00
Khoronzhuk, Ivan
7206111e52 mtd: nand: davinci_nand: update write_page function for keystone RBL
After mtd was synced with Linux 3.14
(ff94bc40af)
the number of parameters for write_page function of nand_chip was
changed. The additional two var were needed for subpage write.
As keystone has no supbage write they are not needed. So correct
only function definition by upgrading it's parameter list.
That helps to get ritd of compilation warning.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-16 12:23:59 -04:00
Masahiro Yamada
3b61297024 kbuild: force to define __UBOOT__ in all the C sources
U-Boot has imported various source files from other projects,
mostly Linux.

Something like

  #ifdef __UBOOT__
    [ modification for U-Boot ]
  #else
    [ original code ]
  #endif

is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.

Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2014-09-16 12:23:56 -04:00
Thierry Reding
5d9f423ddb rtl8169: Defer network packet processing
When network protocol errors occur (such as a file not being found on a
TFTP server), the processing done by the NetReceive() function will end
up calling the driver's .halt() implementation. However, after that the
device no longer has access to the memory buffers and will cause errors
such as this in the rtl_recv() function when trying to hand descriptors
back to the device:

	pci_hose_bus_to_phys: invalid physical address

This can be fixed by deferring processing of network packets until the
descriptors have been handed back. That way rtl_halt() tearing down
network buffers is not going to prevent access to the buffers.

Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-09-16 12:23:45 -04:00
Stefan Agner
72d7beabf7 mtd: nand: add Freescale vf610_nfc driver
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
2014-09-16 13:25:18 +02:00
Vasili Galka
9f680d2d97 openrisc: Fix a few type cast related warnings
Use size_t type for positive offsets instead of the loff_t type. The
later is defined as long long, which is larger than the pointer type
on OpenRISC architecture and therefore the following warning was
generated:

"warning: cast to pointer from integer of different size"

Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-09-15 13:32:56 -04:00
Tom Rini
8d028d404f Merge branch 'master' of git://git.denx.de/u-boot-dm 2014-09-13 16:32:52 -04:00
Tom Rini
114cc4290b Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-09-12 11:27:46 -04:00
Simon Glass
858530a8c0 dm: tegra: Enable driver model for serial
Use driver model for serial ports.

Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:02 -06:00
Simon Glass
12e431b277 dm: serial: Add driver model support for ns16550
Add driver model support so that ns16550 can support operation both with
and without driver model.

The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:01 -06:00
Simon Glass
8bbe33c829 dm: serial: Collect common baud rate code in ns16550
The same sequence is used in several places, so move it into a function.
Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:01 -06:00
Simon Glass
fa54eb1243 dm: serial: Move baud rate calculation to ns16550.c
Move the function that calculates the baud rate divisor into ns16550.c so
it can be used by that file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:01 -06:00
Simon Glass
72e98228c3 sandbox: serial: Support a coloured console
The current sandbox serial driver is a pretty trivial example and does not
have the featues that might be needed for other board serial drivers. To
help provide a better example, add a text colour property to the device
tree for sandbox. This uses platform data, a device tree node, driver
private data and a remove() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:00 -06:00
Simon Glass
890fcefe2e sandbox: Convert serial driver to use driver model
Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:00 -06:00
Simon Glass
57d92753d4 dm: Add a uclass for serial devices
Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 13:00:00 -06:00
Simon Glass
1f359e3611 dm: Adjust lists_bind_fdt() to return the bound device
Allow the caller to find out the device that was bound in response to this
call.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Simon Glass
addf9513d0 serial: Set up the 'priv' pointer when creating a serial device
The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Simon Glass
2fccd2d96b tegra: Convert tegra GPIO driver to use driver model
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.

The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.

The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.

Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Fabio Estevam
1b8ad74a6f pcie_imx: Add mx6solox support
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 17:24:49 +02:00
Stefan Agner
89e69fd4a9 arm: vf610: lpuart: disable FIFO on initializaton
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.

This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09 16:54:16 +02:00
Stefan Agner
a3db78d887 arm: vf610: lpuart: fix status register handling
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.

Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.

Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-09-09 16:52:44 +02:00
Tim Harvey
0991866cf7 pci: add support for board_pci_fixup_dev function
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09 16:15:02 +02:00
Nikita Kiryanov
dc383dd583 sata: dwc_ahsata: implement sata_port_status
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09 15:32:32 +02:00
Fabio Estevam
f599288d55 net: fec_mxc: Poll FEC_TBD_READY after polling TDAR
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 15:06:12 +02:00
Fabio Estevam
db5b7f566e net: fec_mxc: Adjust RX DMA alignment for mx6solox
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.

Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-09-09 15:05:37 +02:00
Albert ARIBAUD
b653516769 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-09-09 00:21:24 +02:00
Wang Huan
327def5060 video: dcu: Add DCU driver support
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:35 -07:00
Jingchang Lu
6209e14cb0 serial: lpuart: add 32-bit registers lpuart support
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.

Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
2014-09-08 10:30:35 -07:00
York Sun
ef87cab664 driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
5cb27c5d44 driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
d28cb67142 driver/ddr/freescale: Add support of accumulate ECC
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
Wang Huan
19060bd886 ls102xa: esdhc: Add esdhc support for LS102xA
For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.

For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:34 -07:00
Alison Wang
52d00a812a ls102xa: etsec: Add etsec support for LS102xA
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:33 -07:00
Alison Wang
d2614ea0ff net: mdio: Use mb() to be compatible for both ARM and PowerPC
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:33 -07:00
Claudiu Manoil
93f26f130e net: Merge asm/fsl_enet.h into fsl_mdio.h
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08 10:30:33 -07:00
Wang Huan
df0a5b880d ls102xa: i2c: Add i2c support for LS102xA
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.

This patch is to add I2C 1,2,3 support for LS102xA.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08 10:30:32 -07:00
Wang Huan
d60a2099a2 arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-08 10:30:32 -07:00
Vadim Bendebury
9e8f664ecb video: Add driver for Parade PS8625 dP to LVDS bridge
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
45c480c9f6 video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
f0017175e3 exynos_fb: Remove usage of static defines
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.

Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Rostislav Lisovy
cc81a52919 mtd: nand: omap_gpmc: Fix 'bit-flip' errors
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html

Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."

This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-04 13:06:00 -04:00
Rostislav Lisovy
5c3f7e0ead mtd: nand: omap_gpmc: Enable multiple NAND flash devices
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.

Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
fc12a1f589 mtd: nand: davinci_nand: correct keystone RBL layout definition
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-04 13:06:00 -04:00
Khoronzhuk, Ivan
e6c9428a2f keystone2: use readl/writel functions instead of redefinition
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
2014-09-04 13:06:00 -04:00
Bo Shen
06fa91cd67 USB: gadget: s3c: get rid of debug compile warning
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-09-02 14:32:15 +02:00
Bo Shen
f9abd4b415 USB: gadget: atmel: get rid of debug compile warning
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-09-02 14:32:15 +02:00
Stephen Warren
842ef9a98e usb: ci_udc: implement dfu_usb_get_reset
This allows the USB code to determine whether a USB bus reset was issued,
which in turn allows the code to differentiate between a detach (return
to shell prompt) and a board reset/reboot request.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 14:29:28 +02:00
Lukasz Majewski
f2ec4e34aa udc: dfu: s3c_udc: Provide function to check if USB reset was asserted
New dfu_usb_get_reset() method is necessary to distinct two different
use cases of dfu-util program.
This method checks if the USB bus reset has been really performed after
DFU DETACH.

Without this function the previous DFU behavior is preserved.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-09-02 14:29:28 +02:00
Lukasz Majewski
1cc03c5c53 dfu: Provide means to find difference between dfu-util -e and -R
This commit provides distinction between DFU device detach and reset.
The -R behavior is preserved with proper handling of the dfu-util's -e
switch, which detach the DFU device.

By running dfu-util -e; one can force device to finish the execution of
dfu command on target and execute some other scripted commands.

Moreover, some naming has been changed - the dfu_reset() method now is known
as dfu_detach(). New name better reflects the purpose of the code.

It was also necessary to increase the number of usb_gadget_handle_interrupts()
calls since we also must wait for detection of the USB reset event.

Example usage:
1. -e (detach) switch
 dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e

 access to u-boot prompt.

2. -R (reset) switch
 dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage

 target board reset

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 14:29:28 +02:00
Tom Rini
0a64bc20f7 Merge branch 'master' of git://git.denx.de/u-boot-nios 2014-08-31 07:45:55 -04:00
Holger Brunck
292221e183 arm/kirkwood/nand: allow forced disabling for subpage writes
Make it configurable to disable subpage writes like the DaVinci NAND
driver already does.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Scott Wood <scottwood@freescale.com>
2014-08-30 07:46:41 -04:00
Jiandong Zheng
799e125cca arm: bcm281xx: net: Add Ethernet Driver
The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom
SoC(s) and:
- supports multiple MAC blocks,
- provides support for the Broadcom GMAC.
This driver requires MII and PHYLIB.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Pavel Machek
7860649716 socfpga: cleanup socfpga_dw_mmc
Cleanups as suggested by wd on mailing list.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
2014-08-30 07:46:38 -04:00
Thomas Chou
3a55a56662 serial: move nios2-yanu.h into opencores_yanu driver
The nios2-yanu.h contains hardware registers and bits of
opencores yanu. As there is no other user of this header
, it should be moved into the driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
CC: Renato Andreola <renato.andreola@imagos.it>
2014-08-30 17:48:43 +08:00
Thomas Chou
8645071006 nios2: divide nios2-io.h into each specific drivers and remove it
The nios2-io.h defines hardware registers and bits of several FPGA
IP cores. It could be divided in to the specific drivers, including
altera timer, altera sysid, altera uart and altera jtag uart. The
altera pio and altera spi drivers use their own hardware definitions.
The removal of nios2-io.h will help modularity and maintenance.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Pavel Machek
51fb455f82 socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.

This fixes structure to match hardware.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29 15:50:50 -04:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
Stefan Roese
5a834c1f9e net: cpsw: am335x: Drop constant link checking from rx/tx path's
We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected
to the CPSW MAC) that the network performance in U-Boot is quite poor. Only
when the transfer is started without a cable connected, and the cable is
plugged after the first timeout "T" occured, an increased in performance
can be seen. Debugging has revealed, that the cpsw driver has constant
link checking builtin into the rx and tx functions. This results in the
bad performance and seems to be unnecessary. The link has already been
checked in the init function, before the transfer is started. This usually
is sufficient.

BTW: I have seen no other network driver in U-Boot so far, that constantly
checks for link in the rx / tx functions.

The performance numbers on the DXR2 board are:

0.56 MiB/s	cpsw_check_link() in rx and tx path
0.87 MiB/s	cpsw_check_link() only in tx path
1.0  MiB/s	cpsw_check_link() only in rx path
2.7  MiB/s	no cpsw_check_link() in rx and tx path

So with this patch the network performance on DXR2 increases from 0.56
to 2.7 MiB/s (nearly 5 times as fast).

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Samuel Egli <samuel.egli@siemens.com>
Tested-by: Heiko Schocher <hs@denx.de>
Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
2014-08-28 17:18:49 -04:00
Tom Rini
3e1b36bd58 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-28 13:03:25 -04:00
Heiko Schocher
4e67c57125 mtd,ubi,ubifs: sync with linux v3.15
snyc with linux v3.15:

commit 1860e379875dfe7271c649058aeddffe5afd9d0d
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Jun 8 11:19:54 2014 -0700

    Linux 3.15

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ddf7bcfa6c mtd, ubi, ubifs: update for the sync with linux v3.14
while playing with the new mtd/ubi/ubifs sync, found some
small updates for it:

- add del_mtd_partition() to include/linux/mtd/mtd
- mtd: add a debug_printf
- remove some not used functions

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ff94bc40af mtd, ubi, ubifs: resync with Linux-3.14
resync ubi subsystem with linux:

commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Mar 30 20:40:15 2014 -0700

    Linux 3.14

A nice side effect of this, is we introduce UBI Fastmap support
to U-Boot.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Joerg Krause <jkrause@posteo.de>
2014-08-25 19:25:55 -04:00
Heiko Schocher
0c06db5983 lib, linux: move linux specific defines to linux/compat.h
- move linux specific defines from usb and video code
  into linux/compat.h
- move common linux specific defines from include/ubi_uboot.h
  to linux/compat.h
- add for new mtd/ubi/ubifs sync new needed linux specific
  defines to linux/compat.h

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
[trini: Add spin_lock_irqsave/spin_unlock_irqrestore dummies from
usb/lin_gadet_compat.h]
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 19:25:03 -04:00
Tom Rini
7bee1c91a9 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2014-08-25 08:34:39 -04:00
Marek Vasut
951860634f e1000: add i210 support
Add i210 support to the e1000 driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-21 12:01:28 -04:00
Marek Vasut
873e8e0198 e1000: Implement dcache support
Implement proper support for cache flushing and invalidation into the
Intel e1000 NIC driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-21 12:01:28 -04:00
Masahiro Yamada
d1a4aafd71 powerpc: mpc8xx: remove svm_sc8xx board
This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
62d636aa2a omap: remove omap5912osk board support
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.

Tom suggested to remove this board.

Remove also omap1510_udc.c because this is the last board
to enable it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
368b4d2b49 drivers: net: remove dead drivers
The following configs are not defined at all:

 - CONFIG_INCA_IP_SWITCH
 - CONFIG_PBL2800_ETHER
 - CONFIG_PHY_ICPLUS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Tom Rini
67ee22b068 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-08-20 16:07:34 -04:00
Shaohui Xie
9bf499ace8 powerpc/T4240QDS/eth: some fix for XFI
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:<10g_mac_name>

the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.

Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Vijay Rai
12eeb1359a driver/qe: update status of QE microcode
This Patch updates error print for QE which should be easily understood

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Tim Harvey
5a82e1a21d pci: mx6: fix occasional link failures
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 12:37:15 +02:00
Markus Niebel
412921d29e RTC: add support for DS1339 (using DS1307 driver)
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2014-08-14 14:45:58 +02:00
vijay rai
5be1af0198 driver/qe: update status of QE microcode
This Patch updates error print for QE which should be easily understood

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
2014-08-14 14:22:09 +02:00
Stephen Warren
d878c9a932 pci: fix overflow in __pci_hose_bus_to_phys w/ large RAM
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-14 11:38:47 +02:00
Jeroen Hofstee
e6e9cff2dc video: ipu_disp: squash clang warning
Since rgb2ycbcr_coeff and friends are declared const, but assigned
to a void pointer, clang will warn that the const is implicity casted
away. If the pointer is changed to void const * gcc will warn when it
is implicitly casted to a const int array. Just add a correctly
typed pointer instead to prevent these casts and hence the warnings.

Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-11 17:52:21 +02:00
Liu Ying
e66866c542 video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Instead of waiting for DC triple buffer to be cleared, this patch
changes to wait for a relevant DP sync flow end interrupt to come
when disabling sync BG flows.  In this way, we align the implement
to the freescale internal IPUv3 driver.  After applying this patch,
an uboot hang up issue at the arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2014-08-11 17:31:41 +02:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
Hannes Petermaier
3c5fabd139 video: Add support for TI's AM335x LCD-Controller
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
  to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD,
  common/lcd.c)

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
2014-08-10 15:34:27 +02:00
Masahiro Yamada
8ac22a60e2 omap: clean-up dead configs
The following configs are not defined at all.

 - CONFIG_OMAP1510
 - CONFIG_OMAP_1510P1
 - CONFIG_OMAP_SX1
 - CONFIG_OMAP3_DMA
 - CONFIG_OMAP3_ZOOM2
 - CONFIG_OMAP_INNOVATOR

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2014-08-09 11:17:04 -04:00
maxin.john@enea.com
79e86ccb37 vitesse: remove duplicated argument to ||
Remove the duplicated argument to || check

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:02 -04:00
Nobuhiro Iwamatsu
53022c3113 serial: sh: Add support External Clock mode
R8A7780 and R7A7791 of rmobile supports External Clock mode, and these uses
different from Internal Clock mode registers and calculations to the baud rate
setting. This adds function for External Clock mode.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
1a223c9324 serial: sh: Add support DL and CKS register for R8A7794
R8A7794 has DL and CKS register, and these registers are used in external clock
mode. This adds support these for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
5906fadefa usb: ehci: rmobile: Remove xHCI address
echi-rmobile does not support xHCI. This removes xHCI address
from address table. And this revise a value of CONFIG_USB_MAX_CONTROLLER_COUNT
for lager board and koelsh board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
ed7ce836cd usb: ehci: rmobile: Add support R8A7794
R8A7794 has same IP of USB controller as R8A7790 and R8A7791.
This addes support for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-09 11:17:01 -04:00
Stephen Warren
67ab0a5e9f dfu: fix readback buffer overflow test
The buffer is too small if it's < size to read, not if it's <= the size.
This fixes the 1MB test case on Tegra, which has a 1MB buffer.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:01 -04:00
Stephen Warren
6f12ebf6ea dfu: add SF backend
This allows SPI Flash to be programmed using DFU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
cb7bd2e07e dfu: add free_entity() to struct dfu_entity
This allows the backend to free any resources allocated during the
relevant dfu_fill_entity_*() call. This will soon be used by the
SF backend.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
7ac1b410ac dfu: allow backend to specify a maximum buffer size
CONFIG_SYS_DFU_DATA_BUF_SIZE may be large to allow for FAT/ext layouts
to transfer large files. However, this means that individual write
operations will take a long time. Allow backends to specify a maximum
buffer size, so that each write operation is limited to a smaller data
block. This prevents the DFU protocol from timing out when e.g. writing
to SPI flash. I would guess that NAND might benefit from setting this
value too, but I can't test that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
dd64827eb6 dfu: defer parsing of device string to IO backend
Devices are not all identified by a single integer. To support
this, defer the parsing of the device string to the IO backed, so that
it can apply the appropriate rules.

SPI devices are specified as controller:chip_select. SPI/SF support will
be added soon.

MMC devices can also be specified as controller[.hwpart][:partition] in
many commands, although we don't support that syntax in DFU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
3ee9593fce dfu: add write error handling
Fix calls to dfu_write() and dfu_flush() to detect errors in the I/O
itself. This could happen due to problems with the storage medium, or
simply when trying to write a FAT/ext file that is larger than the buffer
dfu_mmc.c maintains for this purpose.

Signal the error by switching the DFU state/status. This will be picked
up by the DFU client when it sends the next DFU request. Note that errors
can't simply be returned from e.g. dnload_request_complete(), since that
function has no way to pass errors back to the DFU client; a call to
dnload_request_complete() simply means that a USB OUT completed.

This error state/status needs to be cleared when the next DFU client
connects. While there is a DFU_CLRSTATUS request, no DFU client seems to
send this. Hence, clear this when selecting the USB alternate setting on
the USB interface.

Finally, dfu.c relies on a call to dfu_flush() to clear up the internal
state of the write transaction. Now that errors in dfu_write() are
detected, dfu_flush() may no longer be called for every transaction.
Separate out the cleanup code into a new function, and call it whenever
dfu_write() fails, as well as from any call to dfu_flush().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
0e285b503c dfu: fix some issues with reads/uploads
DFU read support appears to rely upon dfu->read_medium() updating the
passed-by-reference len parameter to indicate the remaining size
available for reading.

dfu_read_medium_mmc() never does this, and the implementation of
dfu_read_medium_nand() will only work if called just once; it hard-codes
the value to the total size of the NAND device irrespective of read
offset.

I believe that overloading dfu->read_medium() is confusing. As such,
this patch introduces a new function dfu->get_medium_size() which can
be used to explicitly find out the medium size, and nothing else.
dfu_read() is modified to use this function to set the initial value for
dfu->r_left, rather than attempting to use the side-effects of
dfu->read_medium() for this purpose.

Due to this change, dfu_read() must initially set dfu->b_left to 0, since
no data has been read.

dfu_read_buffer_fill() must also be modified not to adjust dfu->r_left
when simply copying data from dfu->i_buf_start to the upload request
buffer. r_left represents the amount of data left to be read from HW.
That value is not affected by the memcpy(), but only by calls to
dfu->read_medium().

After this change, I can read from either a 4MB or 1.5MB chunk of a 4MB
eMMC boot partion with CONFIG_SYS_DFU_DATA_BUF_SIZE==1MB. Without this
change, attempting to do that would result in DFU read returning no data
at all due to r_left never being set.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Albert ARIBAUD
1899fac925 Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-08-09 16:48:34 +02:00
Fabio Estevam
676ac24e07 pmic: pmic_pfuze100: Use a shorter name for PMIC name
It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.

Call it simply 'PFUZE100' instead.

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:41 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Andy Fleming
b21f87a3e0 Change Andy Fleming's email address
Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com

Signed-off-by: Andy Fleming <afleming@gmail.com>
2014-08-06 09:12:30 -04:00
Tom Rini
336450f5fc Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-08-06 08:38:19 -04:00
Heiko Schocher
f659b57361 spi, spi_mxc: do not hang in spi_xchg_single
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
22052c6236 spi: Support half-duplex mode in FDT decode
This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
a4e29db257 exynos: spi: Fix calculation of SPI transaction start time
The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
2001b9a641 cros_ec: Fix two bugs in the SPI implementation
An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Marek Vasut
a52a178f0b sf: sf_ops: Stop leaking memory
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Bo Shen
da55c66ec9 MMC: atmel_mci: enable high speed mode support
If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:01:33 +03:00
Bo Shen
cd60ebd430 MMC: atmel_mci: refactor setting the mode register
The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:01:09 +03:00
Chin Liang See
6ace153d13 mmc/dw_mmc: Fix clock divider calculation error for bypass mode
To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
2014-08-01 19:45:32 +03:00
Marek Vasut
dae0f5c644 mmc: s3c: Add SD driver
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 19:24:34 +03:00
Lubomir Rintel
64973023df bcm2835_sdhci: Add SDHCI_QUIRK_NO_HISPD_BIT flag
Seems like the controller doesn't support the flag. None of the hi-speed cards
I've tried could be read, while they successfully worked with the quirk enabled.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-08-01 18:57:02 +03:00
DrEagle
3fe3b4fb1c ARM: kirkwood: add mvsdio driver
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 18:44:56 +03:00
Roman Byshko
8d154002f3 sunxi: add USB EHCI driver
The Allwinner aka sunxi SoCs have one or more USB host controllers.
This adds a driver for their EHCI.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Ian Campbell
a6e50a88d8 ahci: provide sunxi SATA driver using AHCI platform framework
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.

The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.

The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port.  This is added under a
suitable ifdef.

This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Tom Rini
362f16b1e9 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-07-29 09:41:35 -04:00
Tom Rini
d5f8a6ddd4 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-07-28 14:54:29 -04:00
Albert ARIBAUD
b1cdd8baa1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-28 12:26:21 +02:00
Albert ARIBAUD
48b3ed217f Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2014-07-28 10:54:54 +02:00
Albert ARIBAUD
740f41d3cb Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-07-28 10:12:45 +02:00
Khoronzhuk, Ivan
7c38764606 keystone2: use CONFIG_SOC_KEYSTONE in common places
Use CONFIG_SOC_KEYSTONE in common places instead of defining
a lot of "if def .. || if def " for different Keystone2 SoC types.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
67ac6ffaee mtd: nand: davinci: add opportunity to write keystone U-boot image
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.

The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.

The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.

Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 15:21:06 -04:00
Tom Rini
7aa5598aac tps65218/am43xx_evm: Add power framework support to TPS65218
Add in an init function for the drivers/power framework so we can dump
and read the registers via i2c.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-07-25 15:21:06 -04:00
Mugunthan V N
7a0227534d drivers: net: cpsw: add support for using second port as ethernet
Add support for using the second slave port of cpsw
to be used as primary ethernet.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Nobuhiro Iwamatsu
2f972a3c62 serial: sh: Add support R8A7794
This adds the preset value to register for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Nobuhiro Iwamatsu
172437472a net: sh-eth: Add support R8A7794
R8A7794 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Simon Glass
74f96dada1 dm: Give the demo uclass a name
Uclasses should be named, so add a name for the demo uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
bb58503d80 dm: Add dm_scan_other() to locate board-specific devices
Some boards will have devices which are not in the device tree and do not
have platform data. They may be programnatically created, for example.
Add a hook which boards can use to bind those devices early in boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
9b0ba067f9 dm: Improve errors and warnings in lists_bind_fdt()
Add a debug message for when a device tree node has no driver. Also reword
the warning when a device fails to bind, which was misleading.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
a327dee0f4 dm: Add child_pre_probe() and child_post_remove() methods
Some devices (particularly bus devices) must track their children, knowing
when a new child is added so that it can be set up for communication on the
bus.

Add a child_pre_probe() method to provide this feature, and a corresponding
child_post_remove() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
e59f458de6 dm: Introduce per-child data for devices
Some device types can have child devices and want to store information
about them. For example a USB flash stick attached to a USB host
controller would likely use this space. The controller can hold
information about the USB state of each of its children.

The data is stored attached to the child device in the 'parent_priv'
member. It can be auto-allocated by dm when the child is probed. To
do this, add a per_child_auto_alloc_size value to the parent driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
997c87bb0b dm: Add functions to access a device's children
Devices can have childen that can be addressed by a simple index, the
sequence number or a device tree offset. Add functions to access a child
in each of these ways.

The index is typically used as a fallback when the sequence number is not
available. For example we may use a serial UART with sequence number 0 as
the console, but if no UART has sequence number 0, then we can fall back
to just using the first UART (index 0).

The device tree offset function is useful for buses, where they want to
locate one of their children. The device tree can be scanned to find the
offset of each child, and that offset can then find the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
1ca7e2062b dm: Provide a function to scan child FDT nodes
At present only root nodes in the device tree are scanned for devices.
But some devices can have children. For example a SPI bus may have
several children for each of its chip selects.

Add a function which scans subnodes and binds devices for each one. This
can be used for the root node scan also, so change it.

A device can call this function in its bind() or probe() methods to bind
its children.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:36 +01:00
Simon Glass
c910e2e2da dm: Avoid accessing uclasses before they are ready
Don't allow access to uclasses before they have been initialised.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
f4cdead24a dm: Allow a device to be found by its FDT offset
Each device that was bound from a device tree has an node that caused it to
be bound. Add functions that find and return a device based on a device tree
offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
5a66a8ff86 dm: Introduce device sequence numbering
In U-Boot it is pretty common to number devices from 0 and access them
on the command line using this numbering. While it may come to pass that
we will move away from this numbering, the possibility seems remote at
present.

Given that devices within a uclass will have an implied numbering, it
makes sense to build this into driver model as a core feature. The cost
is fairly small in terms of code and data space.

With each uclass having numbered devices we can ask for SPI port 0 or
serial port 1 and receive a single device.

Devices typically request a sequence number using aliases in the device
tree. These are resolved when the device is probed, to deal with conflicts.
Sequence numbers need not be sequential and holes are permitted.

At present there is no support for sequence numbers using static platform
data. It could easily be added to 'struct driver_info' if needed, but it
seems better to add features as we find a use for them, and the use of -1
to mean 'no sequence' makes the default value somewhat painful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
9ca296a1b0 dm: Move uclass error checking/probing into a function
Several functions will use this same pattern, so bring it into a function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
093f79ab88 Add a flag indicating when the serial console is ready
For sandbox we have a fallback console which is used very early in
U-Boot, before serial drivers are available. Rather than try to guess
when to switch to the real console, add a flag so we can be sure. This
makes sure that sandbox can always output a panic() message, for example,
and avoids silent failure (which is very annoying in sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
ab7cd62790 dm: Support driver model prior to relocation
Initialise devices marked 'pre-reloc' and make them available prior to
relocation. Note that this requires pre-reloc malloc() to be available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
00606d7e39 dm: Allow drivers to be marked 'before relocation'
Driver model currently only operates after relocation is complete. In this
state U-Boot typically has a small amount of memory available. In adding
support for driver model prior to relocation we must try to use as little
memory as possible.

In addition, on some machines the memory has not be inited and/or the CPU
is not running at full speed or the data cache is off. These can reduce
execution performance, so the less initialisation that is done before
relocation the better.

An immediately-obvious improvement is to only initialise drivers which are
actually going to be used before relocation. On many boards the only such
driver is a serial UART, so this provides a very large potential benefit.

Allow drivers to mark themselves as 'pre-reloc' which means that they will
be initialised prior to relocation. This can be done either with a driver
flag or with a 'dm,pre-reloc' device tree property.

To support this, the various dm scanning function now take a 'pre_reloc_only'
parameter which indicates that only drivers marked pre-reloc should be
bound.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
9adbd7a116 dm: Provide a way to shut down driver model
Add a new method which removes and unbinds all drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:24 +01:00
Simon Glass
7497812d47 dm: Make sure that the root device is probed
The root device should be probed just like any other device. The effect of
this is to mark the device as activated, so that it can be removed (along
with its children) if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:24 +01:00
Simon Glass
709ea543b9 stdio: Pass device pointer to stdio methods
At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.

For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.

Instead, add a stdio_dev pointer to each of the stdio member functions.

Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.

Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.

22: stdio: Pass device pointer to stdio methods
       arm: (for 2/2 boards)  all +244.0  bss -4.0  text +248.0
   powerpc: (for 1/1 boards)  all +428.0  text +428.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Simon Glass
91d0be1dd8 stdio: Remove redundant code around stdio_register() calls
There is no point in setting a structure's memory to NULL when it has
already been zeroed with memset().

Also, there is no need to create a stub function for stdio to call - if the
function is NULL it will not be called.

This is a clean-up, with no change in functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Simon Glass
5b9765c7d6 dm: gpio: Don't use the driver model uclass for SPL
Driver model does not support SPL yet, so we should not use the GPIO
uclass for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:23 +01:00
Heiko Schocher
562f8df18d spi: add config option to enable the WP pin function on st micron flashes
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128 thorugh
the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-07-23 12:26:45 +02:00
Heiko Schocher
b2f97cf279 pwm, imx6: add support for pwm modul on imx6
add basic support for the pwm modul found on imx6.
Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c
Commit "cd3de83f1476 Linux 3.16-rc4"

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-07-23 12:25:42 +02:00
York Sun
3d75ec95f5 driver/ddr: Fix DDR register timing_cfg_8
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
591dd19230 driver/nand: Add support of 16K SRAM for IFC 2.0
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

Update the page offset calculation logic to support the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zang Roy-R61911
32514d259b fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint
Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
04818bbdc3 driver/nand: Update SRAM initialize logic for IFC.
IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.

update SRAM initialize logic to reflect the same.

Also print error message in case of Page read error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
3bab3d8324 driver/nand:Define MAX_BANKS same as SoC defined for IFC
The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zhao Qiang
38d67a4e55 qe: move immap_qe.h from arch directory into common directory
ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Rotariu Marian-Cristian
1155d8d853 net/fm: call fm_port_to_index() with proper checks
Some of the fm_port_to_index() callers did not check for -1 return value and
used -1 as an array index.

Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:53 -07:00
Ian Campbell
e0ddcf93b9 AHCI: Increase link timeout to 200ms
In 73545f75b6 "ahci: wait longer for link" I increased the
timeout to 40ms based on the observed behaviour of a WD disk on a
Cubietruck. Since then Karsten Merker and myself have both
observed timeouts with HGST disks (Karsten on Cubietruck, me on
Cubieboard2). Increasing the timeout to ~175ms fixes this, so go
to 200ms for a bit of headroom.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Karsten Merker <merker@debian.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-22 07:44:28 -04:00
Masahiro Yamada
5b9587ae31 serial: ns16550: use a const variable instead of macro
Just for type checking.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-22 07:44:25 -04:00
Masahiro Yamada
f8c7c2033d serial: ns16550: use DIV_ROUND_CLOSEST macro to compute the divisor
The function still returns the same value.

The comment block is no longer necessary because our intention is
clear enough by using DIV_ROUND_CLOSEST() macro.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-22 07:44:25 -04:00
Masahiro Yamada
841977df21 serial: ns16550: drop CONFIG_OMAP1610 from the special case
If CONFIG_OMAP1610 is defined, the code returning the fixed value (26)
is enabled. But this case is covered by the following code.

(CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
    (MODE_X_DIV * gd->baudrate)
= (48000000 + (115200 * (16 / 2))) / (16 * 115200)
= 48921600 / 1843200
= 26

The "#ifdef CONFIG_OMAP1610" was added by commit 6f21347d more than
ten years ago. In those days, the divide-and-round was not used.
I guess that is why this weird code was added here.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Rishi Bhattacharya <rishi@ti.com>
2014-07-22 07:44:25 -04:00
Lijun Pan
4a755f1da5 driver/usb: include upper/lower_32_bits() from linux/compat.h
upper_32_bits() and lower_32_bits() have been ported into linux/compat.h.
Start use them now in drivers/usb/host/xhci.h.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
2014-07-22 07:44:24 -04:00
Tom Rini
3364b1898c Merge branch 'master' of git://git.denx.de/u-boot-i2c 2014-07-21 11:04:10 -04:00
Jeroen Hofstee
750121c350 mmc: prevent some warnings with make W=1
Add missing prototypes for global functions and
make local functions static.

cc: panto@antoniou-consulting.com
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:24 -04:00
Jeroen Hofstee
cee9ab7cb6 dirvers: mmc: use __weak
use weak instead of alias to prevent some clang warnings.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
fd536d818d dm: add missing includes
lists.c / root.c do not include their own header and they
could potentially implement a different function. Therefore
actually include the headers.

cc: sjg@chromium.org
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
c15df21fe7 mtd: cfi_flash: fix clang warning
clang warns this check is silly; it is since s is
a local variable.

u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
  array 's' not equal to a null pointer is always true
  else if ((s != NULL) && (strcmp(s, "yes") == 0)) {

cc: Stefan Roese <sr@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:22 -04:00
Ian Campbell
abce2c6220 sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:25 +01:00
Hans de Goede
2428920835 sunxi: Add axp152 pmic support
Add support for the x-powers axp152 pmic which is found on most A10s boards
and enable it for the r7-tv-dongle board.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:16 +01:00
Henrik Nordstrom
14bc66bd9a sunxi: Add axp209 pmic support
Add support for the x-powers axp209 pmic which is found on most A10, A13 and
A20 boards.

And enable AXP209 support for the Cubietruck and Cubieboard boards.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:10 +01:00
Hans de Goede
6620377e4b sunxi: Add i2c support
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
2014-07-18 19:41:30 +01:00
Hans de Goede
0db2bbdc04 mvtwsi: convert to CONFIG_SYS_I2C framework
Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).

The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-07-16 19:56:24 +01:00
Shengzhou Liu
a17fd10fb5 fsl_i2c: add support for 3rd and 4th I2C
Add support for 3rd and 4th I2C.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-07-16 05:19:15 +02:00
Heiko Schocher
f7c1053535 i2c, omap24xx: add i2c deblock sequenz
If a bus busy is detected when intializing the driver,
toggle 9 times the scl pin. Therefore enable the test mode
of the controller, in which the scl, sda pins can be
controlled manually.

Tested on the siemens boards pxm2, rut and dxr2.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Lubomir Popov <lpopov@mm-sol.com>
Cc: Steve Sakoman <steve@sakoman.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Vincent Stehlé <v-stehle@ti.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
2014-07-16 05:18:55 +02:00
Felipe Balbi
5ba95541b7 usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x
Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-07-09 22:11:51 +02:00
Felipe Balbi
26707d9e6b usb: host: xhci: make sure to power up PHY
some boards won't work if the PHY isn't explicitly
powered up.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2014-07-09 22:11:51 +02:00
Dirk Eibach
3a990bfaea board: gdsys: Make gdsys osd hardware detection more robust
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2014-07-07 19:47:19 -04:00
Dirk Eibach
b46226bdb5 i2c: IHS I2C master driver
IHS I2C master support was merely a hack in the osd driver.
Now it is a proper u-boot I2C framework driver, supporting the
v2.00 master features.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2014-07-07 19:47:18 -04:00
Vasili Galka
0519e80d83 blackfin: Fix warning about undefined function
get_sclk() was not defined in bfin_wdt.c, include the corresponding header.

Cc: Sonic Zhang <sonic.adi@gmail.com>
Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-07-07 19:47:09 -04:00
Masahiro Yamada
b8c1438a7a mpc8xx: remove v37 board support
This board is old enough and has no maintainer.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-07 19:43:02 -04:00
Masahiro Yamada
c750b9c012 mpc8xx: remove rbc823 board support
This board is old enough and has no maintainer.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-07 19:43:02 -04:00
Masahiro Yamada
0657e46e28 mpc8xx: remove RPXlite_dw, quantum board support
These boards are old enough and have no maintainers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-07 19:43:01 -04:00
Jeroen Hofstee
49f9337956 tpm: don't use unneeded double brackets
clang is tempted to inteprete such a condition as a assignment
as well. Since it isn't don't use double brackets.

cc: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-07 19:43:01 -04:00
Masahiro Yamada
a8b0f9b685 build: define CPU only when arch/${ARCH}/cpu/${CPU} exists
The directory arch/${ARCH}/cpu/${CPU} does not exist
in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86.

These architectures have only one CPU type.
Defining CPU should not be required for such architectures.

This commit allows cpu field (= the 3rd field of boards.cfg)
to be kept blank.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
2014-07-07 19:42:34 -04:00
Tom Rini
6ee3d00d1d Merge branch 'master' of git://git.denx.de/u-boot-i2c 2014-07-07 10:10:52 -04:00
Stefan Roese
b70ed300b0 net: Rename and cleanup sunxi (Allwinner) emac driver
There have been 3 versions of the sunxi_emac support patch during its
development. Somehow version 2 ended up in upstream u-boot where as
the u-boot-sunxi git repo got version 3.

This bumps the version in upstream u-boot to version 3 of the patch:
- Initialize MII clock earlier so mii access to allow independent use
- Name change from WEMAC to EMAC to match mainline kernel & chip manual
- Cosmetic code cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
b6ae6765c5 sunxi: Remove mmc DMA support
The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the
dma descriptors on the stack, and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may
be re-used. So far we've gotten away with this by luck, but recent u-boot
changes have shifted the stack start address by 16 bytes, which combined
with dma alignment now exposes this problem.

Since we end up just busy waiting for the dma engine anyway, this commit
fixes things by simply removing the dma code, resulting in smaller bug-free
code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Chin Liang See
d8c67dc6e1 watchdog/denali: Adding DesignWare watchdog driver support
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file  within include/configs folder.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-07-05 00:24:16 +02:00
Sergey Kostanbaev
7237d22baa arm: ep9315: Return back Cirrus Logic EDB9315A board support
This patch returns back support for old ep93xx processors family

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
2014-07-04 23:45:48 +02:00
Axel Lin
c0c374024d gpio: spear_gpio: Fix gpio_set_value() implementation
In current gpio_set_value() implementation, it always sets the gpio control bit
no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
This patch fixes this bug.

The address bus is used as a mask on read/write operations, so that independent
software drivers can set their GPIO bits without affecting any other pins in a
single write operation. Thus we don't need a read-modify-write to update the
register.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2014-07-04 21:37:29 +02:00
J. German Rivera
b940ca64b2 armv8/fsl-lsch3: Add support to load and start MC Firmware
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
2014-07-03 08:40:58 +02:00
York Sun
2f78eae506 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-07-03 08:40:51 +02:00
Stephen Warren
ad3091ad03 i2c: tegra: dump alen in debug statements
Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump
the address length (alen) too, so the address value can be correctly
interpreted.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-07-03 06:29:39 +02:00
Stephen Warren
981b14f01a i2c: tegra: write clean data to TX FIFO
The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.

Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-07-03 06:29:31 +02:00
Stephen Warren
68049a082b i2c: tegra: use repeated start for reads
I2C read transactions are typically implemented as follows:

START(write) address REPEATED_START(read) data... STOP

However, Tegra's I2C driver currently implements reads as follows:

START(write) address STOP START(read) data... STOP

This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
2014-07-03 06:29:19 +02:00
Tom Rini
fe8b3212b7 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-07-02 16:38:02 -04:00
Stephen Warren
dcb89b5aa0 usb: ci_udc: use var name ep/ci_ep consistently
Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and
"ci_ep" for a struct ci_ep. This is nice and consistent, and helps people
know what type a variable is without searching for the declaration.
handle_ep_complete() doesn't do this, so fix it to be consistent.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
369d3c439a USB: gadget: atmel: zero out allocated requests
A UDC's alloc_request method should zero out the newly allocated request.
Ensure the Atmel driver does so. This issue was found by code inspection,
following the investigation of an intermittent issue with ci_udc, which
was tracked down to failing to zero out allocated requests following some
of my changes. All other UDC drivers already zero out requests in one
way or another.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
639e9903c2 usb: ci_udc: don't memalign() struct ci_req allocations
struct ci_req is a purely software structure, and needs no specific
memory alignment. Hence, allocate it with calloc() rather than
memalign(). The use of memalign() was left-over from when struct ci_req
was going to hold the aligned bounce buffer, but this is now dynamically
allocated.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
6ac15fda4e usb: ci_udc: remove controller.items array
There's no need to store an array of QTD pointers in the controller.
Since the calculation is so simple, just have ci_get_qtd() perform it
at run-time, rather than pre-calculating everything.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
7e54188775 usb: ci_udc: fix items array size/stride calculation
2 QTDs are allocated for each EP. The current allocation scheme aligns
the first QTD in each pair, but simply adds the struct size to calculate
the second QTD's address. This will result in a non-cache-aligned
addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the
size of struct ept_queue_item).

Similarly, the original ilist_ent_sz calculation aligned the value to
ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment
requirement into account. This doesn't cause a practical issue unless
ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may
as well fix the code to be explicit, so it's obviously completely
correct.

The new value of ILIST_ENT_SZ takes all alignment requirements into
account, so we can simplify ci_{flush,invalidate}_qtd() by simply using
that macro rather than calling roundup().

Similarly, the calculation of controller.items[i] can be simplified,
since each QTD is evenly spaced at its individual alignment requirement,
rather than each pair being aligned, and entries within the pair being
spaced apart only by structure size.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
06b38fcbae usb: ci_udc: lift ilist size calculations to global scope
This will allow functions other than ci_udc_probe() to make use of the
constants in a future change.

This in turn requires converting the const int variables to #defines,
since the initialization of one global const int can't depend on the
value of another const int; the compiler thinks it's non-constant if
that dependency exists.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
8d7c39d3e8 usb: ci_udc: don't assume QTDs are adjacent when transmitting ZLPs
Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly
call ci_get_qtd() to find the address of the other QTD to use. This
will allow us to correctly align each QTD individually in the future,
which may involve leaving a gap between the QTDs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Stephen Warren
d7beeb9358 usb: ci_udc: fix ci_flush_{qh,qtd} calls in ci_udc_probe()
ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After
each pair has been initialized, the pair is cache-flushed. The
conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index
[0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields
the QH/QTD index of the first entry in the pair) rather than dividing
by two (which scales the range). Fix this.

On my system, this avoids cache debug prints due to requests to flush
unaligned ranges. This is caused because the flush calls happen before
the items[] array entries are initialized for all but EP0.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-02 15:45:38 +02:00
Albert ARIBAUD
304f936aea Merge remote-tracking branch 'u-boot-samsung/master'
Conflicts:
	boards.cfg

Conflict was trivial between goni maintainer change and
lager_nor removal.
2014-07-01 20:52:51 +02:00
Albert ARIBAUD
e99f30e105 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-01 15:11:18 +02:00
Albert ARIBAUD
d6694aff56 Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-06-30 23:00:34 +02:00
Ilya Ledvich
08ebd467c8 usb: eth: smsc95xx: add LAN9500A device ID
Add LAN9500A product ID (0x9e00) in order to support LAN9500A based dongles.
Tested on cm_t335.

Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Acked-by: Marek Vasut <marex@denx.de>
2014-06-25 22:46:28 +02:00
Jeroen Hofstee
29425be49b usb: fastboot: fix potential buffer overflow
cb_getvar tries to prevent overflowing the response buffer
by using strncat. But strncat takes the number of data bytes
copied as a limit not the total buffer length so it can still
overflow. Pass the correct value instead.

cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
cc: Rob Herring <robh@kernel.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-06-25 22:44:40 +02:00
Jeroen Hofstee
25d1936a19 usb: xhci: (likely) fix bracket in if condition
Because of the brackets the & and && is evaluated before
the comparison. This is likely not the intention. Change
it to test the first and second condition to both be true.

cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-06-25 22:43:16 +02:00
Jeroen Hofstee
19a2a67fa2 usb:g_dnl:f_thor: remove memset before memcpy
since ALLOC_CACHE_ALIGN_BUFFER defines a pointer and not a
buffer, the memset with sizeof(rqt) likely does something else
then intended. Since there is a memcpy directly after it with
the full size, drop the memset completely.

Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
2014-06-25 22:42:40 +02:00
Jeroen Hofstee
933611f7bb usb:composite: clear the whole common buffer
Since the struct fsg_common is calloced, reset it completely
with zero's when reused. While at it, make checkpatch happy.

cc: Lukasz Majewski <l.majewski@samsung.com>
cc: Piotr Wilczek <p.wilczek@samsung.com>
cc: Kyungmin Park <kyungmin.park@samsung.com>
cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
2014-06-25 22:42:07 +02:00
Yasuhisa Umano
198c5f998a usb: r8a66597: Fix initilization size of r8a66597 info structure
Initialization of r8a66597 info structure is not enough.
Because initilization was used size of pointer.
This fixes that use size of r8a6659 info structure.

Signed-off-by: Yasuhisa Umano <yasuhisa.umano.zc@renesas.com>
2014-06-25 22:38:04 +02:00
yasuhisa umano
8ecdce7280 usb: r8a66597: Fix initialization hub that using R8A66597_MAX_ROOT_HUB
This driver is processed as two USB hub despite one.
The number of root hub is defined in R8A66597_MAX_ROOT_HUB.
This fixes that register is accessed by using the definition
of R8A66597_MAX_ROOT_HUB.

Signed-off-by: Yasuhisa Umano <yasuhisa.umano.zc@renesas.com>
2014-06-25 22:31:41 +02:00
Jeroen Hofstee
51afc2c68c usb: cosmetic: double const
For plain array const can be either before or after
the type definition. Adding both is simply redundand.
Remove the later one.

cc: marex@denx.de
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-06-25 22:22:20 +02:00
Stephen Warren
83c3750088 usb: ci_udc: fix typo in debug message
s/ot/to/

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-25 22:22:20 +02:00
Stephen Warren
fb22ae6c7e usb: ci_udc: fix interaction with CONFIG_USB_ETH_CDC
ci_udc.c's usb_gadget_unregister_driver() doesn't call driver->unbind()
unlike other USB gadget drivers. Fix it to do this.

Without this, when ether.c's CDC Ethernet device is torn down,
eth_unbind() is never called, so dev->gadget is never set to NULL.
For some reason, usb_eth_halt() is called both at the end of the first
use of the Ethernet device, and prior to any subsequent use. Since
dev->gadget is never cleared, all calls to usb_eth_halt() attempt to
stop, disconnect, and clean up the device, resulting in double cleanup,
which hangs U-Boot on my Tegra device at least.

ci_udc allocates its own singleton EP0 request object, and cleans it up
during usb_gadget_unregister_driver(). This appears necessary when using
the USB gadget framework in U-Boot, since that does not allocate/free
the EP0 request. However, the CDC Ethernet driver *does* allocate and
free its own EP0 requests. Consequently, we must protect
ci_ep_free_request() against double-freeing the request.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-25 22:22:20 +02:00
Albert ARIBAUD
ed1d98d801 Merge branch 'u-boot/master' into 'u-boot-arm/master' 2014-06-25 10:39:58 +02:00
Jeroen Hofstee
00d4796c55 PMIC: MAX77686: fix invalid bus check
Since p->bus is unsigned checking for negative values
is optimized away. Since bus is already used as an argument
use tmp. While at it, don't declare variables in the middle
of a function.

cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-23 10:04:13 +09:00
Akshay Saraswat
e76d2a81bc Exynos: SPI: Fix reading data from SPI flash
SPI recieve and transfer code in exynos_spi driver has a logical bug.
We read data in a variable which can hold an integer. Then we assign
this integer 32 bit value to another variable which has data type uchar.
Latter represents a unit of our recieve buffer. Everytime when we write
a value to our recieve buffer we step ahead by 4 units when actually we
wrote to one unit. This results in the loss of 3 bytes out of every 4
bytes recieved. This patch intends to fix this bug.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-06-23 07:47:05 +09:00
Simon Glass
89876a55a6 dm: Cast away the const-ness of the global_data pointer
In a very few cases we need to adjust the driver model root device, such as
when setting it up at initialisation. Add a macro to make this easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-20 11:55:49 -06:00
Simon Glass
6a6d8fbef7 dm: Add missing header files in lists and root
These files don't compile in some architectures. Fix it by adding the
missing headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-20 11:55:42 -06:00
Simon Glass
939cda5bf0 dm: Use case-insensitive comparison for GPIO banks
We want 'N0' and 'n0' to mean the same thing, so ensure that case is not
considered when naming GPIO banks.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-20 11:55:39 -06:00
Simon Glass
ae7f451308 dm: Rename struct device_id to udevice_id
It is best to avoid having any occurence of 'struct device' in driver
model, so rename to achieve this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-20 11:55:18 -06:00
Axel Lin
7a4861fad0 spi: davinci: Fix register address for SPI1_BUS
Fix a trivial copy-paste bug.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
2014-06-19 17:53:59 -04:00
Khoronzhuk, Ivan
909ea9aa26 ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.c
Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-06-19 17:53:58 -04:00
Khoronzhuk, Ivan
3e01ed00da mtd: nand: davinci: add header file for driver definitions
The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <trini@ti.com>
2014-06-19 17:53:58 -04:00
Jeroen Hofstee
a348d56934 pmic: tps65090: correct checking i2c bus
The function tps65090_init checks the i2c bus of p->bus. However
the pointer p is not intialiased at this point. Check the local
variable bus instead.

cc: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
2014-06-19 11:19:05 -04:00
Jeroen Hofstee
2b9912e6a7 includes: move openssl headers to include/u-boot
commit 18b06652cd "tools: include u-boot version of sha256.h"
unconditionally forced the sha256.h from u-boot to be used
for tools instead of the host version. This is fragile though
as it will also include the host version. Therefore move it
to include/u-boot to join u-boot/md5.h etc which were renamed
for the same reason.

cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-06-19 11:19:04 -04:00
Wu, Josh
b137bd8c8d video: atmel_hlcdfb: enable dcache support
To support dcache, we need flush DMA descriptor buffer before enable lcd
DMA.

Also we need call lcd_set_flush_dcache(1) to make lcd driver flush the
lcd buffer if there is any change.

Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-06-14 18:07:02 +02:00
Wu, Josh
5ae0e38278 net: macb: enable dcache in macb
Add to code to flush the dcache after we writing in DMA buffer.
Also we need invalidate the dcache before we check the status in the
DMA buffer.

Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below:
	Disable DCache: 1.1 MiB/s
	Enable DCache: 1.6 MiB/s
Increase speed with about 40%.

The code should have no impact with the boards which are not
enable_dcache().
Tested in AT91SAM9M10G45EK.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-06-14 18:07:01 +02:00
Andreas Bießmann
ceef983bf9 macb: make checkpatch clean
This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and
therefore don't need the CONFIG_SYS_ prefix.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Josh Wu <josh.wu@atmel.com>
2014-06-14 18:07:00 +02:00
Tom Rini
d8a97f934c Merge branch 'master' of git://git.denx.de/u-boot-mmc 2014-06-12 09:02:23 -04:00
Darwin Rambo
3d6a5a4dfc mmc: free allocated memory on initialization errors
Cleanup to balance malloc/free calls.

Signed-off-by: Darwin Rambo <drambo@broadcom.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-06-12 15:21:12 +03:00
Stephen Warren
d4622df342 mmc: return meaningful error codes from mmc_select_hwpart
Rather than just returning -1 everywhere, try to return something
meaningful from mmc_select_hwpart(). Note that most other MMC functions
don't do this, including functions called from mmc_select_hwpart(), so
I'm not sure how effective this will be. Still, it's one less place with
hard-coded -1.

Suggested-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-06-12 14:15:59 +03:00
Steve Rae
6736ec15c5 i2c: kona: Resolve Kona I2C driver issue
- "i2c mw" command hangs (with some compilers)

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-06-12 11:42:50 +02:00
Simon Glass
ddc94378db m68k: Fix warnings with gcc 4.6
Most of the warnings seem to be related to using 'int' for size_t. Change
this and fix up the remaining warnings and problems. For bootm, the warning
was masked by others, and there is an actual bug in the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-06-11 16:27:05 -04:00
Tom Rini
28b62f0de3 Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-06-11 11:40:11 -04:00
Tom Rini
61e76f5370 Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-06-10 20:37:00 -04:00
Lukasz Majewski
3d83e6752d dfu: Disable default calculation of CRC32
Patch (SHA1: bd694244db)
dfu: Introduction of the "dfu_hash_algo" env variable for checksum method
setting

already introduced more generic handling of the crc32 calculation.
Up till now the CRC32 of received data was calculated unconditionally.
This patch changes this and from now - by default the crc32 is NOT
calculated anymore.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
2014-06-11 02:31:48 +02:00
Stephen Warren
e0672b3c3a usb: ci_udc: terminate ep0 INs with a zlp when required
Sometimes, a zero-length packet is required at the end of an IN
transaction so that the host knows the device is done sending data.
Enhance ci_udc to send a zlp when necessary. See the comments for
more details.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-11 02:26:05 +02:00
Stephen Warren
b7c0051687 usb: ci_udc: clean up all allocations in unregister
usb_gadget_unregister_driver() is called to tear down the USB device mode
stack. Fix the driver to stop the USB HW (which causes any attached host
to notice the disappearance of the device), and free all allocations
(which obviously prevents memory leaks).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-11 02:26:05 +02:00
Stephen Warren
9a7d34be13 usb: ci_udc: fix probe error cleanup
If allocation of the ep0 req fails, clean up all the allocations that
were made in ci_udc_probe().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-11 02:26:05 +02:00
Stephen Warren
bdf81611e4 usb: ci_udc: fix freeing of ep0 req
ci_ep_alloc_request() avoids allocating multiple request objects for ep0
by keeping a record of the first req allocated for ep0, and always
returning that instead of allocating a new req. However, if this req is
ever freed, the record of the previous allocation is not cleared, so
ci_ep_alloc_request() will keep returning this stale pointer. Fix
ci_ep_free_request() to clear the record of the previous allocation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-11 02:26:05 +02:00
Stephen Warren
43a8f25b6c usb: ci_udc: call udc_disconnect() from ci_pullup()
ci_pullup()'s !is_on path contains a cut/paste copy of udc_disconnect().
Remove the duplication by simply calling udc_disconnect() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-11 02:26:05 +02:00
Nobuhiro Iwamatsu
1dbd7280dc net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF
'r' of rESR_RTLF is a mistake of E.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-06-10 17:05:03 +09:00
Nobuhiro Iwamatsu
e2752db052 net: sh-eth: Fix coding style
This fixes checkpatch's warning.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-06-10 17:05:03 +09:00
Nobuhiro Iwamatsu
62cbddc493 net: sh-eth: Add support R7S72100 of rmobile
The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-06-10 17:05:03 +09:00
Alison Wang
6b57ff6fd5 arm: vf610: Add QSPI driver support
Add Freescale QSPI driver support for VF610.

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
2014-06-09 09:18:09 +02:00
Poddar, Sourav
1f436a6ddf sf: probe: Fix quad bit set path
Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-06-08 23:12:27 +05:30
Andrew Ruder
c1c0dd2644 spi: soft_spi: Support NULL din/dout buffers
This mirrors the conventions used in other SPI drivers (kirkwood,
davinci, atmel, et al) where the din/dout buffer can be NULL when the
received/transmitted data isn't important.  This reduces the need for
allocating additional buffers when write-only/read-only functionality is
needed.

In the din == NULL case, the received data is simply not stored.  In the
dout == NULL case, zeroes are transmitted.

Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-06-08 23:12:27 +05:30
Siva Durga Prasad Paladugu
0472808608 sf: params: Added support for Spansion S25FL512S_512K
Added support for Spansion chip "S25FL512S_512K".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-06-08 23:12:27 +05:30
Tom Rini
55e8250bd3 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-06-08 07:58:41 -04:00
Tom Rini
86db550b38 power: Add support for the TPS65218 PMIC
Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and
may be used by TI AM335x SoCs.

Signed-off-by: Tom Rini <trini@ti.com>
2014-06-06 17:46:16 -04:00
Sourav Poddar
ce3cc8ecf5 ti: qspi: populate slave device to set flash quad bit.
The patch populates the slave data which will be used by flash driver to
set the  flash quad enable bit.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
2014-06-06 17:46:14 -04:00
pekon gupta
46840f66ca mtd: nand: omap: add support for BCH16_ECC - NAND driver updates
This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:10 -04:00
pekon gupta
b80a660338 mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL:    SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
        which is called before probing for devices, hence any ONFI parameter
        information is not available during GPMC initialization.

Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.

This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:06 -04:00
Brian Norris
27ce9e4290 mtd: nand: force NAND_CMD_READID onto 8-bit bus
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:03 -04:00
Brian Norris
b9ae609fdb mtd: nand: don't use read_buf for 8-bit ONFI transfers
Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author:     Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers

  Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
  devices, we need to avoid the upper I/O[16:9] bits. See the following
  commit for reference:

  commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
  Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  Date:   Thu Dec 5 22:22:04 2013 +0100

      mtd: nand: don't use {read,write}_buf for 8-bit transfers

  Now, I think that all barriers to probing ONFI on x16 devices are
  removed, so remove the check from nand_flash_detect_onfi().

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-06-06 17:46:01 -04:00
pekon gupta
3f990dc83b mtd: nand: omap: fix error-codes returned from omap-elm driver
This patch
 omap-elm.c: replaces -ve integer value returned during errorneous condition,
             with proper error-codes.
 omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
             omap-elm driver to upper layers

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:46:00 -04:00
pekon gupta
a09431da38 mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch
This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:57 -04:00
pekon gupta
9233279f8e mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info
This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemes

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:55 -04:00
pekon gupta
d21e77ff84 mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'
This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
 - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
 - remove nand_bch_priv.mode: <unused>

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:51 -04:00
pekon gupta
41bbe4dd49 mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16
ELM hardware engine support ECC error detection for multiple ECC strengths like
 +------+------------------------+
 |Type  | ECC syndrome length    |
 +------+------------------------+
 |BCH4  | 6.5 bytes = 13 nibbles |
 |BCH8  | 13 byte = 26 nibbles   |
 |BCH16 | 26 bytes = 52 nibbles  |
 +------+------------------------+

Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:48 -04:00
pekon gupta
b98c5755c0 mtd: nand: omap_elm: remove #include omap_gpmc.h
There is no dependency of omap_elm.c on omap_gpmc.h

Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-06-06 17:45:47 -04:00
Tim Harvey
ca84d72d1c dwc_ahsata: return failure for MX6 if not IMX6Q/IMX6D
The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return failure
instead of attempting a memory access that results in a data abort and reset.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:14:07 +02:00
Tim Harvey
73210dccdb spl: nand: add support for mxs nand
This utilizes existing mxs_nand support layer to provide a method to load an
image off nand for SPL. The flash device will be detected in order to support
multiple flash devices instead of having layout hard coded at build time.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:07:25 +02:00
Tom Rini
3e1fa221f9 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-06-05 17:38:30 -04:00
York Sun
353527d527 driver/ddr/fsl: Fix printing unspecified module info for DDR4
The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
York Sun
9855b3beca powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Hou Zhiqiang
afb907061a powerpc/espi: remove 80us delay to improve transfer performance
Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:20 -07:00
Cormier, Jonathan
08be2836df phy: fix create_phy_by_mask for when its given an actual search mask
get_phy_id returns -EIO when it can't read from a phy at a given addr.  This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.

Example usage:
Replace
    phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
    phydev = phy_find_by_mask(bus, phy_mask, phy_if)
    if (phydev)
	phy_connect_dev(phydev, dev);

Signed-off-by: Cormier, Jonathan <jcormier@criticallink.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
2014-06-05 14:44:56 -04:00
Albert ARIBAUD
cc49da249c Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-06-02 08:43:48 +02:00
Stephen Warren
006c702688 usb: ci_udc: complete ep0 direction handling
handle_setup() currently assumes that the response to a Setup transaction
will be an OUT transaction, and any subsequent packet (if any) will be an
IN transaction. This appears to be valid in many cases; both USB
enumeration and Mass Storage work OK with this restriction. However, DFU
uses ep0 to transfer data in both directions. This renders the assumption
invalid; when sending data from device to host, the Data Stage is an IN
transaction, and the Status Stage is an OUT transaction. Enhance
handle_setup() to deduce the correct direction for the USB transactions
based on Setup transaction data.

ep0's request object only needs to be automatically re-queued when the
Data Stage completes, in order to implement the Status Stage. Once the
Status Stage transaction is complete, there is no need to re-queue the
USB request, so don't do that.

Don't sent USB request completion callbacks for Status Stage transactions.
These were queued by ci_udc itself, and only serve to confuse the USB
function code. For example, f_dfu attempts to interpret the 0-length data
buffers for Status Stage transactions as DFU packets. These buffers
contain stale data from the previous transaction. This causes f_dfu to
complain about a sequence number mismatch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-01 19:22:40 +02:00
Stephen Warren
a2d8f92985 usb: ci_udc: pre-allocate ep0 req
Allocate ep0's USB request object when the UDC driver is probed. This
solves a couple of issues in the current code:

a) A request object always exists for ep0. Prior to this patch, if setup
transactions arrived in an unexpected order, handle_setup() would need
to reply to a setup transaction before any ep0 usb_req was created.

This issue was introduced in commit 2813006fec "usb: ci_udc: allow
multiple buffer allocs per ep."

b) handle_ep_complete no longer /has/ to queue the ep0 request again
after every single request completion. This is currently required, since
handle_setup() assumes it can find some request object in ep0's request
queue. This patch doesn't actually stop handle_ep_complete() from always
requeueing the request, but the next patch will.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-01 19:22:40 +02:00
Stephen Warren
054731b09e usb: ci_udc: use a single descriptor for ep0
ci_udc currently points ep->desc at separate descriptors for IN and OUT.
These descriptors only differ in the ep address IN/OUT field. Modify the
code to use a single descriptor, and change that descriptor's ep address
to indicate IN/OUT as required. This removes some data duplication.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-01 19:22:40 +02:00
Stephen Warren
7484d84cbb usb: ci_udc: detect queued requests on ep0
The flipping of ep0 between IN and OUT relies on ci_ep_queue() consuming
the current IN/OUT setting immediately. If this is deferred to a later
point when the req is pulled out of ci_req->queue, then the IN/OUT
setting may have been changed since the req was queued, and state will
get out of sync. This condition doesn't occur today, but could if bugs
were introduced later, and this error-check will save a lot of debugging
time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-06-01 19:22:39 +02:00
Lukasz Majewski
bd694244db dfu: Introduction of the "dfu_hash_algo" env variable for checksum method setting
Up till now the CRC32 of received data was calculated unconditionally.
The standard crc32 implementation causes long delay when large images
were uploaded.

The "dfu_hash_algo" environment variable gives the opportunity to
disable on demand the hash (crc32) calculation.
It can be done without the need to recompile the u-boot binary.

By default the crc32 is calculated, which means that legacy behavior
has been preserved.

Tests results:
400 MiB ums.img file
With 		crc32 calculation: 65 sec [avg 6.29 MB/s]
Without 		crc32 calculation: 25 sec [avg 16.17 MB/s]

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
2014-06-01 19:18:00 +02:00
Tom Rini
90b51c33f3 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-30 11:34:39 -04:00
Simon Glass
e1bf824dfd Add cli_ prefix to readline functions
This makes it clear where the code resides.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Simon Glass
18d66533ac move CLI prototypes to cli.h and add comments
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Eric Nelson
3a56482590 serial_mxc: disable new features of autobaud detection
Bit 7 of UCR3 is described in the i.MX3x/i.MX5x/i.MX6x
reference manuals as follows:

	Autobaud Detection Not Improved-. Disables new features of
	autobaud detection (See Baud Rate Automatic Detection
        Protocol, for more details).

	0 Autobaud detection new features selected
	1 Keep old autobaud detection mechanism

On at least i.MX6DQ, i.MX6DLS and i.MX53, the "new features"
occasionally cause the receiver to get out of sync and
continuously produce received characters of '\xff'.

This patch disables the "new feature" on all boards, since
there's no support for auto-baud in U-Boot on any of them.

More details are available in this post on i.MX Community:
	https://community.freescale.com/message/403254

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-05-28 17:37:47 +02:00
Aaron Durbin
0b259dc2e8 power: Explicitly select pmic device's bus
The current pmic i2c code assumes the current i2c bus is
the same as the pmic device's bus. There is nothing ensuring
that to be true. Therefore, select the proper bus before performing
a transaction.

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Tom Wai-Hong Tam
ac1058fdb7 power: Add support for TPS65090 PMU chip.
This adds driver support for the TPS65090 PMU. Support includes
hooking into the pmic infrastructure  so that the pmic commands
can be used on the console. The TPS65090 supports the following
functionality:

- fet enable/disable/querying
- getting and setting of charge state

Even though it is connected to the pmic infrastructure it does
not hook into the pmic charging charging infrastructure.

The device tree binding is from Linux, but only a small subset of
functionality is supported.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Simon Glass
78a36c3ef3 power: Add PMIC_ prefix to CHARGER_EN/DISABLE
This enum should be common across all PMICs rather than having it
independently defined with the same name in multiple places.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:18 +09:00
Simon Glass
913702ca39 power: Rename CONFIG_PMIC_... to CONFIG_POWER_...
Commit be3b51aa did this mostly, but several have been added since. Do the
job again.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:18 +09:00
Heiko Schocher
54c5d08a09 dm: rename device struct to udevice
using UBI and DM together leads in compiler error, as
both define a "struct device", so rename "struct device"
in include/dm/device.h to "struct udevice", as we use
linux code (MTD/UBI/UBIFS some USB code,...) and cannot
change the linux "struct device"

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
2014-05-27 10:21:32 -04:00
Wu, Josh
9902c7b6f1 mmc: atmel_mci: fix print incorrect buffer content for debug
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix checkpatch line length warning]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-27 00:10:46 +02:00
Wu, Josh
7d82d89772 gpio: at91: add sanity check for the NULL pointer
We need check the NULL pointer as at91_pio_get_port() may return NULL.

Also print a error message when at91_pio_get_port() failed otherwise we
cannot notice the failure.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-05-27 00:10:45 +02:00
Ian Campbell
49692c5f51 net/designware: Make DMA burst length configurable and reduce by default
The correct value for this setting can vary across SoCs and boards, so make it
configurable.

Also reduce the default value to 8, which is the same default as used in the
Linux driver.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
2014-05-25 17:23:58 +02:00
Ian Campbell
1857075a7f net/designware: reorder struct dw_eth_dev to pack more efficiently.
On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
> The {r,t}xbuffs fields also need to be aligned. Previously this was done
> implicitly because they immediately followed the descriptor tables. Make this
> explicit and also move to the head of the struct.

Looks like I managed to not actually commit the move of the field to the
head of the struct! v3.1 follows....

Ian.

8<------------

>From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Thu, 1 May 2014 19:45:15 +0100
Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
 efficiently.

The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.

Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.

The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
2014-05-25 17:23:48 +02:00
Ian Campbell
964ea7c1ce net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN
This is required at least on ARM.

When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
2014-05-25 17:23:15 +02:00
Ian Campbell
1c848a2586 net/designware: ensure device private data is DMA aligned.
struct dw_eth_dev contains fields which are accessed via DMA, so make sure it
is aligned to a dma boundary. Without this I see:
    ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-05-25 17:23:12 +02:00
Ian Campbell
e24ea55c04 sunxi: mmc support
On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > +	case 1:
> > +#if CONFIG_MMC1_PG

> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?

It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...

> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.

...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.

> Other than this please add my:
>
> Reviewed-by: Stefan Roese <sr@denx.de>

Thanks!

8<---------------------------------

>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support

This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Cc: Aaron Maoye <leafy.myeh@allwinnertech.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:26:43 +02:00
Albert ARIBAUD
c534d2fdcf Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2014-05-23 22:50:23 +02:00
Tom Rini
10dc77716f esdhc/usdhc: Fix warning when CONFIG_SYS_FSL_ESDHC_USE_PIO is not set
In 7168977 we made calls to check_and_invalidate_dcache_range()
conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO.  Only define this function
in this case as well.

Signed-off-by: Tom Rini <trini@ti.com>
2014-05-23 09:19:05 -04:00
Tom Rini
638b3e8342 Merge branch 'master' of git://git.denx.de/u-boot-mmc 2014-05-23 08:13:59 -04:00
Stephen Warren
d235628434 mmc: provide a select_hwpart implementation for get_device()
This enables specifying which eMMC HW partition to target for any U-Boot
command that uses the generic get_partition() function to parse its
command-line arguments.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-23 12:11:44 +03:00
Pierre Aubert
91fdabc67a eMMC: add support for operations in RPMB partition
This patch adds functions for read, write and authentication
key programming for the Replay Protected Memory Block partition
in the eMMC.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
2014-05-23 11:52:51 +03:00
Andrew Gabbasov
6b2221b008 mmc: Handle switch error status bit in MMC card status
MMC switch command for unsupported feature (e.g. bus width) sets a switch
error bit in card status. This bit should be checked, and, if it's set,
no access with new controller settings should be performed.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-05-23 11:34:33 +03:00
Mateusz Zalega
d803fea576 mmc: postponed needless timer initialization
mmc_init() doesn't call get_timer() anymore if MMC is already
initialized.

<panto> Minor formatting fix.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Mateusz Zalega <m.zalega@samsung.com>
2014-05-23 11:19:53 +03:00
Tom Rini
4d16f67e7b Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze 2014-05-22 14:38:19 -04:00
Tom Rini
f6ed9d5094 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-22 14:29:41 -04:00
Tom Rini
8e38128596 Merge branch 'pr-15052014' of git://git.denx.de/u-boot-usb 2014-05-22 13:42:26 -04:00
Tom Rini
c9afa7cea8 Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-05-22 12:56:15 -04:00
Ye.Li
716897760f esdhc/usdhc: Fix PIO mode bug in fsl_esdhc driver
When configure the fsl_esdhc driver to PIO mode by defining
"CONFIG_SYS_FSL_ESDHC_USE_PIO", the SD/MMC read and write will fail.

Two bugs in the driver to cause the issue:
1. The read buffer was invalidated after reading from DATAPORT register,
which should be only applied to DMA mode. The valid data in cache was
overwritten by physical memory.
2. The watermarks are not set in PIO mode, will cause according state not
be set.

Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
2014-05-22 18:52:45 +03:00
Siva Durga Prasad Paladugu
1a897668ac fpga: Added support to load bit stream from SD/MMC
Added support to load a bitstream image in chunks by reading it in
chunks from SD/MMC.
Command format:
loadfs [dev] [address] [image size] [blocksize] <interface>
       [<dev[:part]>] <filename>
Example: fpga loadfs 0 1000000 3dbafc 4000 mmc 0 fpga.bin

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
5b815c9c61 fpga: zynqpl: Clean partial bitstream handling
Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
7a78bd2679 fpga: Define bitstream type based on command selection
Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Albert ARIBAUD
05d134b084 Merge remote-tracking branch 'u-boot/master'
Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
2014-05-20 10:05:42 +02:00
Tom Rini
d7782d0653 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-05-16 18:30:33 -04:00
Nikhil Badola
15231f6dd1 drivers/usb : Define usb control register mask for w1c bits
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:27 -05:00
Chunhe Lan
f1a96ec1a9 fsl/pci: Add workaround for erratum A-005434
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:26 -05:00
Chunhe Lan
ffc8667acf net: phy/vitesse: Add support for VSC8664 phy module
This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-16 16:24:05 -05:00
Albert ARIBAUD
6a2f30a03a Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' 2014-05-16 17:56:50 +02:00
Albert ARIBAUD
a90bed77a6 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-05-16 16:49:50 +02:00
Jaehoon Chung
9b8c9a3c09 mmc: s5p_sdhci: add the s5p_sdhci_core_init function
To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
e09bd85329 mmc: exynos_dw_mmc: enable the DDR mode
Set the ddr mode capability by default.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
045bdcd0b2 mmc: dw_mmc: support the DDR mode
Support the DDR mode at dw-mmc controller

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
d22e3d46a9 mmc: support the DDR mode for eMMC
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
8caf46d189 mmc: remove the unnecessary define and fix the wrong bit control
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Lukasz Majeski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Jaehoon Chung
959198f7ca mmc: exynos_dw_mmc: restore the property into host
Restore the platdata(property of dt) into host struct.
Then data's information is maintained and reused anywhere.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Albert ARIBAUD
44cfc3a83f Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2014-05-15 17:19:45 +02:00
Albert ARIBAUD
9f5f51540d Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2014-05-15 16:36:02 +02:00
Stefano Babic
e7f9350525 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-05-15 10:27:32 +02:00
Lukasz Majewski
c8151b4a5d dfu: mmc: Provide support for eMMC boot partition access
Before this patch it was only possible to access the default eMMC HW
partition. By partition selection I mean the access to eMMC via the
ext_csd[179] register programming.

It sometimes happens that it is necessary to write to other partitions.
This patch adds extra attribute to "raw" sub type of the dfu_alt_info
environment variable (e.g. boot-mmc.bin raw 0x0 0x200 mmcpart 1;)

It saves the original boot value and restores it after storing the file.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-05-15 00:24:24 +02:00
Przemyslaw Marczak
584b55b072 usb:gadget:f_thor: download_tail(): remove dfu_write with 0 size
Since dfu_flush() can write raw data, dfu_write() with zero size
can be removed from download_tail() in thor gadget.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
2014-05-15 00:23:56 +02:00
Przemyslaw Marczak
1aa4bdc82d drivers:dfu: dfu_flush(): add raw data flush to complete dfu write
Before dfu write and flush operations separation,
dfu write data was flushed by host download request
with len of zero size.

Since above change manually calling dfu write with zero
size has non sense (e.g. in THOR). This should be done by
flush operation.
So now dfu_write_buffer_drain() is called in dfu_flush().
If there is any raw data to flush (like it can be in thor)
then it will be physically written to medium.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
2014-05-15 00:23:56 +02:00
Stephen Warren
8630c1c7e3 usb: ci_udc: parse QTD before over-writing it
ci_udc only allocates a single QTD structure per EP. All data needs to be
extracted from the DTD prior to calling ci_ep_submit_next_request(), since
that fills the QTD with next transaction's parameters. Fix
handle_ep_complete() to extract the transaction (remaining) length before
kicking off the next transaction.

In practice, this only causes writes to UMS devices to fail for me. I may
have tested the final versions of my previous ci_udc patch only with
reads. More recently, I had patches applied locally that allocated a QTD
per USB request rather than per USB EP, although since that doesn't give
any performance benefit, I'm dropping those.

Fixes: 2813006fec ("usb: ci_udc: allow multiple buffer allocs per ep")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-15 00:21:30 +02:00
Stephen Warren
a4539a2aa7 usb: tegra: support device mode
A few changes are made to the Tegra EHCI driver so that it can set
everything up for device-mode operation on the first USB controller.
This can be used in conjunction with ci_udc.c to operate as a USB
device.

Detailed changes are:

* Rename set_host_mode() to set_up_vbus() since that's really what it
  does.

* Modify set_up_vbus() to know whether it's initializing in host or
  device mode, and:

  - Skip the external VBUS check in device mode, since external VBUS is
    expected in this case.

  - Disable VBUS output in device mode.

* Modify init_phy_mux() to know whether it's initializing in host or
  device mode, and hence skip setting USBMODE_CM_HC (which enables host
  mode) in device mode. See the comments in that function for why this
  is safe w.r.t. the ordering requirements of PHY selection.

* Modify init_utmi_usb_controller() to force "b session valid" in device
  mode, since the HW requires this. This is done in UTMI-specific code,
  since we only support device mode on the first USB controller, and that
  controller can only talk to a UTMI PHY.

* Enhance ehci_hcd_init() to error-check the requested host-/device-mode
  vs. the dr_mode (dual-role mode) value present in device tree, and the
  HW configurations which support device mode.

* Enhance ehci_hcd_init() not to skip HW initialization when switching
  between host and device mode on a controller. This requires remembering
  which mode the last initialization used.

Cc: Jim Lin <jilin@nvidia.com>
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-15 00:21:17 +02:00
Stephen Warren
2d34151f75 usb: tegra: refactor PHY type selection
Both init_{utmi,ulpi}_usb_controller() have nearly identical code for
PHY type selection. Pull this out into a common function to remove the
duplication.

Cc: Jim Lin <jilin@nvidia.com>
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-15 00:21:17 +02:00
Stephen Warren
9b20fe6f1a usb: tegra: fix PHY selection code
The TRM for Tegra30 and later all state that USBMODE_CM_HC must be set
before writing to hostpc1_devlc to select which PHY to use for a USB
controller. However, neither init_{utmi,ulpi}_usb_controller() do this
today, so the register writes they perform for PHY selection do not
work.

For the UTMI case, this was hacked around in commit 7e44d9320e "ARM:
Tegra: USB: EHCI: Add support for Tegra30/Tegra114" by adding code to
ehci_hcd_init() which sets USBMODE_CM_HC and duplicates the PHY
selection register write. This code doesn't cover the ULPI case, so I
wouldn't be surprised if ULPI doesn't work with the current code, unless
the ordering requirement only ends up being an issue in HW for UTMI not
ULPI.

This patch fixes init_{utmi,ulpi}_usb_controller() to correctly set
USBMODE_CM_HC before selecting the PHY. Now that this works, we can
remove the duplicate UTMI-specific code in ehci_hcd_init(), thus
simplifying that function.

Cc: Jim Lin <jilin@nvidia.com>
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-05-15 00:21:17 +02:00
Marek Vasut
4180b3dba2 Merge remote-tracking branch 'u-boot/master' into test 2014-05-15 00:20:54 +02:00
Hans de Goede
2072e72629 mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globals
These are used only once, so their is no need to have them global.

This also stops mvtwsi from using any bss vars making it easier to use
before dram init (to talk to the pmic to set the dram voltage).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-05-14 12:59:12 +02:00
Hans de Goede
fab356a0b8 mvtwsi: Fix clock programming
The TWSI_FREQUENCY macro was wrong in 2 ways:
1) It was casting the result of the calculations to an u8, while i2c clk
rates are often >= 100Khz which won't fit in a u8, drop the cast.
2) It had an extra factor of 2 in the divider which neither the datasheet nor
the Linux driver have.

The comment for the default value was wrongly saying that m lives in
bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct
shift by 3 used in i2c_init().

While at it remove the unused twsi_actual_speed variable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-05-14 12:58:55 +02:00
Michal Simek
eb8c54bfaa ARM: zynq: ehci: Added USB host driver support
Added USB host driver for zynq.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-14 07:43:35 +02:00
Belisko Marek
97eeae1a07 mtd: nand: omap_gpmc: Fix update of read_ecc in oob
We need to flip only one bit not assign.

Signed-off-by: Marek Belisko <marek.belisko@gmail.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-05-13 19:48:17 -04:00
Tom Rini
557a331908 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-05-13 17:09:28 -04:00
Stephen Warren
eceb3f26f4 ARM: tegra: add GPIO initialization table function
The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Stephen Warren
f175603f7c ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICE
If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.

A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE

1) It isn't documented in README. The same is true for a lot of similar
   defines used by api_storage.c.

2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
   valid values are 0..n-1 not 0..n.

However, I this patch does not address those shortcomings.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-05-13 10:41:31 -07:00
Zhao Qiang
ca721fb292 qe: disable qe when qe-ucode fails to be uploaded for "deep sleep"
when qe-ucode fails to be uploaded, "deep sleep" will hang.
if there is no qe-ucode, disable qe module for platforms
which support "deep sleep"

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2014-05-13 08:26:56 -07:00
Shengzhou Liu
5122dfae5d powerpc/85xx: add T4080 SoC support
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-13 08:26:54 -07:00
Shaohui Xie
3a7ed5aa23 powerpc/fman/memac: use default MDIO_HOLD value
Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO
access, this is due to an errata A-006260 on T4 rev1.0 which is fixed
on rev2.0, so remove the maximum value to use the default value for rev2.0.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2014-05-13 08:26:54 -07:00
Chunhe Lan
0b2e13d9cc powerpc/85xx: Add T4240RDB board support
T4240RDB board Specification
----------------------------
Memory subsystem:
   6GB DDR3
   128MB NOR flash
   2GB NAND flash

Ethernet:
   Eight 1G SGMII ports
   Four 10Gbps SFP+ ports

PCIe:
   Two PCIe slots

USB:
   Two USB2.0 Type A ports

SDHC:
   One SD-card port

SATA:
   One SATA port

UART:
   Dual RJ45 ports

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
2014-05-13 08:24:32 -07:00
Tom Rini
27b4e4b991 Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze 2014-05-13 07:34:08 -04:00
Tom Rini
e7d4a88e69 Merge branch 'master' of git://git.denx.de/u-boot-video 2014-05-13 07:31:00 -04:00
Siva Durga Prasad Paladugu
3108185985 fpga: zynq: Use helper function zynq_validate_bitstream
Use helper function zynq_validate_bitstream so that the
code can be reused easily for different cases of dma transfer.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:14:05 +02:00