mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
a90bed77a6
2
Makefile
2
Makefile
|
|
@ -890,7 +890,7 @@ MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \
|
|||
spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
|
||||
$(call if_changed,mkimage)
|
||||
|
||||
OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE)
|
||||
OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
|
||||
u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
|
||||
$(call if_changed,pad_cat)
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,8 @@
|
|||
#define MODULE_CLKCTRL_IDLEST_DISABLED 3
|
||||
|
||||
/* CM_CLKMODE_DPLL */
|
||||
#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
|
||||
#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
|
||||
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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||||
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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||||
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
|
||||
|
|
|
|||
|
|
@ -322,6 +322,9 @@
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|||
|
||||
#define V_SCLK V_OSCK
|
||||
|
||||
/* CKO buffer control */
|
||||
#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
|
||||
|
||||
/* AUXCLKx reg fields */
|
||||
#define AUXCLK_ENABLE_MASK (1 << 8)
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||||
#define AUXCLK_SRCSELECT_SHIFT 1
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||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@
|
|||
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
|
||||
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
|
||||
#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
|
||||
#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000)
|
||||
|
||||
/* General Purpose Timers */
|
||||
#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
|
||||
|
|
|
|||
13
board/gumstix/pepper/Makefile
Normal file
13
board/gumstix/pepper/Makefile
Normal file
|
|
@ -0,0 +1,13 @@
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|||
#
|
||||
# Makefile
|
||||
#
|
||||
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
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||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += mux.o
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||||
endif
|
||||
|
||||
obj-y += board.o
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||||
226
board/gumstix/pepper/board.c
Normal file
226
board/gumstix/pepper/board.c
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
/*
|
||||
* Board functions for Gumstix Pepper and AM335x-based boards
|
||||
*
|
||||
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
|
||||
* Based on board/ti/am335x/board.c from Texas Instruments, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
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||||
#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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||||
#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <asm/arch/sys_proto.h>
|
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#include <asm/arch/mem.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <cpsw.h>
|
||||
#include <power/tps65217.h>
|
||||
#include <environment.h>
|
||||
#include <watchdog.h>
|
||||
#include "board.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
|
||||
(MT47H128M16RT25E_RD_DQS<<20) |
|
||||
(MT47H128M16RT25E_RD_DQS<<10) |
|
||||
(MT47H128M16RT25E_RD_DQS<<0)),
|
||||
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
|
||||
(MT47H128M16RT25E_WR_DQS<<20) |
|
||||
(MT47H128M16RT25E_WR_DQS<<10) |
|
||||
(MT47H128M16RT25E_WR_DQS<<0)),
|
||||
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
|
||||
(MT47H128M16RT25E_PHY_WRLVL<<20) |
|
||||
(MT47H128M16RT25E_PHY_WRLVL<<10) |
|
||||
(MT47H128M16RT25E_PHY_WRLVL<<0)),
|
||||
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
|
||||
(MT47H128M16RT25E_PHY_GATELVL<<20) |
|
||||
(MT47H128M16RT25E_PHY_GATELVL<<10) |
|
||||
(MT47H128M16RT25E_PHY_GATELVL<<0)),
|
||||
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
|
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
|
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
|
||||
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
|
||||
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
|
||||
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
|
||||
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
|
||||
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr2_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT47H128M16RT25E_RATIO,
|
||||
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT47H128M16RT25E_RATIO,
|
||||
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT47H128M16RT25E_RATIO,
|
||||
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static const struct emif_regs ddr2_emif_reg_data = {
|
||||
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
|
||||
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
return serial_tstc() && serial_getc() == 'c';
|
||||
}
|
||||
#endif
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
return &dpll_ddr;
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
enable_uart0_pin_mux();
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
const struct ctrl_ioregs ioregs = {
|
||||
.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
config_ddr(266, &ioregs, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
hw_watchdog_init();
|
||||
#endif
|
||||
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
gpmc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 0,
|
||||
.phy_if = PHY_INTERFACE_MODE_RGMII,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
const char *devname;
|
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid0l);
|
||||
mac_hi = readl(&cdev->macid0h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
if (is_valid_ether_addr(mac_addr))
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||
}
|
||||
|
||||
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
|
||||
/*
|
||||
*
|
||||
* CPSW RGMII Internal Delay Mode is not supported in all PVT
|
||||
* operating points. So we must set the TX clock delay feature
|
||||
* in the KSZ9021 PHY. Since we only support a single ethernet
|
||||
* device in U-Boot, we only do this for the current instance.
|
||||
*/
|
||||
devname = miiphy_get_current_dev();
|
||||
/* max rx/tx clock delay, min rx/tx control delay */
|
||||
miiphy_write(devname, 0x0, 0x0b, 0x8104);
|
||||
miiphy_write(devname, 0x0, 0xc, 0xa0a0);
|
||||
|
||||
/* min rx data delay */
|
||||
miiphy_write(devname, 0x0, 0x0b, 0x8105);
|
||||
miiphy_write(devname, 0x0, 0x0c, 0x0000);
|
||||
|
||||
/* min tx data delay */
|
||||
miiphy_write(devname, 0x0, 0x0b, 0x8106);
|
||||
miiphy_write(devname, 0x0, 0x0c, 0x0000);
|
||||
|
||||
return n;
|
||||
}
|
||||
#endif
|
||||
19
board/gumstix/pepper/board.h
Normal file
19
board/gumstix/pepper/board.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Gumstix Pepper and AM335x-based boards information header
|
||||
*
|
||||
* Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* We must be able to enable uart0, for initial output. We then have a
|
||||
* main pinmux function that can be overridden to enable all other pinmux that
|
||||
* is required on the board.
|
||||
*/
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
#endif
|
||||
78
board/gumstix/pepper/mux.c
Normal file
78
board/gumstix/pepper/mux.c
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Muxing for Gumstix Pepper and AM335x-based boards
|
||||
*
|
||||
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include "board.h"
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
/* I2C_DATA */
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
/* I2C_SCLK */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rgmii1_pin_mux[] = {
|
||||
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
|
||||
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
|
||||
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
|
||||
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
|
||||
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
|
||||
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
|
||||
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
|
||||
{OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
|
||||
{OFFSET(xdma_event_intr1), MODE(3)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do board-specific muxes.
|
||||
*/
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
/* I2C0 */
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
/* SD Card */
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
/* Ethernet pinmux. */
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
}
|
||||
|
|
@ -128,12 +128,6 @@ do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
button = 0;
|
||||
|
||||
gpio_free(gpio);
|
||||
if (!button) {
|
||||
/* LED0 - RED=1: GPIO2_0 2*32 = 64 */
|
||||
gpio_request(BOARD_DFU_BUTTON_LED, "");
|
||||
gpio_direction_output(BOARD_DFU_BUTTON_LED, 1);
|
||||
gpio_set_value(BOARD_DFU_BUTTON_LED, 1);
|
||||
}
|
||||
|
||||
return button;
|
||||
}
|
||||
|
|
@ -144,6 +138,46 @@ U_BOOT_CMD(
|
|||
""
|
||||
);
|
||||
#endif
|
||||
/*
|
||||
* This command sets led
|
||||
* Input - name of led
|
||||
* value of led
|
||||
* Returns - 1 if input does not match
|
||||
* 0 if led was set
|
||||
*/
|
||||
static int
|
||||
do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int gpio = 0;
|
||||
if (argc != 3)
|
||||
goto exit;
|
||||
#if defined(BOARD_STATUS_LED)
|
||||
if (!strcmp(argv[1], "stat"))
|
||||
gpio = BOARD_STATUS_LED;
|
||||
#endif
|
||||
#if defined(BOARD_DFU_BUTTON_LED)
|
||||
if (!strcmp(argv[1], "dfu"))
|
||||
gpio = BOARD_DFU_BUTTON_LED;
|
||||
#endif
|
||||
/* If argument does not mach exit */
|
||||
if (gpio == 0)
|
||||
goto exit;
|
||||
gpio_request(gpio, "");
|
||||
gpio_direction_output(gpio, 1);
|
||||
if (!strcmp(argv[2], "1"))
|
||||
gpio_set_value(gpio, 1);
|
||||
else
|
||||
gpio_set_value(gpio, 0);
|
||||
return 0;
|
||||
exit:
|
||||
return 1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
led, CONFIG_SYS_MAXARGS, 2, do_setled,
|
||||
"Set led on or off",
|
||||
"dfu val - set dfu led\nled stat val - set status led"
|
||||
);
|
||||
|
||||
static int
|
||||
do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Board functions for TI AM335X based dxr2 board
|
||||
* Board functions for TI AM335X based draco board
|
||||
* (C) Copyright 2013 Siemens Schweiz AG
|
||||
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
|
|
@ -37,13 +37,27 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
|
||||
/* @303MHz-i0 */
|
||||
static struct draco_baseboard_id __attribute__((section(".data"))) settings;
|
||||
|
||||
#if DDR_PLL_FREQ == 303
|
||||
/* Default@303MHz-i0 */
|
||||
const struct ddr3_data ddr3_default = {
|
||||
0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
|
||||
0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
|
||||
0x00000618, 0x0000014A,
|
||||
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
|
||||
0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
|
||||
0x0000093B, 0x0000014A,
|
||||
"default name @303MHz \0",
|
||||
"default marking \0",
|
||||
};
|
||||
#elif DDR_PLL_FREQ == 400
|
||||
/* Default@400MHz-i0 */
|
||||
const struct ddr3_data ddr3_default = {
|
||||
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
|
||||
0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
|
||||
0x00000618, 0x0000014A,
|
||||
"default name @400MHz \0",
|
||||
"default marking \0",
|
||||
};
|
||||
#endif
|
||||
|
||||
static void set_default_ddr3_timings(void)
|
||||
{
|
||||
|
|
@ -53,8 +67,12 @@ static void set_default_ddr3_timings(void)
|
|||
|
||||
static void print_ddr3_timings(void)
|
||||
{
|
||||
printf("\n\nDDR3 Timing parameters:\n");
|
||||
printf("Diff Eeprom Default\n");
|
||||
printf("\nDDR3\n");
|
||||
printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
|
||||
printf("device:\t\t%s\n", settings.ddr3.manu_name);
|
||||
printf("marking:\t%s\n", settings.ddr3.manu_marking);
|
||||
printf("timing parameters\n");
|
||||
printf("diff\teeprom\tdefault\n");
|
||||
PRINTARGS(magic);
|
||||
PRINTARGS(version);
|
||||
PRINTARGS(ddr3_sratio);
|
||||
|
|
@ -78,9 +96,9 @@ static void print_ddr3_timings(void)
|
|||
|
||||
static void print_chip_data(void)
|
||||
{
|
||||
printf("\n");
|
||||
printf("Device: '%s'\n", settings.chip.sdevname);
|
||||
printf("HW version: '%s'\n", settings.chip.shwver);
|
||||
printf("\nCPU BOARD\n");
|
||||
printf("device: \t'%s'\n", settings.chip.sdevname);
|
||||
printf("hw version: \t'%s'\n", settings.chip.shwver);
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
|
|
@ -112,20 +130,18 @@ static int read_eeprom(void)
|
|||
printf("Using DDR3 settings from EEPROM\n");
|
||||
} else {
|
||||
if (ddr3_default.magic != settings.ddr3.magic)
|
||||
printf("Error: No valid DDR3 data in eeprom.\n");
|
||||
printf("Warning: No valid DDR3 data in eeprom.\n");
|
||||
if (ddr3_default.version != settings.ddr3.version)
|
||||
printf("Error: DDR3 data version does not match.\n");
|
||||
printf("Warning: DDR3 data version does not match.\n");
|
||||
|
||||
printf("Using default settings\n");
|
||||
set_default_ddr3_timings();
|
||||
}
|
||||
|
||||
if (MAGIC_CHIP == settings.chip.magic) {
|
||||
printf("Valid chip data in eeprom\n");
|
||||
if (MAGIC_CHIP == settings.chip.magic)
|
||||
print_chip_data();
|
||||
} else {
|
||||
printf("Error: No chip data in eeprom\n");
|
||||
}
|
||||
else
|
||||
printf("Warning: No chip data in eeprom\n");
|
||||
|
||||
print_ddr3_timings();
|
||||
#endif
|
||||
|
|
@ -135,48 +151,48 @@ static int read_eeprom(void)
|
|||
#ifdef CONFIG_SPL_BUILD
|
||||
static void board_init_ddr(void)
|
||||
{
|
||||
struct emif_regs dxr2_ddr3_emif_reg_data = {
|
||||
struct emif_regs draco_ddr3_emif_reg_data = {
|
||||
.zq_config = 0x50074BE4,
|
||||
};
|
||||
|
||||
struct ddr_data dxr2_ddr3_data = {
|
||||
struct ddr_data draco_ddr3_data = {
|
||||
};
|
||||
|
||||
struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
|
||||
struct cmd_control draco_ddr3_cmd_ctrl_data = {
|
||||
};
|
||||
|
||||
struct ctrl_ioregs dxr2_ddr3_ioregs = {
|
||||
struct ctrl_ioregs draco_ddr3_ioregs = {
|
||||
};
|
||||
|
||||
/* pass values from eeprom */
|
||||
dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
|
||||
dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
|
||||
dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
|
||||
dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
|
||||
draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
|
||||
draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
|
||||
draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
|
||||
draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
|
||||
settings.ddr3.emif_ddr_phy_ctlr_1;
|
||||
dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
|
||||
dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
|
||||
draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
|
||||
draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
|
||||
|
||||
dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
|
||||
dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
|
||||
dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
|
||||
dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
|
||||
draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
|
||||
draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
|
||||
draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
|
||||
draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
|
||||
|
||||
dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
|
||||
dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
|
||||
dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
|
||||
dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
|
||||
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
|
||||
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
|
||||
draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
|
||||
draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
|
||||
draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
|
||||
draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
|
||||
draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
|
||||
draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
|
||||
|
||||
dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
|
||||
dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
|
||||
dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
|
||||
dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
|
||||
dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
|
||||
draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
|
||||
draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
|
||||
draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
|
||||
draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
|
||||
draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
|
||||
|
||||
config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
|
||||
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
|
||||
config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
|
||||
&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
|
||||
}
|
||||
|
||||
static void spl_siemens_board_init(void)
|
||||
|
|
@ -22,24 +22,26 @@
|
|||
#define MAGIC_CHIP 0x50494843
|
||||
|
||||
/* Automatic generated definition */
|
||||
/* Wed, 18 Sep 2013 18:58:27 +0200 */
|
||||
/* From file: draco/ddr3-data-micron-v2.txt */
|
||||
/* Wed, 16 Apr 2014 16:50:41 +0200 */
|
||||
/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
|
||||
struct ddr3_data {
|
||||
unsigned int magic; /* 0x33524444 */
|
||||
unsigned int version; /* 0x56312e34 */
|
||||
unsigned short int ddr3_sratio; /* 0x0100 */
|
||||
unsigned short int iclkout; /* 0x0001 */
|
||||
unsigned int version; /* 0x56312e35 */
|
||||
unsigned short int ddr3_sratio; /* 0x0080 */
|
||||
unsigned short int iclkout; /* 0x0000 */
|
||||
unsigned short int dt0rdsratio0; /* 0x003A */
|
||||
unsigned short int dt0wdsratio0; /* 0x008A */
|
||||
unsigned short int dt0fwsratio0; /* 0x010B */
|
||||
unsigned short int dt0wrsratio0; /* 0x00C4 */
|
||||
unsigned short int dt0wdsratio0; /* 0x003F */
|
||||
unsigned short int dt0fwsratio0; /* 0x009F */
|
||||
unsigned short int dt0wrsratio0; /* 0x0079 */
|
||||
unsigned int sdram_tim1; /* 0x0888A39B */
|
||||
unsigned int sdram_tim2; /* 0x26247FDA */
|
||||
unsigned int sdram_tim3; /* 0x501F821F */
|
||||
unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
|
||||
unsigned int sdram_config; /* 0x61C04AB2 */
|
||||
unsigned int ref_ctrl; /* 0x00000618 */
|
||||
unsigned int ioctr_val; /* 0x0000018B */
|
||||
unsigned int sdram_config; /* 0x61A44A32 */
|
||||
unsigned int ref_ctrl; /* 0x0000093B */
|
||||
unsigned int ioctr_val; /* 0x0000014A */
|
||||
char manu_name[32]; /* "default@303MHz \0" */
|
||||
char manu_marking[32]; /* "default \0" */
|
||||
};
|
||||
|
||||
struct chip_data {
|
||||
|
|
@ -48,7 +50,7 @@ struct chip_data {
|
|||
char shwver[7];
|
||||
};
|
||||
|
||||
struct dxr2_baseboard_id {
|
||||
struct draco_baseboard_id {
|
||||
struct ddr3_data ddr3;
|
||||
struct chip_data chip;
|
||||
};
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* pinmux setup for siemens dxr2 board
|
||||
* pinmux setup for siemens draco board
|
||||
*
|
||||
* (C) Copyright 2013 Siemens Schweiz AG
|
||||
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
|
|
@ -70,11 +70,11 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
|
|||
};
|
||||
|
||||
const struct ctrl_ioregs ioregs = {
|
||||
.cm0ioctl = DXR2_IOCTRL_VAL,
|
||||
.cm1ioctl = DXR2_IOCTRL_VAL,
|
||||
.cm2ioctl = DXR2_IOCTRL_VAL,
|
||||
.dt0ioctl = DXR2_IOCTRL_VAL,
|
||||
.dt1ioctl = DXR2_IOCTRL_VAL,
|
||||
.cm0ioctl = DDR_IOCTRL_VAL,
|
||||
.cm1ioctl = DDR_IOCTRL_VAL,
|
||||
.cm2ioctl = DDR_IOCTRL_VAL,
|
||||
.dt0ioctl = DDR_IOCTRL_VAL,
|
||||
.dt1ioctl = DDR_IOCTRL_VAL,
|
||||
};
|
||||
|
||||
config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
|
||||
|
|
|
|||
|
|
@ -400,7 +400,7 @@ static int conf_disp_pll(int m, int n)
|
|||
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
|
||||
writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
|
||||
writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
|
||||
writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
|
||||
writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
|
||||
&cmwkup->clkmoddplldisp); /* 0x98 */
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -257,10 +257,12 @@ Active arm armv7 am33xx BuR tseries
|
|||
Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
|
||||
Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
|
||||
Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
|
||||
Active arm armv7 am33xx gumstix pepper pepper - Ash Charles <ash@gumstix.com>
|
||||
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
|
||||
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
|
||||
Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
|
||||
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx siemens draco draco - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx siemens draco dxr2 - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
|
||||
|
|
|
|||
|
|
@ -403,7 +403,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
|
|||
dat[byte_pos] ^= 1 << bit_pos;
|
||||
printf("nand: bit-flip corrected @data=%d\n", byte_pos);
|
||||
} else if (byte_pos < error_max) {
|
||||
read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos;
|
||||
read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
|
||||
printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
|
||||
SECTOR_BYTES);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -386,6 +386,7 @@
|
|||
#define CONFIG_SPL_STACK 0x8001ff00
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80000000
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT 32768
|
||||
#define CONFIG_SPL_PAD_TO 32768
|
||||
#endif
|
||||
|
||||
/* Load U-Boot Image From MMC */
|
||||
|
|
|
|||
92
include/configs/draco.h
Normal file
92
include/configs/draco.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2013 Siemens Schweiz AG
|
||||
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* Based on:
|
||||
* U-Boot file:/include/configs/am335x_evm.h
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_DRACO_H
|
||||
#define __CONFIG_DRACO_H
|
||||
|
||||
#define CONFIG_SIEMENS_DRACO
|
||||
#define MACH_TYPE_DRACO 4314
|
||||
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO
|
||||
|
||||
#include "siemens-am33x-common.h"
|
||||
|
||||
#define CONFIG_SYS_MPUCLK 275
|
||||
#define DDR_PLL_FREQ 303
|
||||
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
|
||||
|
||||
#define BOARD_DFU_BUTTON_GPIO 27
|
||||
#define BOARD_DFU_BUTTON_LED 64 /* red LED */
|
||||
#define BOARD_STATUS_LED 103 /* green LED */
|
||||
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
|
||||
|
||||
#undef CONFIG_DOS_PARTITION
|
||||
#undef CONFIG_CMD_FAT
|
||||
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define EEPROM_ADDR_DDR3 0x90
|
||||
#define EEPROM_ADDR_CHIP 0x120
|
||||
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
|
||||
|
||||
#undef CONFIG_SPL_NET_SUPPORT
|
||||
#undef CONFIG_SPL_NET_VCI_STRING
|
||||
#undef CONFIG_SPL_ETH_SUPPORT
|
||||
|
||||
#undef CONFIG_MII
|
||||
#undef CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#define CONFIG_FACTORYSET
|
||||
|
||||
/* Watchdog */
|
||||
#define CONFIG_OMAP_WATCHDOG
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
/* Default env settings */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"nand_img_size=0x400000\0" \
|
||||
"optargs=\0" \
|
||||
CONFIG_COMMON_ENV_SETTINGS
|
||||
|
||||
#ifndef CONFIG_RESTORE_FLASH
|
||||
/* set to negative value for no autoboot */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if dfubutton; then " \
|
||||
"run dfu_start; " \
|
||||
"reset; " \
|
||||
"fi;" \
|
||||
"run nand_boot;" \
|
||||
"reset;"
|
||||
|
||||
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 0
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv autoload no; " \
|
||||
"dhcp; " \
|
||||
"if tftp 80000000 debrick.scr; then " \
|
||||
"source 80000000; " \
|
||||
"fi"
|
||||
#endif
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
#endif /* ! __CONFIG_DRACO_H */
|
||||
|
|
@ -20,12 +20,12 @@
|
|||
#include "siemens-am33x-common.h"
|
||||
|
||||
#define CONFIG_SYS_MPUCLK 275
|
||||
#define DXR2_IOCTRL_VAL 0x18b
|
||||
#define DDR_PLL_FREQ 303
|
||||
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
|
||||
|
||||
#define BOARD_DFU_BUTTON_GPIO 27
|
||||
#define BOARD_DFU_BUTTON_LED 64
|
||||
#define BOARD_DFU_BUTTON_LED 64 /* red LED */
|
||||
#define BOARD_STATUS_LED 103 /* green LED */
|
||||
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
|
||||
|
||||
#undef CONFIG_DOS_PARTITION
|
||||
|
|
|
|||
|
|
@ -165,6 +165,7 @@
|
|||
#define CONFIG_CMD_EEPROM
|
||||
|
||||
/* U-Boot general configuration */
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_SYS_PROMPT "K2HK EVM # "
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SYS_PBSIZE 2048
|
||||
|
|
|
|||
|
|
@ -170,11 +170,17 @@
|
|||
"if test $beaglerev = C4; then " \
|
||||
"setenv fdtfile omap3-beagle.dtb; fi; " \
|
||||
"if test $beaglerev = xMAB; then " \
|
||||
"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
|
||||
"setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \
|
||||
"if test $beaglerev = xMC; then " \
|
||||
"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
|
||||
"if test $fdtfile = undefined; then " \
|
||||
"echo WARNING: Could not determine device tree to use; fi; \0" \
|
||||
"validatefdt=" \
|
||||
"if test $beaglerev = xMAB; then " \
|
||||
"if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
|
||||
"setenv fdtfile omap3-beagle-xm.dtb; " \
|
||||
"fi; " \
|
||||
"fi; \0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
|
|
@ -190,7 +196,7 @@
|
|||
"rootfstype=${ramrootfstype}\0" \
|
||||
"loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
|
||||
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
||||
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
|
|
|||
99
include/configs/pepper.h
Normal file
99
include/configs/pepper.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PEPPER_H
|
||||
#define __CONFIG_PEPPER_H
|
||||
|
||||
#define CONFIG_MMC
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
#undef CONFIG_BOARD_LATE_INIT
|
||||
#undef CONFIG_SPL_OS_BOOT
|
||||
|
||||
/* Clock defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#undef CONFIG_SYS_PROMPT
|
||||
#define CONFIG_SYS_PROMPT "pepper# "
|
||||
|
||||
/* Mach type */
|
||||
#define MACH_TYPE_PEPPER 4207 /* Until the next sync */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
|
||||
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
/* Display cpuinfo */
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
DEFAULT_LINUX_BOOT_ENV \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"fdtfile=am335x-pepper.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t ${loadaddr} ${filesize}\0" \
|
||||
"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
|
||||
"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
|
||||
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"ubiboot=echo Booting from nand (ubifs) ...; " \
|
||||
"run ubiargs; run ubiload; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run mmcload; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run uimageboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
|
||||
/* Serial console configuration */
|
||||
#define CONFIG_CONS_INDEX 1 /* UART0 */
|
||||
#define CONFIG_SERIAL1 1
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000
|
||||
|
||||
/* Ethernet support */
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ9021
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
|
||||
|
||||
#endif /* __CONFIG_PEPPER_H */
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
#include "siemens-am33x-common.h"
|
||||
|
||||
#define CONFIG_SYS_MPUCLK 720
|
||||
#define DXR2_IOCTRL_VAL 0x18b
|
||||
#define DDR_IOCTRL_VAL 0x18b
|
||||
#define DDR_PLL_FREQ 266
|
||||
|
||||
#define BOARD_DFU_BUTTON_GPIO 59
|
||||
|
|
|
|||
|
|
@ -358,7 +358,7 @@
|
|||
|
||||
#define CONFIG_COMMON_ENV_SETTINGS \
|
||||
"verify=no \0" \
|
||||
"project_dir=systemone\0" \
|
||||
"project_dir=targetdir\0" \
|
||||
"upgrade_available=0\0" \
|
||||
"altbootcmd=run bootcmd\0" \
|
||||
"bootlimit=3\0" \
|
||||
|
|
@ -402,7 +402,11 @@
|
|||
"dfu_args=run bootargs_defaults;" \
|
||||
"setenv bootargs ${bootargs} ;" \
|
||||
"mtdparts default; " \
|
||||
"dfu 0 nand 0; \0" \
|
||||
"led dfu 1;" \
|
||||
"led stat 0;" \
|
||||
"dfu 0 nand 0;" \
|
||||
"led dfu 0;" \
|
||||
"led stat 1;\0" \
|
||||
"dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
|
||||
"net_args=run bootargs_defaults;" \
|
||||
"mtdparts default;" \
|
||||
|
|
|
|||
|
|
@ -24,6 +24,10 @@
|
|||
#define LDO1_CTRL 0x50
|
||||
#define LDO1_VOLTAGE 0x51
|
||||
|
||||
/* LDO2 control/voltage */
|
||||
#define LDO2_CTRL 0x52
|
||||
#define LDO2_VOLTAGE 0x53
|
||||
|
||||
/* LDO9 control/voltage */
|
||||
#define LDO9_CTRL 0x60
|
||||
#define LDO9_VOLTAGE 0x61
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user