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https://github.com/brain-hackers/u-boot-brain
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sunxi: add USB EHCI driver
The Allwinner aka sunxi SoCs have one or more USB host controllers. This adds a driver for their EHCI. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Roman Byshko
Hans de Goede
parent
06cdd94077
commit
8d154002f3
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@ -35,6 +35,7 @@ obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
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obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
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obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
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obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
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obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
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obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
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obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
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obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
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201
drivers/usb/host/ehci-sunxi.c
Normal file
201
drivers/usb/host/ehci-sunxi.c
Normal file
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@ -0,0 +1,201 @@
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/*
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* Copyright (C) 2014 Roman Byshko
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*
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* Roman Byshko <rbyshko@gmail.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <common.h>
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#include "ehci.h"
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#define SUNXI_USB1_IO_BASE 0x01c14000
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#define SUNXI_USB2_IO_BASE 0x01c1c000
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#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
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#define SUNXI_USB_CSR 0x01c13404
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#define SUNXI_USB_PASSBY_EN 1
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#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
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#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
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#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
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#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
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static struct sunxi_ehci_hcd {
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struct usb_hcd *hcd;
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int usb_rst_mask;
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int ahb_clk_mask;
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int gpio_vbus;
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void *csr;
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int irq;
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int id;
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} sunxi_echi_hcd[] = {
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{
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.usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
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.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
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.gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO,
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.csr = (void *)SUNXI_USB_CSR,
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.irq = 39,
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.id = 1,
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},
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#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
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{
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.usb_rst_mask = CCM_USB_CTRL_PHY2_RST,
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.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
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.gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO,
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.csr = (void *)SUNXI_USB_CSR,
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.irq = 40,
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.id = 2,
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}
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#endif
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};
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static int enabled_hcd_count;
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static void *get_io_base(int hcd_id)
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{
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if (hcd_id == 1)
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return (void *)SUNXI_USB1_IO_BASE;
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else if (hcd_id == 2)
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return (void *)SUNXI_USB2_IO_BASE;
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else
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return NULL;
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}
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static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
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int data, int len)
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{
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int j = 0, usbc_bit = 0;
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void *dest = sunxi_ehci->csr;
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usbc_bit = 1 << (sunxi_ehci->id * 2);
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for (j = 0; j < len; j++) {
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/* set the bit address to be written */
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clrbits_le32(dest, 0xff << 8);
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setbits_le32(dest, (addr + j) << 8);
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clrbits_le32(dest, usbc_bit);
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/* set data bit */
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if (data & 0x1)
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setbits_le32(dest, 1 << 7);
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else
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clrbits_le32(dest, 1 << 7);
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setbits_le32(dest, usbc_bit);
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clrbits_le32(dest, usbc_bit);
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data >>= 1;
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}
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}
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static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
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{
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/* The following comments are machine
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* translated from Chinese, you have been warned!
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*/
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/* adjust PHY's magnitude and rate */
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usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
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/* threshold adjustment disconnect */
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#ifdef CONFIG_SUN4I
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usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
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#else
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usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
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#endif
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return;
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}
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static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable)
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{
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unsigned long bits = 0;
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void *addr = get_io_base(sunxi_ehci->id) + SUNXI_USB_PMU_IRQ_ENABLE;
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bits = SUNXI_EHCI_AHB_ICHR8_EN |
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SUNXI_EHCI_AHB_INCR4_BURST_EN |
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SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
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SUNXI_EHCI_ULPI_BYPASS_EN;
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if (enable)
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setbits_le32(addr, bits);
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else
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clrbits_le32(addr, bits);
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return;
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}
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static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
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setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
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sunxi_usb_phy_init(sunxi_ehci);
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sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
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gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
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}
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static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
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sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
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clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
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clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
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}
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int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
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struct ehci_hcor **hcor)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
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/* enable common PHY only once */
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if (index == 0)
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setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
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sunxi_ehci_enable(sunxi_ehci);
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*hccr = get_io_base(sunxi_ehci->id);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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enabled_hcd_count++;
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
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sunxi_ehci_disable(sunxi_ehci);
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/* disable common PHY only once, for the last enabled hcd */
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if (enabled_hcd_count == 1)
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clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
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enabled_hcd_count--;
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return 0;
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}
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