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https://github.com/brain-hackers/u-boot-brain
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net: Rename and cleanup sunxi (Allwinner) emac driver
There have been 3 versions of the sunxi_emac support patch during its development. Somehow version 2 ended up in upstream u-boot where as the u-boot-sunxi git repo got version 3. This bumps the version in upstream u-boot to version 3 of the patch: - Initialize MII clock earlier so mii access to allow independent use - Name change from WEMAC to EMAC to match mainline kernel & chip manual - Cosmetic code cleanup Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Stefan Roese
Ian Campbell
parent
f84269c5c0
commit
b70ed300b0
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@ -20,6 +20,7 @@ obj-$(CONFIG_DNET) += dnet.o
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obj-$(CONFIG_E1000) += e1000.o
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obj-$(CONFIG_E1000_SPI) += e1000_spi.o
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obj-$(CONFIG_EEPRO100) += eepro100.o
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obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
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obj-$(CONFIG_ENC28J60) += enc28j60.o
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obj-$(CONFIG_EP93XX) += ep93xx_eth.o
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obj-$(CONFIG_ETHOC) += ethoc.o
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@ -51,7 +52,6 @@ obj-$(CONFIG_RTL8169) += rtl8169.o
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obj-$(CONFIG_SH_ETHER) += sh_eth.o
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obj-$(CONFIG_SMC91111) += smc91111.o
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obj-$(CONFIG_SMC911X) += smc911x.o
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obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
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obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
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obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
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obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
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@ -1,5 +1,5 @@
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/*
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* sunxi_wemac.c -- Allwinner A10 ethernet driver
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* sunxi_emac.c -- Allwinner A10 ethernet driver
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*
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* (C) Copyright 2012, Stefan Roese <sr@denx.de>
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*
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@ -7,16 +7,16 @@
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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/* EMAC register */
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struct wemac_regs {
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struct emac_regs {
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u32 ctl; /* 0x00 */
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u32 tx_mode; /* 0x04 */
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u32 tx_flow; /* 0x08 */
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@ -27,7 +27,7 @@ struct wemac_regs {
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u32 tx_pl1; /* 0x1c */
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u32 tx_sta; /* 0x20 */
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u32 tx_io_data; /* 0x24 */
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u32 tx_io_data1; /* 0x28 */
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u32 tx_io_data1;/* 0x28 */
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u32 tx_tsvl0; /* 0x2c */
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u32 tx_tsvh0; /* 0x30 */
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u32 tx_tsvl1; /* 0x34 */
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@ -141,33 +141,33 @@ struct sunxi_sramc_regs {
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#define EMAC_MAC_IPGT 0x15
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#define EMAC_MAC_NBTB_IPG1 0xC
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#define EMAC_MAC_NBTB_IPG1 0xc
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#define EMAC_MAC_NBTB_IPG2 0x12
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#define EMAC_MAC_CW 0x37
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#define EMAC_MAC_RM 0xF
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#define EMAC_MAC_RM 0xf
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#define EMAC_MAC_MFL 0x0600
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/* Receive status */
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#define EMAC_CRCERR (1 << 4)
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#define EMAC_LENERR (3 << 5)
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#define EMAC_CRCERR (0x1 << 4)
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#define EMAC_LENERR (0x3 << 5)
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#define DMA_CPU_TRRESHOLD 2000
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struct wemac_eth_dev {
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struct emac_eth_dev {
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u32 speed;
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u32 duplex;
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u32 phy_configured;
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int link_printed;
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};
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struct wemac_rxhdr {
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struct emac_rxhdr {
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s16 rx_len;
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u16 rx_status;
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};
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static void wemac_inblk_32bit(void *reg, void *data, int count)
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static void emac_inblk_32bit(void *reg, void *data, int count)
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{
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int cnt = (count + 3) >> 2;
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@ -181,7 +181,7 @@ static void wemac_inblk_32bit(void *reg, void *data, int count)
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}
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}
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static void wemac_outblk_32bit(void *reg, void *data, int count)
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static void emac_outblk_32bit(void *reg, void *data, int count)
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{
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int cnt = (count + 3) >> 2;
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@ -194,14 +194,12 @@ static void wemac_outblk_32bit(void *reg, void *data, int count)
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}
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}
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/*
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* Read a word from phyxcer
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*/
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static int wemac_phy_read(const char *devname, unsigned char addr,
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/* Read a word from phyxcer */
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static int emac_phy_read(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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/* issue the phy address and reg */
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writel(addr << 8 | reg, ®s->mac_madr);
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@ -221,14 +219,12 @@ static int wemac_phy_read(const char *devname, unsigned char addr,
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return 0;
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}
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/*
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* Write a word to phyxcer
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*/
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static int wemac_phy_write(const char *devname, unsigned char addr,
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/* Write a word to phyxcer */
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static int emac_phy_write(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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/* issue the phy address and reg */
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writel(addr << 8 | reg, ®s->mac_madr);
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@ -250,7 +246,7 @@ static int wemac_phy_write(const char *devname, unsigned char addr,
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static void emac_setup(struct eth_device *dev)
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{
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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u32 reg_val;
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u16 phy_val;
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u32 duplex_flag;
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@ -266,7 +262,7 @@ static void emac_setup(struct eth_device *dev)
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writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
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/* Set MAC CTL1 */
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wemac_phy_read(dev->name, 1, 0, &phy_val);
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emac_phy_read(dev->name, 1, 0, &phy_val);
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debug("PHY SETUP, reg 0 value: %x\n", phy_val);
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duplex_flag = !!(phy_val & (1 << 8));
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@ -288,9 +284,9 @@ static void emac_setup(struct eth_device *dev)
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writel(EMAC_MAC_MFL, ®s->mac_maxf);
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}
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static void wemac_reset(struct eth_device *dev)
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static void emac_reset(struct eth_device *dev)
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{
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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debug("resetting device\n");
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@ -302,10 +298,10 @@ static void wemac_reset(struct eth_device *dev)
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udelay(200);
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}
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static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
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static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
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{
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct wemac_eth_dev *priv = dev->priv;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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struct emac_eth_dev *priv = dev->priv;
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u16 phy_reg;
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/* Init EMAC */
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@ -317,10 +313,7 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
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/* Init MAC */
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/* Soft reset MAC */
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clrbits_le32(®s->mac_ctl0, 1 << 15);
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/* Set MII clock */
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clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
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clrbits_le32(®s->mac_ctl0, 0x1 << 15);
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/* Clear RX counter */
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writel(0x0, ®s->rx_fbc);
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@ -336,14 +329,14 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
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mdelay(1);
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wemac_reset(dev);
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emac_reset(dev);
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/* PHY POWER UP */
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wemac_phy_read(dev->name, 1, 0, &phy_reg);
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wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
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emac_phy_read(dev->name, 1, 0, &phy_reg);
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emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
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mdelay(1);
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wemac_phy_read(dev->name, 1, 0, &phy_reg);
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emac_phy_read(dev->name, 1, 0, &phy_reg);
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priv->speed = miiphy_speed(dev->name, 0);
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priv->duplex = miiphy_duplex(dev->name, 0);
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@ -357,11 +350,11 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
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/* Set EMAC SPEED depend on PHY */
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clrsetbits_le32(®s->mac_supp, 1 << 8,
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((phy_reg & (1 << 13)) >> 13) << 8);
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((phy_reg & (0x1 << 13)) >> 13) << 8);
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/* Set duplex depend on phy */
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clrsetbits_le32(®s->mac_ctl1, 1 << 0,
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((phy_reg & (1 << 8)) >> 8) << 0);
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((phy_reg & (0x1 << 8)) >> 8) << 0);
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/* Enable RX/TX */
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setbits_le32(®s->ctl, 0x7);
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@ -369,15 +362,15 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
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return 0;
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}
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static void sunxi_wemac_eth_halt(struct eth_device *dev)
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static void sunxi_emac_eth_halt(struct eth_device *dev)
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{
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/* Nothing to do here */
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}
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static int sunxi_wemac_eth_recv(struct eth_device *dev)
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static int sunxi_emac_eth_recv(struct eth_device *dev)
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{
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct wemac_rxhdr rxhdr;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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struct emac_rxhdr rxhdr;
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u32 rxcount;
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u32 reg_val;
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int rx_len;
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@ -386,8 +379,7 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
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/* Check packet ready or not */
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/*
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* Race warning: The first packet might arrive with
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/* Race warning: The first packet might arrive with
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* the interrupts disabled, but the second will fix
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*/
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rxcount = readl(®s->rx_fbc);
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@ -401,26 +393,25 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
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reg_val = readl(®s->rx_io_data);
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if (reg_val != 0x0143414d) {
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/* Disable RX */
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clrbits_le32(®s->ctl, 1 << 2);
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clrbits_le32(®s->ctl, 0x1 << 2);
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/* Flush RX FIFO */
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setbits_le32(®s->rx_ctl, 1 << 3);
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while (readl(®s->rx_ctl) & (1 << 3))
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setbits_le32(®s->rx_ctl, 0x1 << 3);
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while (readl(®s->rx_ctl) & (0x1 << 3))
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;
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/* Enable RX */
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setbits_le32(®s->ctl, 1 << 2);
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setbits_le32(®s->ctl, 0x1 << 2);
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return 0;
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}
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/*
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* A packet ready now
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/* A packet ready now
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* Get status/length
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*/
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good_packet = 1;
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wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
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emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
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rx_len = rxhdr.rx_len;
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rx_status = rxhdr.rx_status;
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@ -440,13 +431,13 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
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printf("length error\n");
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}
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/* Move data from WEMAC */
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/* Move data from EMAC */
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if (good_packet) {
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if (rx_len > DMA_CPU_TRRESHOLD) {
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printf("Received packet is too big (len=%d)\n", rx_len);
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} else {
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wemac_inblk_32bit((void *)®s->rx_io_data,
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NetRxPackets[0], rx_len);
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emac_inblk_32bit((void *)®s->rx_io_data,
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NetRxPackets[0], rx_len);
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/* Pass to upper layer */
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NetReceive(NetRxPackets[0], rx_len);
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@ -457,15 +448,15 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
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return 0;
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}
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static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
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static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
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{
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struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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/* Select channel 0 */
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writel(0, ®s->tx_ins);
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/* Write packet */
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wemac_outblk_32bit((void *)®s->tx_io_data, packet, len);
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emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
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/* Set TX len */
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writel(len, ®s->tx_pl0);
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@ -476,50 +467,55 @@ static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
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return 0;
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}
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int sunxi_wemac_initialize(void)
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int sunxi_emac_initialize(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_sramc_regs *sram =
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(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
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struct emac_regs *regs =
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(struct emac_regs *)SUNXI_EMAC_BASE;
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struct eth_device *dev;
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struct wemac_eth_dev *priv;
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struct emac_eth_dev *priv;
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int pin;
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dev = malloc(sizeof(*dev));
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if (dev == NULL)
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return -ENOMEM;
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priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
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priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
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if (!priv) {
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free(dev);
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return -ENOMEM;
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}
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memset(dev, 0, sizeof(*dev));
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memset(priv, 0, sizeof(struct wemac_eth_dev));
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memset(priv, 0, sizeof(struct emac_eth_dev));
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/* Map SRAM to EMAC */
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setbits_le32(&sram->ctrl1, 0x5 << 2);
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/* Configure pin mux settings for MII Ethernet */
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for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
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sunxi_gpio_set_cfgpin(pin, 2);
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
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/* Set up clock gating */
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setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
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dev->iobase = SUNXI_EMAC_BASE;
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/* Set MII clock */
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clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
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dev->iobase = (int)regs;
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dev->priv = priv;
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dev->init = sunxi_wemac_eth_init;
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dev->halt = sunxi_wemac_eth_halt;
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dev->send = sunxi_wemac_eth_send;
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dev->recv = sunxi_wemac_eth_recv;
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strcpy(dev->name, "wemac");
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dev->init = sunxi_emac_eth_init;
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dev->halt = sunxi_emac_eth_halt;
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dev->send = sunxi_emac_eth_send;
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dev->recv = sunxi_emac_eth_recv;
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strcpy(dev->name, "emac");
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eth_register(dev);
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miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
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miiphy_register(dev->name, emac_phy_read, emac_phy_write);
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return 0;
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}
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@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis);
|
|||
int skge_initialize(bd_t *bis);
|
||||
int smc91111_initialize(u8 dev_num, int base_addr);
|
||||
int smc911x_initialize(u8 dev_num, int base_addr);
|
||||
int sunxi_emac_initialize(bd_t *bis);
|
||||
int sunxi_gmac_initialize(bd_t *bis);
|
||||
int sunxi_wemac_initialize(bd_t *bis);
|
||||
int tsi108_eth_initialize(bd_t *bis);
|
||||
int uec_standard_init(bd_t *bis);
|
||||
int uli526x_initialize(bd_t *bis);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user