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Merge remote-tracking branch 'u-boot/master'

Browse Source 
Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
This commit is contained in:
Albert ARIBAUD 2014-05-20 10:05:42 +02:00
commit 05d134b084
226 changed files with 3953 additions and 1896 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
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@ -47,8 +47,8 @@
/errlog
/reloc_off
!/spl/Makefile
/spl/*
!/spl/Makefile
/tpl/
#

13
Makefile
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@ -6,9 +6,9 @@
#
VERSION = 2014
PATCHLEVEL = 04
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@ -285,7 +285,7 @@ export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
#
# If $(quiet) is empty, the whole command will be printed.
# If it is set to "quiet_", only the short version will be printed.
# If it is set to "quiet_", only the short version will be printed.
# If it is set to "silent_", nothing will be printed at all, since
# the variable $(silent_cmd_cc_o_c) doesn't exist.
#
@ -578,6 +578,9 @@ KBUILD_AFLAGS += -Wa,-gstabs,-S
endif
endif
# Prohibit date/time macros, which would make the build non-deterministic
KBUILD_CFLAGS += $(call cc-option,-Werror=date-time)
ifneq ($(CONFIG_SYS_TEXT_BASE),)
KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
@ -995,7 +998,7 @@ ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,u-boot__) common/system_map.o
endif
# The actual objects are generated when descending,
# The actual objects are generated when descending,
# make sure no implicit rule kicks in
$(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
@ -1434,7 +1437,7 @@ endif
$(build)=$(build-dir) $(@:.ko=.o)
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
# FIXME Should go into a make.lib or something
# FIXME Should go into a make.lib or something
# ===========================================================================
quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN $(wildcard $(rm-dirs)))

21
README
View File

@ -264,6 +264,17 @@ e.g. "make cogent_mpc8xx_config". And also configure the cogent
directory according to the instructions in cogent/README.
Sandbox Environment:
--------------------
U-Boot can be built natively to run on a Linux host using the 'sandbox'
board. This allows feature development which is not board- or architecture-
specific to be undertaken on a native platform. The sandbox is also used to
run some of U-Boot's tests.
See board/sandbox/sandbox/README.sandbox for more details.
Configuration Options:
----------------------
@ -440,6 +451,12 @@ The following options need to be configured:
supported, core will start to execute uboot when wakes up.
- Generic CPU options:
CONFIG_SYS_GENERIC_GLOBAL_DATA
Defines global data is initialized in generic board board_init_f().
If this macro is defined, global data is created and cleared in
generic board board_init_f(). Without this macro, architecture/board
should initialize global data before calling board_init_f().
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
Defines the endianess of the CPU. Implementation of those
@ -740,6 +757,10 @@ The following options need to be configured:
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
CONFIG_SERIAL_HW_FLOW_CONTROL
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
- Console Interface:
Depending on board, define exactly one serial port

2
arch/arc/include/asm/config.h
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@ -7,6 +7,8 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_LMB
#endif /*__ASM_ARC_CONFIG_H_ */

2
arch/arm/include/asm/config.h
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@ -7,6 +7,8 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH

1
arch/arm/include/asm/u-boot.h
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@ -27,7 +27,6 @@
#ifndef __ASSEMBLY__
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */

1
arch/arm/lib/board.c
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@ -445,7 +445,6 @@ void board_init_f(ulong bootflag)
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
gd->bd->bi_baudrate = gd->baudrate;
/* Ram ist board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */

1
arch/avr32/include/asm/u-boot.h
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@ -7,7 +7,6 @@
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;

1
arch/avr32/lib/board.c
View File

@ -220,7 +220,6 @@ void board_init_f(ulong board_type)
*/
bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
bd->bi_dram[0].size = sdram_size;
bd->bi_baudrate = gd->baudrate;
memcpy(new_gd, gd, sizeof(gd_t));

28
arch/blackfin/include/asm/net.h
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@ -1,28 +0,0 @@
/*
* net.h - misc Blackfin network helpers
*
* Copyright (c) 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __ASM_BFIN_RAND_MAC__
#define __ASM_BFIN_RAND_MAC__
/* If the board does not have a real MAC assigned to it, then generate a
* locally administrated pseudo-random one based on CYCLES and compile date.
*/
static inline void bfin_gen_rand_mac(uchar *mac_addr)
{
/* make something up */
const char s[] = __DATE__;
size_t i;
u32 cycles;
for (i = 0; i < 6; ++i) {
asm("%0 = CYCLES;" : "=r" (cycles));
mac_addr[i] = cycles ^ s[i];
}
mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
}
#endif

1
arch/blackfin/include/asm/u-boot.h
View File

@ -13,7 +13,6 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */

2
arch/blackfin/lib/board.c
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@ -69,7 +69,6 @@ static int display_banner(void)
static int init_baudrate(void)
{
gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
gd->bd->bi_baudrate = gd->baudrate;
return 0;
}
@ -92,7 +91,6 @@ static void display_global_data(void)
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" \\-bd: %p\n", gd->bd);
printf(" |-bi_baudrate: %x\n", bd->bi_baudrate);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);
printf(" |-bi_memsize: %lx\n", bd->bi_memsize);

1
arch/m68k/include/asm/u-boot.h
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@ -44,7 +44,6 @@ typedef struct bd_info {
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */

1
arch/m68k/lib/board.c
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@ -342,7 +342,6 @@ board_init_f (ulong bootflag)
bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
#endif
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));

1
arch/microblaze/include/asm/u-boot.h
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@ -24,7 +24,6 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned int bi_baudrate; /* Console Baudrate */
ulong bi_boot_params; /* where this board expects params */
} bd_t;

1
arch/microblaze/lib/board.c
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@ -78,7 +78,6 @@ void board_init_f(ulong not_used)
memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
gd->bd = bd;
gd->baudrate = CONFIG_BAUDRATE;
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */

2
arch/mips/include/asm/config.h
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@ -7,6 +7,8 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH

1
arch/mips/include/asm/u-boot.h
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@ -23,7 +23,6 @@
#else /* !CONFIG_SYS_GENERIC_BOARD */
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */

1
arch/mips/lib/board.c
View File

@ -204,7 +204,6 @@ void board_init_f(ulong bootflag)
*/
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */
bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
memcpy(id, (void *)gd, sizeof(gd_t));

1
arch/nds32/include/asm/u-boot.h
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@ -23,7 +23,6 @@
#include <environment.h>
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */

1
arch/nds32/lib/board.c
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@ -255,7 +255,6 @@ void board_init_f(ulong bootflag)
addr_sp &= ~0x07;
debug("New Stack Pointer is: %08lx\n", addr_sp);
gd->bd->bi_baudrate = gd->baudrate;
/* Ram isn't board specific, so move it to board code ... */
dram_init_banksize();
display_dram_config(); /* and display it */

1
arch/nios2/include/asm/u-boot.h
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@ -23,7 +23,6 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */

1
arch/nios2/lib/board.c
View File

@ -92,7 +92,6 @@ void board_init(void)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();

1
arch/openrisc/include/asm/u-boot.h
View File

@ -16,7 +16,6 @@
#define _U_BOOT_H_
typedef struct bd_info {
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */

1
arch/openrisc/lib/board.c
View File

@ -84,7 +84,6 @@ void board_init(void)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
WATCHDOG_RESET();

2
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o

3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -299,6 +299,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
puts("Work-around for Erratum A-005434 enabled\n");
#endif
return 0;
}

24
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -77,6 +77,30 @@ int checkcpu (void)
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (SVR_SOC_VER(svr) == SVR_T4080) {
ccsr_rcpm_t *rcpm =
(void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
FSL_CORENET_DEVDISR2_DTSEC1_9);
setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
/* It needs SW to disable core4~7 as HW design sake on T4080 */
for (i = 4; i < 8; i++)
cpu_disable(i);
/* request core4~7 into PH20 state, prior to entering PCL10
* state, all cores in cluster should be placed in PH20 state.
*/
setbits_be32(&rcpm->pcph20setr, 0xf0);
/* put the 2nd cluster into PCL10 state */
setbits_be32(&rcpm->clpcl10setr, 1 << 1);
}
#endif
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"

17
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -368,12 +368,12 @@ void fsl_erratum_a007212_workaround(void)
}
#endif
void cpu_init_f (void)
ulong cpu_init_f(void)
{
ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
@ -442,13 +442,14 @@ void cpu_init_f (void)
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
return flag;
}
/* Implement a dummy function for those platforms w/o SERDES */
@ -462,10 +463,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
int enable_cluster_l2(void)
{
int i = 0;
u32 cluster;
u32 cluster, svr = get_svr();
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
/* only the L2 of first cluster should be enabled as expected on T4080,
* but there is no EOC in the first cluster as HW sake, so return here
* to skip enabling L2 cache of the 2nd cluster.
*/
if (SVR_SOC_VER(svr) == SVR_T4080)
return 0;
cluster = in_be32(&gur->tp_cluster[i].lower);
if (cluster & TP_CLUSTER_EOC)
return 0;
@ -888,6 +896,7 @@ skip_l2:
}
#endif
init_used_tlb_cams();
return 0;
}

2
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
View File

@ -102,11 +102,13 @@ void cpu_init_early_f(void *fdt)
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
#ifdef CONFIG_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
#endif
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);

2
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -674,7 +674,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_CPM2
do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
"current-speed", bd->bi_baudrate, 1);
"current-speed", gd->baudrate, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
"clock-frequency", bd->bi_brgfreq, 1);

3
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info)
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
*/
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) >= 2)
mem_pll_rat *= 2;
#endif

4
arch/powerpc/cpu/mpc85xx/spl_minimal.c
View File

@ -12,7 +12,7 @@
DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
@ -27,6 +27,8 @@ void cpu_init_f(void)
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV

4
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -314,7 +314,7 @@ l2_disabled:
#endif
mtspr HID0,r0
#ifndef CONFIG_E500MC
#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
@ -1158,7 +1158,7 @@ _start_cont:
mtmsr r3
isync
bl cpu_init_f
bl cpu_init_f /* return boot_flag for calling board_init_f */
bl board_init_f
isync

2
arch/powerpc/cpu/mpc85xx/t4240_ids.c
View File

@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
};
#endif
#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_BASE(1, 307),
SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN

2
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
View File

@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
#elif defined(CONFIG_PPC_T4160)
#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,

2
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
#include "config.h"
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000

2
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
View File

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
#include "config.h"
OUTPUT_ARCH(powerpc)
SECTIONS

2
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
View File

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
#include "config.h"
OUTPUT_ARCH(powerpc)
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC

2
arch/powerpc/cpu/mpc85xx/u-boot.lds
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
#include "config.h"
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS

1
arch/powerpc/cpu/mpc86xx/start.S
View File

@ -273,6 +273,7 @@ diag_done:
/* bl l2cache_enable */
/* run 1st part of board init code (from Flash) */
li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
sync

6
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -62,10 +62,12 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
CPU_TYPE_ENTRY(T4160, T4160, 0),
CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
CPU_TYPE_ENTRY(B4220, B4220, 0),
@ -176,7 +178,7 @@ struct cpu_type *identify_cpu(u32 ver)
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
u32 cpu_mask(void)
__weak u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
@ -195,7 +197,7 @@ u32 cpu_mask(void)
/*
* Return the number of cores on this SOC.
*/
int cpu_numcores(void)
__weak int cpu_numcores(void)
{
struct cpu_type *cpu = gd->arch.cpu;

22
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -247,7 +247,9 @@
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2
@ -591,11 +593,13 @@
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_A005434
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@ -611,13 +615,18 @@
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 7
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#if defined(CONFIG_PPC_T4160)
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#elif defined(CONFIG_PPC_T4080)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_NUM_LAWS 32
@ -798,6 +807,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE

5
arch/powerpc/include/asm/fsl_errata.h
View File

@ -16,6 +16,7 @@ static inline bool has_erratum_a006379(void)
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
@ -49,9 +50,13 @@ static inline bool has_erratum_a006261(void)
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T4240:
case SVR_T4160:
case SVR_T4080:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
case SVR_T1040:
return IS_SVR_REV(svr, 1, 0);
case SVR_T2080:
case SVR_T2081:
return IS_SVR_REV(svr, 1, 0);
case SVR_P5040:
return IS_SVR_REV(svr, 1, 0);
}

3
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -20,8 +20,9 @@
#if defined(CONFIG_B4860QDS) || \
defined(CONFIG_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
defined(CONFIG_T1040RDB)
defined(CONFIG_T104xRDB)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000

6
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1748,7 +1748,8 @@ typedef struct ccsr_gur {
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000

2
arch/powerpc/include/asm/processor.h
View File

@ -1111,11 +1111,13 @@
#define SVR_T4240 0x824000
#define SVR_T4120 0x824001
#define SVR_T4160 0x824100
#define SVR_T4080 0x824102
#define SVR_C291 0x850000
#define SVR_C292 0x850020
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101

1
arch/powerpc/include/asm/u-boot.h
View File

@ -64,7 +64,6 @@ typedef struct bd_info {
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \

1
arch/powerpc/lib/board.c
View File

@ -547,7 +547,6 @@ void board_init_f(ulong bootflag)
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));

6
arch/sandbox/config.mk
View File

@ -18,3 +18,9 @@ cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
CONFIG_ARCH_DEVICE_TREE := sandbox
# Define this to avoid linking with SDL, which requires SDL libraries
# This can solve 'sdl-config: Command not found' errors
ifneq ($(NO_SDL),)
PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL
endif

1
arch/sandbox/dts/.gitignore vendored Normal file
View File

@ -0,0 +1 @@
*.dtb

1
arch/sandbox/include/asm/config.h
View File

@ -7,6 +7,7 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SANDBOX_ARCH
/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */

1
arch/sh/include/asm/u-boot.h
View File

@ -20,7 +20,6 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned int bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;

1
arch/sh/lib/board.c
View File

@ -155,7 +155,6 @@ void sh_generic_init(void)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET();

22
arch/sparc/cpu/leon2/cpu_init.c
View File

@ -13,6 +13,9 @@
#include <config.h>
#define TIMER_BASE_CLK 1000000
#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
/* reset CPU (jump to 0, without reset) */
@ -90,7 +93,7 @@ void cpu_wait_ticks(unsigned long ticks)
while (get_timer(start) < ticks) ;
}
/* initiate and setup timer0 interrupt to 1MHz
/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
* Return irq number for timer int or a negative number for
* dealing with self
*/
@ -98,28 +101,31 @@ int timer_interrupt_init_cpu(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
/* 1ms ticks */
/* SYS_HZ ticks per second */
leon2->Timer_Counter_1 = 0;
leon2->Timer_Reload_1 = 999; /* (((1000000 / 100) - 1)) */
leon2->Timer_Reload_1 = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
leon2->Timer_Control_1 =
(LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD);
return LEON2_TIMER1_IRQNO;
}
ulong get_tbclk(void)
{
return TIMER_BASE_CLK;
}
/*
* This function is intended for SHORT delays only.
*/
unsigned long cpu_usec2ticks(unsigned long usec)
{
/* timer set to 1kHz ==> 1 clk tick = 1 msec */
if (usec < 1000)
if (usec < US_PER_TICK)
return 1;
return (usec / 1000);
return usec / US_PER_TICK;
}
unsigned long cpu_ticks2usec(unsigned long ticks)
{
/* 1tick = 1usec */
return ticks * 1000;
return ticks * US_PER_TICK;
}

22
arch/sparc/cpu/leon3/cpu_init.c
View File

@ -14,6 +14,9 @@
#include <config.h>
#define TIMER_BASE_CLK 1000000
#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
/* reset CPU (jump to 0, without reset) */
@ -203,15 +206,15 @@ void cpu_wait_ticks(unsigned long ticks)
while (get_timer(start) < ticks) ;
}
/* initiate and setup timer0 interrupt to 1MHz
/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
* Return irq number for timer int or a negative number for
* dealing with self
*/
int timer_interrupt_init_cpu(void)
{
/* 1ms ticks */
/* SYS_HZ ticks per second */
gptimer->e[0].val = 0;
gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */
gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
gptimer->e[0].ctrl =
(LEON3_GPTIMER_EN |
LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
@ -219,19 +222,22 @@ int timer_interrupt_init_cpu(void)
return gptimer_irq;
}
ulong get_tbclk(void)
{
return TIMER_BASE_CLK;
}
/*
* This function is intended for SHORT delays only.
*/
unsigned long cpu_usec2ticks(unsigned long usec)
{
/* timer set to 1kHz ==> 1 clk tick = 1 msec */
if (usec < 1000)
if (usec < US_PER_TICK)
return 1;
return (usec / 1000);
return usec / US_PER_TICK;
}
unsigned long cpu_ticks2usec(unsigned long ticks)
{
/* 1tick = 1usec */
return ticks * 1000;
return ticks * US_PER_TICK;
}

1
arch/sparc/include/asm/u-boot.h
View File

@ -40,7 +40,6 @@ typedef struct bd_info {
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */

1
arch/sparc/lib/board.c
View File

@ -173,7 +173,6 @@ void board_init_f(ulong bootflag)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */

2
board/amcc/acadia/acadia.c
View File

@ -39,12 +39,10 @@ int board_early_init_f(void)
{
unsigned int reg;
#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
acadia_gpio_init();

87
board/amcc/acadia/u-boot-nand.lds
View File

@ -1,87 +0,0 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

88
board/amcc/bamboo/u-boot-nand.lds
View File

@ -1,88 +0,0 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text*)
board/amcc/bamboo/init.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

88
board/amcc/canyonlands/u-boot-nand.lds
View File

@ -1,88 +0,0 @@
/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
board/amcc/canyonlands/init.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x20000);
common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x80000);
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

87
board/amcc/kilauea/u-boot-nand.lds
View File

@ -1,87 +0,0 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

88
board/amcc/sequoia/u-boot-nand.lds
View File

@ -1,88 +0,0 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
board/amcc/sequoia/init.o (.text*)
/* Align to next NAND block */
. = ALIGN(0x4000);
common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
KEEP(*(.got))
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

7
board/armadeus/apf27/fpga.c
View File

@ -26,7 +26,7 @@
* Spartan2 code is used to download our Spartan 3 :) code is compatible.
* Just take care about the file size
*/
Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
xilinx_spartan3_slave_parallel_fns fpga_fns = {
fpga_pre_fn,
fpga_pgm_fn,
fpga_init_fn,
@ -42,12 +42,13 @@ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
fpga_post_fn,
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{Xilinx_Spartan3,
xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_parallel,
1196128l/8,
(void *)&fpga_fns,
0,
&spartan3_op,
"3s200aft256"}
};

47
board/astro/mcf5373l/fpga.c
View File

@ -203,7 +203,7 @@ int astro5373l_altera_load(void)
}
/* Set the FPGA's PROG_B line to the specified level */
int xilinx_pgm_fn(int assert, int flush, int cookie)
int xilinx_pgm_config_fn(int assert, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@ -218,7 +218,7 @@ int xilinx_pgm_fn(int assert, int flush, int cookie)
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
int xilinx_init_fn(int cookie)
int xilinx_init_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@ -226,7 +226,7 @@ int xilinx_init_fn(int cookie)
}
/* Test the state of the active-high FPGA DONE pin */
int xilinx_done_fn(int cookie)
int xilinx_done_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@ -234,7 +234,7 @@ int xilinx_done_fn(int cookie)
}
/* Abort an FPGA operation */
int xilinx_abort_fn(int cookie)
int xilinx_abort_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
/* ensure all SPI peripherals and FPGAs are deselected */
@ -300,7 +300,7 @@ int xilinx_post_config_fn(int cookie)
return rc;
}
int xilinx_clk_fn(int assert_clk, int flush, int cookie)
int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@ -311,7 +311,7 @@ int xilinx_clk_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
int xilinx_wr_fn(int assert_write, int flush, int cookie)
int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@ -322,7 +322,7 @@ int xilinx_wr_fn(int assert_write, int flush, int cookie)
return assert_write;
}
int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
{
size_t bytecount = 0;
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@ -363,23 +363,24 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
xilinx_pgm_fn,
xilinx_clk_fn,
xilinx_init_fn,
xilinx_done_fn,
xilinx_wr_fn,
xilinx_pgm_config_fn,
xilinx_clk_config_fn,
xilinx_init_config_fn,
xilinx_done_config_fn,
xilinx_wr_config_fn,
0,
xilinx_fastwr_fn
xilinx_fastwr_config_fn
};
Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
{Xilinx_Spartan3,
xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
{xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)&xilinx_fns,
0}
0,
&spartan3_op}
};
/* Initialize the fpga. Return 1 on success, 0 on failure. */
@ -395,12 +396,12 @@ int astro5373l_xilinx_load(void)
* so set stuff here instead of static initialisation:
*/
xilinx_fns.pre = xilinx_pre_config_fn;
xilinx_fns.pgm = xilinx_pgm_fn;
xilinx_fns.clk = xilinx_clk_fn;
xilinx_fns.init = xilinx_init_fn;
xilinx_fns.done = xilinx_done_fn;
xilinx_fns.wr = xilinx_wr_fn;
xilinx_fns.bwr = xilinx_fastwr_fn;
xilinx_fns.pgm = xilinx_pgm_config_fn;
xilinx_fns.clk = xilinx_clk_config_fn;
xilinx_fns.init = xilinx_init_config_fn;
xilinx_fns.done = xilinx_done_config_fn;
xilinx_fns.wr = xilinx_wr_config_fn;
xilinx_fns.bwr = xilinx_fastwr_config_fn;
xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
fpga_add(fpga_xilinx, &xilinx_fpga[i]);
}

4
board/balloon3/balloon3.c
View File

@ -191,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie)
return assert_clk;
}
Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@ -207,7 +207,7 @@ Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
fpga_post_config_fn,
};
Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)&balloon3_fpga_fns, 0);
/* Initialize the FPGA */

3
board/bct-brettl2/bct-brettl2.c
View File

@ -12,7 +12,6 @@
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/gpio.h>
#include <asm/net.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
@ -33,7 +32,7 @@ int checkboard(void)
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}

3
board/bf518f-ezbrd/bf518f-ezbrd.c
View File

@ -13,7 +13,6 @@
#include <netdev.h>
#include <spi.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/otp.h>
#include <asm/sdh.h>
@ -48,7 +47,7 @@ static void board_init_enetaddr(uchar *mac_addr)
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);

3
board/bf526-ezbrd/bf526-ezbrd.c
View File

@ -12,7 +12,6 @@
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
DECLARE_GLOBAL_DATA_PTR;
@ -45,7 +44,7 @@ static void board_init_enetaddr(uchar *mac_addr)
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);

3
board/bf527-ezkit/bf527-ezkit.c
View File

@ -13,7 +13,6 @@
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
DECLARE_GLOBAL_DATA_PTR;
@ -47,7 +46,7 @@ static void board_init_enetaddr(uchar *mac_addr)
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);

3
board/bf537-minotaur/bf537-minotaur.c
View File

@ -12,7 +12,6 @@
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -27,7 +26,7 @@ int checkboard(void)
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}

3
board/bf537-pnav/bf537-pnav.c
View File

@ -12,7 +12,6 @@
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -27,7 +26,7 @@ int checkboard(void)
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}

3
board/bf537-srv1/bf537-srv1.c
View File

@ -12,7 +12,6 @@
#include <netdev.h>
#include <net.h>
#include <asm/blackfin.h>
#include <asm/net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -27,7 +26,7 @@ int checkboard(void)
static void board_init_enetaddr(uchar *mac_addr)
{
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
eth_setenv_enetaddr("ethaddr", mac_addr);
}

3
board/bf537-stamp/bf537-stamp.c
View File

@ -13,7 +13,6 @@
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include <net.h>
#include <asm/mach-common/bits/bootrom.h>
#include <netdev.h>
@ -48,7 +47,7 @@ static void board_init_enetaddr(uchar *mac_addr)
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);

2
board/buffalo/lsxl/lsxl.c
View File

@ -231,7 +231,7 @@ static void rescue_mode(void)
printf("Entering rescue mode..\n");
#ifdef CONFIG_RANDOM_MACADDR
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
eth_random_enetaddr(enetaddr);
eth_random_addr(enetaddr);
if (eth_setenv_enetaddr("ethaddr", enetaddr)) {
printf("Failed to set ethernet address\n");
set_led(LED_ALARM_BLINKING);

3
board/cm-bf527/cm-bf527.c
View File

@ -11,7 +11,6 @@
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include <asm/mach-common/bits/otp.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
@ -46,7 +45,7 @@ static void board_init_enetaddr(uchar *mac_addr)
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);

3
board/cm-bf537e/cm-bf537e.c
View File

@ -12,7 +12,6 @@
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include "gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var)
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
bfin_gen_rand_mac(enetaddr);
eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}

3
board/cm-bf537u/cm-bf537u.c
View File

@ -12,7 +12,6 @@
#include <net.h>
#include <netdev.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include "../cm-bf537e/gpio_cfi_flash.h"
DECLARE_GLOBAL_DATA_PTR;
@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var)
return;
printf("Warning: %s: generating 'random' MAC address\n", var);
bfin_gen_rand_mac(enetaddr);
eth_random_addr(enetaddr);
eth_setenv_enetaddr(var, enetaddr);
}

2
board/dave/PPChameleonEVB/u-boot.lds
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
#include "config.h"
#ifndef RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS 0xfffffffc

3
board/dnp5370/dnp5370.c
View File

@ -14,7 +14,6 @@
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/net.h>
#include <net.h>
#include <netdev.h>
#include <asm/gpio.h>
@ -55,7 +54,7 @@ static void board_init_enetaddr(uchar *mac_addr)
if (!valid_mac) {
puts("Warning: Generating 'random' MAC address\n");
bfin_gen_rand_mac(mac_addr);
eth_random_addr(mac_addr);
}
eth_setenv_enetaddr("ethaddr", mac_addr);

8
board/esd/pmc440/fpga.c
View File

@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USE_SP_CODE
#ifdef USE_SP_CODE
Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
fpga_post_config_fn,
};
#else
Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
};
#endif
Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
ngcc_fpga_pre_config_fn,
ngcc_fpga_pgm_fn,
ngcc_fpga_clk_fn,
@ -57,7 +57,7 @@ Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
ngcc_fpga_post_config_fn
};
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
XILINX_XC3S1200E_DESC(
#ifdef USE_SP_CODE
slave_parallel,

118
board/esd/pmc440/u-boot-nand.lds
View File

@ -1,118 +0,0 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
__bss_end = . ;
PROVIDE (end = .);
}

240
board/freescale/b4860qds/b4860qds.c
View File

@ -23,6 +23,7 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/idt8t49n222a_serdes_clk.h"
#include "../common/zm7300.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
@ -94,6 +95,238 @@ int select_i2c_ch_pca(u8 ch)
return 0;
}
/*
* read_voltage from sensor on I2C bus
* We use average of 4 readings, waiting for 532us befor another reading
*/
#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
static inline int read_voltage(void)
{
int i, ret, voltage_read = 0;
u16 vol_mon;
for (i = 0; i < NUM_READINGS; i++) {
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
}
if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
printf("VID: Core voltage sensor error\n");
return -1;
}
debug("VID: bus voltage reads 0x%04x\n", vol_mon);
/* LSB = 4mv */
voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
udelay(WAIT_FOR_ADC);
}
/* calculate the average */
voltage_read /= NUM_READINGS;
return voltage_read;
}
static int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 fusesr;
u8 vid;
int vdd_target, vdd_last;
int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
int ret;
unsigned int orig_i2c_speed;
unsigned long vdd_string_override;
char *vdd_string;
static const uint16_t vdd[32] = {
0, /* unused */
9875, /* 0.9875V */
9750,
9625,
9500,
9375,
9250,
9125,
9000,
8875,
8750,
8625,
8500,
8375,
8250,
8125,
10000, /* 1.0000V */
10125,
10250,
10375,
10500,
10625,
10750,
10875,
11000,
0, /* reserved */
};
struct vdd_drive {
u8 vid;
unsigned voltage;
};
ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
printf("VID: I2c failed to switch channel\n");
ret = -1;
goto exit;
}
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_VID_MASK;
if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
}
vdd_target = vdd[vid];
debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
vid, vdd_target/10);
/* check override variable for overriding VDD */
vdd_string = getenv("b4qds_vdd_mv");
if (vdd_override == 0 && vdd_string &&
!strict_strtoul(vdd_string, 10, &vdd_string_override))
vdd_override = vdd_string_override;
if (vdd_override >= 819 && vdd_override <= 1212) {
vdd_target = vdd_override * 10; /* convert to 1/10 mV */
debug("VDD override is %lu\n", vdd_override);
} else if (vdd_override != 0) {
printf("Invalid value.\n");
}
if (vdd_target == 0) {
printf("VID: VID not used\n");
ret = 0;
goto exit;
}
/*
* Read voltage monitor to check real voltage.
* Voltage monitor LSB is 4mv.
*/
vdd_last = read_voltage();
if (vdd_last < 0) {
printf("VID: abort VID adjustment\n");
ret = -1;
goto exit;
}
debug("VID: Core voltage is at %d mV\n", vdd_last);
ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
if (ret) {
printf("VID: I2c failed to switch channel to DPM\n");
ret = -1;
goto exit;
}
/* Round up to the value of step of Voltage regulator */
voltage = roundup(vdd_target, ZM_STEP);
debug("VID: rounded up voltage = %d\n", voltage);
/* lower the speed to 100kHz to access ZM7300 device */
debug("VID: Setting bus speed to 100KHz if not already set\n");
orig_i2c_speed = i2c_get_bus_speed();
if (orig_i2c_speed != 100000)
i2c_set_bus_speed(100000);
/* Read the existing level on board, if equal to requsted one,
no need to re-set */
existing_voltage = zm_read_voltage();
/* allowing the voltage difference of one step 0.0125V acceptable */
if ((existing_voltage >= voltage) &&
(existing_voltage < (voltage + ZM_STEP))) {
debug("VID: voltage already set as requested,returning\n");
ret = existing_voltage;
goto out;
}
debug("VID: Changing voltage for board from %dmV to %dmV\n",
existing_voltage/10, voltage/10);
if (zm_disable_wp() < 0) {
ret = -1;
goto out;
}
/* Change Voltage: the change is done through all the steps in the
way, to avoid reset to the board due to power good signal fail
in big voltage change gap jump.
*/
if (existing_voltage > voltage) {
temp_voltage = existing_voltage - ZM_STEP;
while (temp_voltage >= voltage) {
ret = zm_write_voltage(temp_voltage);
if (ret == temp_voltage) {
temp_voltage -= ZM_STEP;
} else {
/* ZM7300 device failed to set
* the voltage */
printf
("VID:Stepping down vol failed:%dmV\n",
temp_voltage/10);
ret = -1;
goto out;
}
}
} else {
temp_voltage = existing_voltage + ZM_STEP;
while (temp_voltage < (voltage + ZM_STEP)) {
ret = zm_write_voltage(temp_voltage);
if (ret == temp_voltage) {
temp_voltage += ZM_STEP;
} else {
/* ZM7300 device failed to set
* the voltage */
printf
("VID:Stepping up vol failed:%dmV\n",
temp_voltage/10);
ret = -1;
goto out;
}
}
}
if (zm_enable_wp() < 0)
ret = -1;
/* restore the speed to 400kHz */
out: debug("VID: Restore the I2C bus speed to %dKHz\n",
orig_i2c_speed/1000);
i2c_set_bus_speed(orig_i2c_speed);
if (ret < 0)
goto exit;
ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
printf("VID: I2c failed to switch channel\n");
ret = -1;
goto exit;
}
vdd_last = read_voltage();
select_i2c_ch_pca(I2C_CH_DEFAULT);
if (vdd_last > 0)
printf("VID: Core voltage %d mV\n", vdd_last);
else
ret = -1;
exit:
if (re_enable)
enable_interrupts();
return ret;
}
int configure_vsc3316_3308(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -697,6 +930,13 @@ int board_early_init_r(void)
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if (adjust_vdd(0) < 0)
printf("Warning: Adjusting core voltage failed\n");
/* SerDes1 refclks need to be set again, as default clks
* are not suitable for CPRI and onboard SGMIIs to work
* simultaneously.

1
board/freescale/common/Makefile
View File

@ -48,6 +48,7 @@ obj-$(CONFIG_P5020DS) += ics307_clk.o
obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/

13
board/freescale/common/sys_eeprom.c
View File

@ -21,7 +21,7 @@
/* some boards with non-256-bytes EEPROM have special define */
/* for MAX_NUM_PORTS in board-specific file */
#ifndef MAX_NUM_PORTS
#define MAX_NUM_PORTS 23
#define MAX_NUM_PORTS 16
#endif
#define NXID_VERSION 1
#endif
@ -58,8 +58,9 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
u32 crc; /* x+1 CRC32 checksum */
u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
u32 crc; /* 0xfc - 0xff CRC32 checksum */
#endif
} e;
@ -425,13 +426,13 @@ int mac_read_from_eeprom(void)
if (read_eeprom()) {
printf("Read failed.\n");
return -1;
return 0;
}
if (!is_valid) {
printf("Invalid ID (%02x %02x %02x %02x)\n",
e.id[0], e.id[1], e.id[2], e.id[3]);
return -1;
return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
@ -447,7 +448,7 @@ int mac_read_from_eeprom(void)
crcp = (void *)&e + crc_offset;
if (crc != be32_to_cpu(*crcp)) {
printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
return -1;
return 0;
}
#ifdef CONFIG_SYS_I2C_EEPROM_NXID

235
board/freescale/common/zm7300.c Normal file
View File

@ -0,0 +1,235 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Power-One ZM7300 DPM */
#include "zm7300.h"
#define DPM_WP 0x96
#define WRP_OPCODE 0x01
#define WRM_OPCODE 0x02
#define RRP_OPCODE 0x11
#define DPM_SUCCESS 0x01
#define DPM_EXEC_FAIL 0x00
static const uint16_t hex_to_1_10mv[] = {
5000,
5125,
5250,
5375,
5500,
5625,
5750,
5875,
6000,
6125,
6250,
6375,
6500,
6625,
6750,
6875,
7000,
7125,
7250,
7375,
7500,
7625,
7750,
7875,
8000,
8125,
8250,
8375,
8500,
8625,
8750,
8875,
9000,
9125,
9250,
9375,
9500, /* 0.95mV */
9625,
9750,
9875,
10000, /* 1.0V */
10125,
10250,
10375,
10500,
10625,
10750,
10875,
11000,
11125,
11250,
11375,
11500,
11625,
11750,
11875,
12000,
12125,
12250,
12375,
0, /* reserved */
};
/* Read Data d from Register r of POL p */
u8 dpm_rrp(uchar r)
{
u8 ret[5];
ret[0] = RRP_OPCODE;
/* POL is 0 */
ret[1] = 0;
ret[2] = r;
i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
debug("RRP_OPCODE returned success data is %x\n", ret[0]);
return ret[0];
} else {
return -1;
}
}
/* Write Data d into DPM register r (RAM) */
int dpm_wrm(u8 r, u8 d)
{
u8 ret[5];
ret[0] = WRM_OPCODE;
ret[1] = r;
ret[2] = d;
i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
debug("WRM_OPCODE returned success data is %x\n", ret[0]);
return ret[0];
} else {
return -1;
}
}
/* Write Data d into Register r of POL(s) a */
int dpm_wrp(u8 r, u8 d)
{
u8 ret[7];
ret[0] = WRP_OPCODE;
/* only POL0 is present */
ret[1] = 0x01;
ret[2] = 0x00;
ret[3] = 0x00;
ret[4] = 0x00;
ret[5] = r;
ret[6] = d;
i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
debug("WRP_OPCODE returned success data is %x\n", ret[0]);
return 0;
} else {
return -1;
}
}
/* Uses the DPM command RRP */
u8 zm_read(uchar reg)
{
u8 d;
d = dpm_rrp(reg);
return d;
}
/* ZM_write --
Steps:
a. Write data to the register
b. Read data from register and compare to written value
c. Return return_code & voltage_read
*/
u8 zm_write(u8 reg, u8 data)
{
u8 d;
/* write data to register */
dpm_wrp(reg, data);
/* read register and compare to written value */
d = dpm_rrp(reg);
if (d != data) {
printf("zm_write : Comparison register data failed\n");
return -1;
}
return d;
}
/* zm_write_out_voltage
* voltage in 1/10 mV
*/
int zm_write_voltage(int voltage)
{
u8 reg = 0x7, vid;
uint16_t voltage_read;
u8 ret;
vid = (voltage - 5000) / ZM_STEP;
ret = zm_write(reg, vid);
if (ret != -1) {
voltage_read = hex_to_1_10mv[ret];
debug("voltage set to %dmV\n", voltage_read/10);
return voltage_read;
}
return -1;
}
/* zm_read_out_voltage
* voltage in 1/10 mV
*/
int zm_read_voltage(void)
{
u8 reg = 0x7;
u8 ret;
int voltage;
ret = zm_read(reg);
if (ret != -1) {
voltage = hex_to_1_10mv[ret];
debug("Voltage read is %dmV\n", voltage/10);
return voltage;
} else {
return -1;
}
}
int zm_disable_wp()
{
u8 new_wp_value;
/* Disable using Write-Protect register 0x96 */
new_wp_value = 0x8;
if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
printf("Disable Write-Protect register failed\n");
return -1;
}
return 0;
}
int zm_enable_wp()
{
u8 orig_wp_value;
orig_wp_value = 0x0;
/* Enable using Write-Protect register 0x96 */
if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
printf("Enable Write-Protect register failed\n");
return -1;
}
return 0;
}

22
board/freescale/common/zm7300.h Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ZM7300_H_
#define __ZM7300_H 1_
#include <common.h>
#include <i2c.h>
#include <errno.h>
#include <asm/io.h>
#define ZM_STEP 125
int zm7300_set_voltage(int voltage_1_10mv);
int zm_write_voltage(int voltage);
int zm_read_voltage(void);
int zm_disable_wp(void);
int zm_enable_wp(void);
#endif /* __ZM7300_H_ */

21
board/freescale/p1_p2_rdb/Makefile
View File

@ -4,8 +4,27 @@
# SPDX-License-Identifier: GPL-2.0+
#
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o tlb.o law.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += p1_p2_rdb.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-$(CONFIG_PCI) += pci.o
obj-y += tlb.o
endif

16
board/freescale/p1_p2_rdb/ddr.c
View File

@ -180,27 +180,22 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
phys_size_t fixed_sdram (void)
{
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
cpu = gd->arch.cpu;
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
} else {
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#if defined(CONFIG_SYS_RAMBOOT)
return ddr_size;
#endif
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
@ -211,8 +206,7 @@ phys_size_t fixed_sdram (void)
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {

141
board/freescale/p1_p2_rdb/spl.c Normal file
View File

@ -0,0 +1,141 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
#include <nand.h>
#include <i2c.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
#define SYSCLK_MASK 0x00200000
#define BOARDREV_MASK 0x10100000
#define SYSCLK_66 66666666
#define SYSCLK_100 100000000
unsigned long get_board_sys_clk(ulong dummy)
{
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
u32 val_gpdat, sysclk_gpio;
val_gpdat = in_be32(&pgpio->gpdat);
sysclk_gpio = val_gpdat & SYSCLK_MASK;
if (sysclk_gpio == 0)
return SYSCLK_66;
else
return SYSCLK_100;
return 0;
}
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
setbits_be32(&gur->pmuxcr,
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
#ifdef CONFIG_SPL_SPI_BOOT
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
#endif
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = bus_clk;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI Flash boot...\n");
#endif
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
puts("Second program loader running in sram...\n");
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

84
board/freescale/p1_p2_rdb/spl_minimal.c Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define SYSCLK_MASK 0x00200000
#define BOARDREV_MASK 0x10100000
#define SYSCLK_66 66666666
#define SYSCLK_100 100000000
unsigned long get_board_sys_clk(ulong dummy)
{
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
u32 val_gpdat, sysclk_gpio;
val_gpdat = in_be32(&pgpio->gpdat);
sysclk_gpio = val_gpdat & SYSCLK_MASK;
if (sysclk_gpio == 0)
return SYSCLK_66;
else
return SYSCLK_100;
return 0;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
puts("\nSecond program loader running in sram...");
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

18
board/freescale/p1_p2_rdb/tlb.c
View File

@ -37,6 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@ -55,6 +56,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 4, BOOKE_PAGESZ_256K, 1),
#endif /* #if defined(CONFIG_PCI) */
#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@ -65,7 +67,21 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT)
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#if CONFIG_SYS_L2_SIZE >= (256 << 10)
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_256K, 1),
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1)

20
board/freescale/qemu-ppce500/qemu-ppce500.c
View File

@ -346,3 +346,23 @@ ulong get_bus_freq (ulong dummy)
get_sys_info(&sys_info);
return sys_info.freq_systembus;
}
/*
* Return the number of cores on this SOC.
*/
int cpu_numcores(void)
{
/*
* The QEMU u-boot target only needs to drive the first core,
* spinning and device tree nodes get driven by QEMU itself
*/
return 1;
}
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
u32 cpu_mask(void)
{
return (1 << cpu_numcores()) - 1;
}

2
board/freescale/t104xrdb/t104xrdb.c
View File

@ -109,6 +109,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);

12
board/freescale/t4rdb/Makefile Normal file
View File

@ -0,0 +1,12 @@
#
# Copyright 2014 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_T4240RDB) += t4240rdb.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
obj-y += tlb.o

118
board/freescale/t4rdb/ddr.c Normal file
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@ -0,0 +1,118 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
/*
* we use identical timing for all slots. If needed, change the code
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
*/
if (popts->registered_dimm_en)
pbsp = rdimms[0];
else
pbsp = udimms[0];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found for data\n"
"rate %lu MT/s\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
"wrlvl_ctrl_3 0x%x\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}

78
board/freescale/t4rdb/ddr.h Normal file
View File

@ -0,0 +1,78 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR_H__
#define __DDR_H__
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};
/*
* These tables contain all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
{}
};
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
{}
};
/*
* The three slots have slightly different timing. The center values are good
* for all slots. We use identical speed tables for them. In future use, if
* DIMMs require separated tables, make more entries as needed.
*/
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
/*
* The three slots have slightly different timing. See comments above.
*/
static const struct board_specific_parameters *rdimms[] = {
rdimm0,
};
#endif

146
board/freescale/t4rdb/eth.c Normal file
View File

@ -0,0 +1,146 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* Chunhe Lan <Chunhe.Lan@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
#include "../common/fman.h"
#include "t4rdb.h"
void fdt_fixup_board_enet(void *fdt)
{
return;
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
if (srds_prtcl_s1 == 28) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
} else {
puts("Invalid SerDes1 protocol for T4240RDB\n");
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
if (srds_prtcl_s2 == 56) {
/* SGMII && XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
} else {
puts("Invalid SerDes2 protocol for T4240RDB\n");
}
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
#endif /* CONFIG_SYS_NUM_FMAN */
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

28
board/freescale/t4rdb/law.c Normal file
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@ -0,0 +1,28 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

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