mirror of
https://github.com/brain-hackers/u-boot-brain
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powerpc: mpc8xx: remove svm_sc8xx board
This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
0ace4d9d8f
commit
d1a4aafd71
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@ -53,9 +53,6 @@ config TARGET_SXNI855T
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config TARGET_SPD823TS
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bool "Support SPD823TS"
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config TARGET_SVM_SC8XX
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bool "Support svm_sc8xx"
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config TARGET_MHPC
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bool "Support MHPC"
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@ -150,7 +147,6 @@ source "board/netvia/Kconfig"
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source "board/r360mpi/Kconfig"
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source "board/sixnet/Kconfig"
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source "board/spd8xx/Kconfig"
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source "board/svm_sc8xx/Kconfig"
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source "board/tqc/tqm8xx/Kconfig"
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endmenu
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@ -44,11 +44,7 @@ void cpu_init_f (volatile immap_t * immr)
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#endif /* CONFIG_WATCHDOG */
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/* SIUMCR - contains debug pin configuration (11-6) */
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#ifndef CONFIG_SVM_SC8xx
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immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
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#else
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immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
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#endif
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/* initialize timebase status and control register (11-26) */
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/* unlock TBSCRK */
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@ -1,11 +0,0 @@
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if TARGET_SVM_SC8XX
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config SYS_BOARD
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string
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default "svm_sc8xx"
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config SYS_CONFIG_NAME
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string
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default "svm_sc8xx"
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endif
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@ -1,6 +0,0 @@
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SVM_SC8XX BOARD
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M: John Zhan <zhanz@sinovee.com>
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S: Orphan (since 2014-06)
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F: board/svm_sc8xx/
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F: include/configs/svm_sc8xx.h
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F: configs/svm_sc8xx_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = svm_sc8xx.o flash.o
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@ -1,666 +0,0 @@
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/*
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#ifndef CONFIG_ENV_ADDR
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#endif
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static int write_word(flash_info_t *info, ulong dest, ulong data);
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#ifdef CONFIG_BOOT_8B
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static int my_in_8(unsigned char *addr);
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static void my_out_8(unsigned char *addr, int val);
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#endif
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#ifdef CONFIG_BOOT_16B
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static int my_in_be16(unsigned short *addr);
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static void my_out_be16(unsigned short *addr, int val);
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#endif
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#ifdef CONFIG_BOOT_32B
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static unsigned my_in_be32(unsigned *addr);
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static void my_out_be32(unsigned *addr, int val);
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#endif
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init(void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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unsigned long size_b0, size_b1;
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int i;
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size_b0 = 0;
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size_b1 = 0;
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/* Init: no FLASHes known */
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
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flash_info[i].flash_id = FLASH_UNKNOWN;
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#ifdef CONFIG_SYS_DOC_BASE
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#ifndef CONFIG_FEL8xx_AT
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/* 32k bytes */
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memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC);
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memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401;
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#else
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/* 32k bytes */
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memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC);
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memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401;
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#endif
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#endif
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#if defined(CONFIG_BOOT_8B)
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size_b0 = 0x80000; /* 512 K */
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flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040;
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flash_info[0].sector_count = 8;
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flash_info[0].size = 0x00080000;
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/* set up sector start address table */
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for (i = 0; i < flash_info[0].sector_count; i++)
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flash_info[0].start[i] = 0x40000000 + (i * 0x10000);
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/* protect all sectors */
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for (i = 0; i < flash_info[0].sector_count; i++)
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flash_info[0].protect[i] = 0x1;
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#elif defined(CONFIG_BOOT_16B)
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size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */
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flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B;
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flash_info[0].sector_count = 67;
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flash_info[0].size = 0x00400000;
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/* set up sector start address table */
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flash_info[0].start[0] = 0x40000000;
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flash_info[0].start[1] = 0x40000000 + 0x4000;
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flash_info[0].start[2] = 0x40000000 + 0x6000;
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flash_info[0].start[3] = 0x40000000 + 0x8000;
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for (i = 4; i < flash_info[0].sector_count; i++) {
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flash_info[0].start[i] =
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0x40000000 + 0x10000 + ((i - 4) * 0x10000);
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}
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/* protect all sectors */
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for (i = 0; i < flash_info[0].sector_count; i++)
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flash_info[0].protect[i] = 0x1;
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#endif
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#ifdef CONFIG_BOOT_32B
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM,
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&flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0 << 20);
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}
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size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
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&flash_info[1]);
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if (size_b1 > size_b0) {
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printf("## ERROR: "
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"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
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size_b1, size_b1 << 20, size_b0, size_b0 << 20);
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flash_info[0].flash_id = FLASH_UNKNOWN;
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flash_info[1].flash_id = FLASH_UNKNOWN;
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flash_info[0].sector_count = -1;
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flash_info[1].sector_count = -1;
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flash_info[0].size = 0;
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flash_info[1].size = 0;
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return 0;
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}
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/* Remap FLASH according to real size */
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH |
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(-size_b0 & OR_AM_MSK);
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
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BR_MS_GPCM | BR_V;
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/* Re-do sizing to get full correct info */
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size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE,
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&flash_info[0]);
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flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[0]);
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
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#endif
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if (size_b1) {
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memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
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(-size_b1 & 0xFFFF8000);
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memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE +
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size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
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/* Re-do sizing to get full correct info */
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size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE +
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size_b0), &flash_info[1]);
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flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0,
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&flash_info[1]);
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[1]);
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
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&flash_info[1]);
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#endif
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} else {
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memctl->memc_br1 = 0; /* invalidate bank */
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flash_info[1].flash_id = FLASH_UNKNOWN;
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flash_info[1].sector_count = -1;
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}
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flash_info[0].size = size_b0;
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flash_info[1].size = size_b1;
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#endif /* CONFIG_BOOT_32B */
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return size_b0 + size_b1;
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}
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void flash_print_info(flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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printf("AMD ");
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break;
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case FLASH_MAN_FUJ:
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printf("FUJITSU ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM400B:
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printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM400T:
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printf("AM29LV400T (4 Mbit, top boot sector)\n");
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break;
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case FLASH_AM800B:
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printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM800T:
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printf("AM29LV800T (8 Mbit, top boot sector)\n");
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break;
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case FLASH_AM160B:
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printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM160T:
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printf("AM29LV160T (16 Mbit, top boot sector)\n");
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break;
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case FLASH_AM320B:
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printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM320T:
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printf("AM29LV320T (32 Mbit, top boot sector)\n");
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break;
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default:
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printf("Unknown Chip Type\n");
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break;
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}
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printf(" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf(" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf("\n ");
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printf(" %08lX%s",
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info->start[i], info->protect[i] ? " (RO)" : " ");
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}
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printf("\n");
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return;
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}
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/*
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* The following code cannot be run from FLASH!
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*/
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int flash_erase(flash_info_t *info, int s_first, int s_last)
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{
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vu_long *addr = (vu_long *) (info->start[0]);
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int flag, prot, sect, l_sect, in_mid, in_did;
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ulong start, now, last;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN)
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printf("- missing\n");
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else
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printf("- no sectors to erase\n");
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return 1;
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}
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if ((info->flash_id == FLASH_UNKNOWN) ||
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(info->flash_id > FLASH_AMD_COMP)) {
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printf("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect])
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prot++;
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}
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if (prot) {
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printf("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf("\n");
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}
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l_sect = -1;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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#if defined(CONFIG_BOOT_8B)
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my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
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my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
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my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90);
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in_mid = my_in_8((unsigned char *)addr);
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in_did = my_in_8((unsigned char *)((ulong)addr + 1));
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printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
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my_out_8((unsigned char *)addr, 0xf0);
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udelay(1);
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my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
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my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
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my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80);
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my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
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my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr = (vu_long *) (info->start[sect]);
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/*addr[0] = 0x00300030; */
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my_out_8((unsigned char *)((ulong)addr), 0x30);
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l_sect = sect;
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}
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}
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#elif defined(CONFIG_BOOT_16B)
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my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa);
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my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55);
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my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90);
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in_mid = my_in_be16((unsigned short *)addr);
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in_did = my_in_be16((unsigned short *)((ulong)addr + 2));
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printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
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my_out_be16((unsigned short *)addr, 0xf0);
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udelay(1);
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my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
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my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
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my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80);
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my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
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my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr = (vu_long *) (info->start[sect]);
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my_out_be16((unsigned short *)((ulong)addr), 0x30);
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l_sect = sect;
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}
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}
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#elif defined(CONFIG_BOOT_32B)
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my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
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my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
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my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90);
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in_mid = my_in_be32((unsigned *)addr);
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in_did = my_in_be32((unsigned *)((ulong)addr + 4));
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printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
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my_out_be32((unsigned *) addr, 0xf0);
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udelay(1);
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my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
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my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
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my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80);
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my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
|
||||
my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_long *) (info->start[sect]);
|
||||
my_out_be32((unsigned *)((ulong)addr), 0x00300030);
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
#error CONFIG_BOOT_(size)B missing.
|
||||
#endif
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay(1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer(0);
|
||||
last = start;
|
||||
addr = (vu_long *) (info->start[l_sect]);
|
||||
#if defined(CONFIG_BOOT_8B)
|
||||
while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80)
|
||||
#elif defined(CONFIG_BOOT_16B)
|
||||
while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080)
|
||||
#elif defined(CONFIG_BOOT_32B)
|
||||
while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080)
|
||||
#else
|
||||
#error CONFIG_BOOT_(size)B missing.
|
||||
#endif
|
||||
{
|
||||
now = get_timer(start);
|
||||
if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (volatile unsigned long *) info->start[0];
|
||||
|
||||
#if defined(CONFIG_BOOT_8B)
|
||||
my_out_8((unsigned char *) addr, 0xf0);
|
||||
#elif defined(CONFIG_BOOT_16B)
|
||||
my_out_be16((unsigned short *) addr, 0x00f0);
|
||||
#elif defined(CONFIG_BOOT_32B)
|
||||
my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */
|
||||
#else
|
||||
#error CONFIG_BOOT_(size)B missing.
|
||||
#endif
|
||||
printf(" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
l = addr - wp;
|
||||
|
||||
if (l != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp)
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
|
||||
for (; i < 4 && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < 4; ++i, ++cp)
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
|
||||
rc = write_word(info, wp, data);
|
||||
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i = 0; i < 4; ++i)
|
||||
data = (data << 8) | *src++;
|
||||
|
||||
rc = write_word(info, wp, data);
|
||||
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < 4; ++i, ++cp)
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
|
||||
return write_word(info, wp, data);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word(flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
ulong addr = (ulong) (info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
ulong i;
|
||||
int data_short[2];
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if (((ulong)*(ulong *)dest & data) != data)
|
||||
return 2;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
#if defined(CONFIG_BOOT_8B)
|
||||
#ifdef DEBUG
|
||||
{
|
||||
int in_mid, in_did;
|
||||
|
||||
my_out_8((unsigned char *) (addr + 0x555), 0xaa);
|
||||
my_out_8((unsigned char *) (addr + 0x2aa), 0x55);
|
||||
my_out_8((unsigned char *) (addr + 0x555), 0x90);
|
||||
|
||||
in_mid = my_in_8((unsigned char *) addr);
|
||||
in_did = my_in_8((unsigned char *) (addr + 1));
|
||||
|
||||
printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
|
||||
|
||||
my_out_8((unsigned char *) addr, 0xf0);
|
||||
udelay(1);
|
||||
}
|
||||
#endif
|
||||
{
|
||||
int data_ch[4];
|
||||
|
||||
data_ch[0] = (int) ((data >> 24) & 0xff);
|
||||
data_ch[1] = (int) ((data >> 16) & 0xff);
|
||||
data_ch[2] = (int) ((data >> 8) & 0xff);
|
||||
data_ch[3] = (int) (data & 0xff);
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
my_out_8((unsigned char *) (addr + 0x555), 0xaa);
|
||||
my_out_8((unsigned char *) (addr + 0x2aa), 0x55);
|
||||
my_out_8((unsigned char *) (addr + 0x555), 0xa0);
|
||||
my_out_8((unsigned char *) (dest + i), data_ch[i]);
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer(0);
|
||||
while ((my_in_8((unsigned char *)(dest + i))) !=
|
||||
(data_ch[i])) {
|
||||
if (get_timer(start) >
|
||||
CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
} /* for */
|
||||
}
|
||||
#elif defined(CONFIG_BOOT_16B)
|
||||
data_short[0] = (int) (data >> 16) & 0xffff;
|
||||
data_short[1] = (int) data & 0xffff;
|
||||
for (i = 0; i < 2; i++) {
|
||||
my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
|
||||
my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
|
||||
my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0);
|
||||
my_out_be16((unsigned short *)(dest + (i * 2)),
|
||||
data_short[i]);
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer(0);
|
||||
while ((my_in_be16((unsigned short *)(dest + (i * 2)))) !=
|
||||
(data_short[i])) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_BOOT_32B)
|
||||
addr[0x0555] = 0x00AA00AA;
|
||||
addr[0x02AA] = 0x00550055;
|
||||
addr[0x0555] = 0x00A000A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer(0);
|
||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOOT_8B
|
||||
static int my_in_8(unsigned char *addr)
|
||||
{
|
||||
int ret;
|
||||
__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void my_out_8(unsigned char *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_BOOT_16B
|
||||
static int my_in_be16(unsigned short *addr)
|
||||
{
|
||||
int ret;
|
||||
__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void my_out_be16(unsigned short *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_BOOT_32B
|
||||
static unsigned my_in_be32(unsigned *addr)
|
||||
{
|
||||
unsigned ret;
|
||||
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void my_out_be32(unsigned *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
const uint sdram_table[] =
|
||||
{
|
||||
/*-----------------
|
||||
UPM A contents:
|
||||
----------------- */
|
||||
/*---------------------------------------------------
|
||||
Read Single Beat Cycle. Offset 0 in the RAM array.
|
||||
---------------------------------------------------- */
|
||||
0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 ,
|
||||
0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 ,
|
||||
/*------------------------------------------------
|
||||
Read Burst Cycle. Offset 0x8 in the RAM array.
|
||||
------------------------------------------------ */
|
||||
0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
|
||||
0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
/*-------------------------------------------------------
|
||||
Write Single Beat Cycle. Offset 0x18 in the RAM array
|
||||
------------------------------------------------------- */
|
||||
0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 ,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
|
||||
/*-------------------------------------------------
|
||||
Write Burst Cycle. Offset 0x20 in the RAM array
|
||||
------------------------------------------------- */
|
||||
0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
|
||||
0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
|
||||
/*------------------------------------------------------------------------
|
||||
Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
|
||||
------------------------------------------------------------------------ */
|
||||
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
|
||||
/*-----------
|
||||
* Exception:
|
||||
* ----------- */
|
||||
0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff ,
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*
|
||||
* Test ID string (SVM8...)
|
||||
*
|
||||
* Return 1 for "SC8xx" type, 0 else.
|
||||
*/
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char buf[64];
|
||||
int i;
|
||||
int l = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
if (l < 0 || strncmp(buf, "SVM8", 4)) {
|
||||
printf("### No HW ID - assuming SVM SC8xx\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
for (i = 0; i < l; ++i) {
|
||||
if (buf[i] == ' ')
|
||||
break;
|
||||
putc(buf[i]);
|
||||
}
|
||||
|
||||
putc('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
long int size_b0 = 0;
|
||||
|
||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
||||
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
#if defined (CONFIG_SDRAM_16M)
|
||||
memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx;
|
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
|
||||
udelay(1);
|
||||
memctl->memc_mcr = 0x80002830;
|
||||
udelay(1);
|
||||
memctl->memc_mar = 0x00000088;
|
||||
udelay(1);
|
||||
memctl->memc_mcr = 0x80002106;
|
||||
udelay(1);
|
||||
memctl->memc_or1 = 0xff000a00;
|
||||
size_b0 = 0x01000000;
|
||||
#elif defined (CONFIG_SDRAM_32M)
|
||||
memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx;
|
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
|
||||
udelay(1);
|
||||
memctl->memc_mcr = 0x80002830;
|
||||
udelay(1);
|
||||
memctl->memc_mar = 0x00000088;
|
||||
udelay(1);
|
||||
memctl->memc_mcr = 0x80002106;
|
||||
udelay(1);
|
||||
memctl->memc_or1 = 0xfe000a00;
|
||||
size_b0 = 0x02000000;
|
||||
#elif defined (CONFIG_SDRAM_64M)
|
||||
memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx;
|
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
|
||||
udelay(1);
|
||||
memctl->memc_mcr = 0x80002830;
|
||||
udelay(1);
|
||||
memctl->memc_mar = 0x00000088;
|
||||
udelay(1);
|
||||
memctl->memc_mcr = 0x80002106;
|
||||
udelay(1);
|
||||
memctl->memc_or1 = 0xfc000a00;
|
||||
size_b0 = 0x04000000;
|
||||
#else
|
||||
#error SDRAM size configuration missing.
|
||||
#endif
|
||||
memctl->memc_br1 = 0x00000081;
|
||||
udelay(200);
|
||||
return (size_b0 );
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_DOC)
|
||||
void doc_init (void)
|
||||
{
|
||||
doc_probe (CONFIG_SYS_DOC_BASE);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
lib/built-in.o (.text*)
|
||||
net/built-in.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
|
||||
arch/powerpc/lib/built-in.o (.text*)
|
||||
board/svm_sc8xx/built-in.o (.text*)
|
||||
*(.text.*printf)
|
||||
*(.text.do_mem_*)
|
||||
*(.text.flash*)
|
||||
*(.text.run_command)
|
||||
*(.text.main_loop)
|
||||
*(.text.srec_decode)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o (.ppcenv*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/vsprintf.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_8xx=y
|
||||
CONFIG_TARGET_SVM_SC8XX=y
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
svm_sc8xx powerpc mpc8xx - - John Zhan <zhanz@sinovee.com>
|
||||
stxxtc powerpc mpc8xx - - Dan Malek <dan@embeddedalley.com>
|
||||
omap5912osk arm arm926ejs - - Rishi Bhattacharya <rishi@ti.com>
|
||||
p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
|
|
|||
|
|
@ -20,14 +20,12 @@
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_PCMCIA) \
|
||||
&& (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx))
|
||||
&& defined(CONFIG_TQM8xxL)
|
||||
|
||||
#if defined(CONFIG_VIRTLAB2)
|
||||
#define PCMCIA_BOARD_MSG "Virtlab2"
|
||||
#elif defined(CONFIG_TQM8xxL)
|
||||
#define PCMCIA_BOARD_MSG "TQM8xxL"
|
||||
#elif defined(CONFIG_SVM_SC8xx)
|
||||
#define PCMCIA_BOARD_MSG "SC8xx"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_NSCU)
|
||||
|
|
@ -302,4 +300,4 @@ done:
|
|||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */
|
||||
#endif /* CONFIG_PCMCIA && CONFIG_TQM8xxL */
|
||||
|
|
|
|||
|
|
@ -779,57 +779,6 @@ typedef struct scc_enet {
|
|||
|
||||
/*** NETVIA *******************************************************/
|
||||
|
||||
/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
|
||||
#if ( defined CONFIG_SVM_SC8xx )
|
||||
# ifndef CONFIG_FEC_ENET
|
||||
|
||||
#define PROFF_ENET PROFF_SCC2
|
||||
#define CPM_CR_ENET CPM_CR_CH_SCC2
|
||||
#define SCC_ENET 1
|
||||
|
||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||
* * * * to configure the pins for SCC2 use.
|
||||
* * * */
|
||||
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
|
||||
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
|
||||
#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
|
||||
#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
|
||||
|
||||
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
|
||||
|
||||
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
|
||||
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
|
||||
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
|
||||
* * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
|
||||
* * * */
|
||||
#define SICR_ENET_MASK ((uint)0x0000ff00)
|
||||
#define SICR_ENET_CLKRT ((uint)0x00003700)
|
||||
|
||||
# else /* Use FEC for Fast Ethernet */
|
||||
|
||||
#undef SCC_ENET
|
||||
#define FEC_ENET
|
||||
|
||||
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
|
||||
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
|
||||
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
|
||||
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
|
||||
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
|
||||
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
|
||||
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
|
||||
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
|
||||
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
|
||||
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
|
||||
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
|
||||
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
|
||||
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
|
||||
|
||||
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
|
||||
|
||||
# endif /* CONFIG_FEC_ENET */
|
||||
#endif /* CONFIG_SVM_SC8xx */
|
||||
|
||||
|
||||
#if defined(CONFIG_NETVIA)
|
||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||
* to configure the pins for SCC2 use.
|
||||
|
|
|
|||
|
|
@ -1,450 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000, 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific,
|
||||
* for SinoVee Microsystems SC8xx series SBC
|
||||
* http://www.fel.com.cn (Chinese)
|
||||
* http://www.sinovee.com (English)
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000
|
||||
|
||||
/* Custom configuration */
|
||||
/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
|
||||
/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
|
||||
/*#define CONFIG_FEL8xx_AT */
|
||||
/*#define CONFIG_LCD */
|
||||
/*#define CONFIG_MPC8XX_LCD*/
|
||||
/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
|
||||
/* #define CONFIG_50MHz */
|
||||
/* #define CONFIG_66MHz */
|
||||
/* #define CONFIG_75MHz */
|
||||
#define CONFIG_80MHz
|
||||
/*#define CONFIG_100MHz */
|
||||
/* #define CONFIG_BUS_DIV2 1 */
|
||||
/* for BOOT device port size */
|
||||
/* #define CONFIG_BOOT_8B */
|
||||
#define CONFIG_BOOT_16B
|
||||
/* #define CONFIG_BOOT_32B */
|
||||
/* #define CONFIG_CAN_DRIVER */
|
||||
/* #define DEBUG */
|
||||
#define CONFIG_FEC_ENET
|
||||
|
||||
/* #define CONFIG_SDRAM_16M */
|
||||
#define CONFIG_SDRAM_32M
|
||||
/* #define CONFIG_SDRAM_64M */
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xffffffff
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
/* #define CONFIG_MPC823 1 */
|
||||
/* #define CONFIG_MPC850 1 */
|
||||
#define CONFIG_MPC855 1
|
||||
/* #define CONFIG_MPC860 1 */
|
||||
/* #define CONFIG_MPC860T 1 */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog */
|
||||
|
||||
#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
|
||||
|
||||
#ifdef CONFIG_LCD /* with LCD controller ? */
|
||||
/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
|
||||
#endif
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
|
||||
"bootfile=pImage-sc855t\0" \
|
||||
"kernel_addr=48000000\0" \
|
||||
"ramdisk_addr=48100000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
||||
"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
# undef CONFIG_STATUS_LED /* disturbs display */
|
||||
#else
|
||||
# define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
#endif /* CONFIG_LCD */
|
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFF000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0x40000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#ifdef CONFIG_BOOT_8B
|
||||
#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
#elif defined (CONFIG_BOOT_16B)
|
||||
#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
#elif defined (CONFIG_BOOT_32B)
|
||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
#endif
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block
|
||||
*/
|
||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
|
||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
|
||||
#define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
/*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
*/
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR 0xffffff88
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#ifndef CONFIG_CAN_DRIVER
|
||||
/*#define CONFIG_SYS_SIUMCR 0x00610c00 */
|
||||
#define CONFIG_SYS_SIUMCR 0x00000000
|
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR 0x0001
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RTCSC 0x00c3
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR 0x0000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*/
|
||||
#if defined (CONFIG_100MHz)
|
||||
#define CONFIG_SYS_PLPRCR 0x06301000
|
||||
#define CONFIG_8xx_GCLK_FREQ 100000000
|
||||
#elif defined (CONFIG_80MHz)
|
||||
#define CONFIG_SYS_PLPRCR 0x04f01000
|
||||
#define CONFIG_8xx_GCLK_FREQ 80000000
|
||||
#elif defined(CONFIG_75MHz)
|
||||
#define CONFIG_SYS_PLPRCR 0x04a00100
|
||||
#define CONFIG_8xx_GCLK_FREQ 75000000
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CONFIG_SYS_PLPRCR 0x04101000
|
||||
#define CONFIG_8xx_GCLK_FREQ 66000000
|
||||
#elif defined(CONFIG_50MHz)
|
||||
#define CONFIG_SYS_PLPRCR 0x03101000
|
||||
#define CONFIG_8xx_GCLK_FREQ 50000000
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_BUS_DIV2
|
||||
#define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL
|
||||
#else /* up to 50 MHz we use a 1:1 clock */
|
||||
#define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
|
||||
#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
|
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
/*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
|
||||
*/
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
|
||||
*/
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
|
||||
*/
|
||||
#define CONFIG_ATAPI
|
||||
#define CONFIG_SYS_PIO_MODE 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
/*#define CONFIG_SYS_DER 0x2002000F*/
|
||||
#define CONFIG_SYS_DER 0x0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
|
||||
#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4
|
||||
#define CONFIG_SYS_MxMR_PTx 0x61000000
|
||||
#define CONFIG_SYS_MPTPR 0x400
|
||||
|
||||
#elif defined(CONFIG_80MHz)
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
|
||||
#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4
|
||||
#define CONFIG_SYS_MxMR_PTx 0x4e000000
|
||||
#define CONFIG_SYS_MPTPR 0x400
|
||||
|
||||
#elif defined(CONFIG_75MHz)
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
|
||||
#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4
|
||||
#define CONFIG_SYS_MxMR_PTx 0x49000000
|
||||
#define CONFIG_SYS_MPTPR 0x400
|
||||
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */
|
||||
#define CONFIG_SYS_OR_TIMING_DOC 0x000003f4
|
||||
#define CONFIG_SYS_MxMR_PTx 0x40000000
|
||||
#define CONFIG_SYS_MPTPR 0x400
|
||||
|
||||
#else /* 50 MHz */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
|
||||
#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4
|
||||
#define CONFIG_SYS_MxMR_PTx 0x30000000
|
||||
#define CONFIG_SYS_MPTPR 0x400
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
|
||||
#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
|
||||
#define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
|
||||
#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
|
||||
#define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
|
||||
#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
|
||||
#define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||
#else
|
||||
#error Boot device port size missing.
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Disk-On-Chip configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_DOC_SHORT_TIMEOUT
|
||||
#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
|
||||
|
||||
#define CONFIG_SYS_DOC_SUPPORT_2000
|
||||
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
|
||||
#define CONFIG_SYS_DOC_BASE 0x80000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
|
||||
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
|
||||
|
||||
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
|
||||
#if defined(CONFIG_TQM8xxL)
|
||||
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
|
||||
#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
|
|
|
|||
|
|
@ -217,20 +217,6 @@ void status_led_set (int led, int state);
|
|||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
#elif defined(CONFIG_SVM_SC8xx)
|
||||
# define STATUS_LED_PAR im_cpm.cp_pbpar
|
||||
# define STATUS_LED_DIR im_cpm.cp_pbdir
|
||||
# define STATUS_LED_ODR im_cpm.cp_pbodr
|
||||
# define STATUS_LED_DAT im_cpm.cp_pbdat
|
||||
|
||||
# define STATUS_LED_BIT 0x00000001
|
||||
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
||||
# define STATUS_LED_STATE STATUS_LED_BLINKING
|
||||
|
||||
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
||||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
#elif defined(CONFIG_V38B)
|
||||
|
||||
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user