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driver/nand:Define MAX_BANKS same as SoC defined for IFC

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The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Prabhakar Kushwaha 2014-06-12 09:13:08 +05:30 committed by York Sun
parent d0bc51407c
commit 3bab3d8324
1 changed files with 5 additions and 1 deletions
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6
drivers/mtd/nand/fsl_ifc_nand.c
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@ -19,8 +19,12 @@
#include <asm/errno.h>
#include <fsl_ifc.h>
#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#endif
#define FSL_IFC_V1_1_0 0x01010000
#define MAX_BANKS 4
#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
#define ERR_BYTE 0xFF /* Value returned for read bytes
when read failed */
#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC