Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.
This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This driver was written for Arria10, but it applies to Gen5, too.
The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.
This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.
Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.
To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.
Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.
Disable the bits to prevent an interrupt storm when Linux enables
the UART interrupts.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Do the regulator related work only if the build has the DM_REGULATOR.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
phy_reset should be called before autoneg is setup
The only boards using MV88E61XX_SWITCH are:
- alliedtelesis/SBx81LIFKW
- alliedtelesis/SBx81LIFXCAT
- gateworks/gw_ventana
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
The initialization of the NAND in SPL hard-coded ecc.bytes,
ecc.size, and ecc.strength which may work for some NAND parts,
but it not appropriate for others. With the pending patch
"mxs_nand: Fix BCH read timeout error on boards requiring ECC"
the driver can auto configure the ECC when these entries are
blank. This patch has been tested in NAND flash with oob 64
and oob 128.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
When DM_REGULATOR is enabled, the driver attempts to call
regulator_autoset() which expects the regulators to be on at boot
and/or always on and fails if they are not true.
For a more generic approach, this patch just calls
regulator_set_enable() which shouldn't have such restrictions.
Fixes: ad8c43cbca ("net: dm: fec: Support the phy-supply
binding")
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
mxs_nand_init_dma is only referenced from mxs_nand.c. It's not
referenced in any headers or outside code, so this patch
defines it as static.
Signed-off-by: Adam Ford <aford173@gmail.com>
The LogicPD board uses a Micron Flash with ECC. To boot this from
SPL, the ECC needs to be correctly configured or the BCH engine
times out.
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
All platforms are converted to DM_I2C that's why there is no reason to
keep this code here.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This driver is replaced by drivers/i2c/i2c-cdns.c DM based driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.
Fixes booting for Apollo Lake processors.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.
Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
For !DM case busses are listed as
ZynqMP> i2c bus
Bus 0: zynq_0
Bus 1: zynq_0->PCA9544A@0x75:0
Bus 2: zynq_0->PCA9544A@0x75:1
Bus 3: zynq_0->PCA9544A@0x75:2
Bus 4: zynq_1
Bus 5: zynq_1->PCA9548@0x74:0
Bus 6: zynq_1->PCA9548@0x74:1
Bus 7: zynq_1->PCA9548@0x74:2
Bus 8: zynq_1->PCA9548@0x74:3
Bus 9: zynq_1->PCA9548@0x74:4
Bus 10: zynq_1->PCA9548@0x75:0
Bus 11: zynq_1->PCA9548@0x75:1
Bus 12: zynq_1->PCA9548@0x75:2
Bus 13: zynq_1->PCA9548@0x75:3
Bus 14: zynq_1->PCA9548@0x75:4
Bus 15: zynq_1->PCA9548@0x75:5
Bus 16: zynq_1->PCA9548@0x75:6
Bus 17: zynq_1->PCA9548@0x75:7
where is exactly describing i2c bus topology.
By moving to DM case i2c mux buses are using names from DT and because
i2c-muxes describing sub busses with the same names like i2c@0, etc it
is hard to identify which bus is where.
Linux is adding topology information to i2c-mux busses to identify them
better.
This patch is doing the same and composing bus name with topology
information.
When patch is applied with topology information on zcu102-revA.
ZynqMP> i2c bus
Bus 0: i2c@ff020000
20: gpio@20, offset len 1, flags 0
21: gpio@21, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 2: i2c@ff020000->i2c-mux@75->i2c@0
Bus 3: i2c@ff020000->i2c-mux@75->i2c@1
Bus 4: i2c@ff020000->i2c-mux@75->i2c@2
Bus 1: i2c@ff030000 (active 1)
74: i2c-mux@74, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@ff030000->i2c-mux@74->i2c@0 (active 5)
54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@ff030000->i2c-mux@74->i2c@1
Bus 7: i2c@ff030000->i2c-mux@74->i2c@2
Bus 8: i2c@ff030000->i2c-mux@74->i2c@3
Bus 9: i2c@ff030000->i2c-mux@74->i2c@4
Bus 10: i2c@ff030000->i2c-mux@75->i2c@0
Bus 11: i2c@ff030000->i2c-mux@75->i2c@1
Bus 12: i2c@ff030000->i2c-mux@75->i2c@2
Bus 13: i2c@ff030000->i2c-mux@75->i2c@3
Bus 14: i2c@ff030000->i2c-mux@75->i2c@4
Bus 15: i2c@ff030000->i2c-mux@75->i2c@5
Bus 16: i2c@ff030000->i2c-mux@75->i2c@6
Bus 17: i2c@ff030000->i2c-mux@75->i2c@7
Behavior before the patch is applied.
ZynqMP> i2c bus
Bus 0: i2c@ff020000
20: gpio@20, offset len 1, flags 0
21: gpio@21, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 2: i2c@0
Bus 3: i2c@1
Bus 4: i2c@2
Bus 1: i2c@ff030000 (active 1)
74: i2c-mux@74, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@0 (active 5)
54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@1
Bus 7: i2c@2
Bus 8: i2c@3
Bus 9: i2c@4
Bus 10: i2c@0
Bus 11: i2c@1
Bus 12: i2c@2
Bus 13: i2c@3
Bus 14: i2c@4
Bus 15: i2c@5
Bus 16: i2c@6
Bus 17: i2c@7
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
For i2c controllers which are missing alias in DT there is no req_seq
setup. This function is setting up proper ID based on highest found
alias ID.
On zcu102 this is the behavior when patch is applied.
ZynqMP> i2c bus
Bus 0: i2c@ff020000
20: gpio@20, offset len 1, flags 0
21: gpio@21, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 2: i2c@0
Bus 3: i2c@1
Bus 4: i2c@2
Bus 1: i2c@ff030000 (active 1)
74: i2c-mux@74, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@0 (active 5)
54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@1
Bus 7: i2c@2
Bus 8: i2c@3
Bus 9: i2c@4
Bus 10: i2c@0
Bus 11: i2c@1
Bus 12: i2c@2
Bus 13: i2c@3
Bus 14: i2c@4
Bus 15: i2c@5
Bus 16: i2c@6
Bus 17: i2c@7
Before this patch applied (controllers have -1 ID)
ZynqMP> i2c bus
Bus 0: i2c@ff020000
20: gpio@20, offset len 1, flags 0
21: gpio@21, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus -1: i2c@0
Bus -1: i2c@1
Bus -1: i2c@2
Bus 1: i2c@ff030000 (active 1)
74: i2c-mux@74, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus -1: i2c@0 (active 0)
54: eeprom@54, offset len 1, flags 0
Bus -1: i2c@1
Bus -1: i2c@2
Bus -1: i2c@3
Bus -1: i2c@4
Bus -1: i2c@0
Bus -1: i2c@1
Bus -1: i2c@2
Bus -1: i2c@3
Bus -1: i2c@4
Bus -1: i2c@5
Bus -1: i2c@6
Bus -1: i2c@7
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
There is a need to find out the first free i2c ID which can be used for
i2s buses (including i2c buses connected to i2c mux). Do it early in
init and share this variable with other i2c classes for uniq bus
identification.
add from hs:
fix build problem in i2c-uclass.c for omap devices
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Common sound support
buildman environment support
of-platdata documentation improvements
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Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dm
Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements
At present there is still some samsung-specific code in the audio codecs.
Remove it so that these can be used by other SoCs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow misc devices to have children, so that we can use this uclass for
cases where a child device (e.g. I2S) needs to access a misc driver for
transferring data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the driver doesn't see an error
when disabling an always-on regulator and when enabling is not supported.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
regulator_set_enable() api throws an error in the following three cases:
- when requested to disable an always-on regulator
- when set_enable() ops not provided by regulator driver
- when enabling is actually failed.(Error returned by the regulator driver)
Sometimes consumer drivers doesn't want to track the first two scenarios
and just need to worry about the case where enabling is actually failed.
But it is also a good practice to have an error value returned in the
first two cases.
So introduce an api regulator_set_enable_if_allowed() which ignores the
first two error cases and returns an error as given by regulator driver.
Consumer drivers can use this api need not worry about the first two
error conditions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This reverts commit e17e0ceb83.
It is advised to return an error when trying to disable an always-on
regulator and let the consumer driver handle the error if needed.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
While uclass_find_device() fails with -ENODEV in case of list_empty
strangely uclass_find_first_device() returns 0.
Fix uclass_find_first_device() to also fail with -ENODEV instead.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) mentions
unexpected tuning pattern errors. A small failure band may be present
in the tuning range which may be missed by the current algorithm.
Furthermore, the failure bands vary with temperature leading to
different optimum tuning values for different temperatures.
As suggested in the related Application Report (SPRACA9B - October 2017
- Revised July 2018 [2]), tuning should be done in two stages.
In stage 1, assign the optimum ratio in the maximum pass window for the
current temperature. In stage 2, if the chosen value is close to the
small failure band, move away from it in the appropriate direction.
References:
[1] http://www.ti.com/lit/pdf/sprz426
[2] http://www.ti.com/lit/pdf/SPRACA9
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of clk dump command and
display information during probe (under CONFIG_DISPLAY_CPUINFO).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Because stgen is initialized with HSI clock, we need to
recalculate the counter when changing frequency.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove support of ck_usbo_48m clock node in device tree,
but force 48MHz frequency to prepare alignment
with kernel device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The DM_FLAG_PRE_RELOC shall be enabled in SBSA PL011 uart driver
as this driver is used in NXP based SoCs
It is necessary to have Serial console running before relocation
The !CONFIG_IS_ENABLED(OF_CONTROL) [*] check is set as "workaround"
for DM problem : 4687919684
This flag is set if board does not support device-tree and using
platform data, In DM Model either of device tree or platform data
can be used to fetch device configuration
It is possible to use SBSA UART with CONFIG_DM_SERIAL but witout
corresponding device tree description (OF_CONTROL)
Other board/SoCs have this flag set unconditionally
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.
Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The internal DMAC asserts DMA transfer end bit too early on older
version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS
delay after the completion of DMA transfer and before invalidating
the cache to let the DMAC fully complete the transfer. Otherwise,
it could happen that the last few bytes of a transferred data are
not available.
A test case to trigger this behavior is the following command, ran
on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted
into SDHI slot 0 and with first partition being of type FAT:
=> while true ; do mmc rescan ; fstype mmc 0:1 ; done
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
It is wrapper for calling of_alias_get_highest_id() when live tree is
enabled and fdtdec_get_alias_highest_id() if not.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The same functionality was added to Linux for i2c bus registration with this
commit message:
"
of: base: add function to get highest id of an alias stem
I2C supports adding adapters using either a dynamic or fixed id. The
latter is provided by aliases in the DT case. To prevent id collisions
of those two types, install this function which gives us the highest
fixed id, so we can then let the dynamically created ones come after
this highest number.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
"
Add it also to U-Boot for DM I2C support.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.
Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
