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clk: stm32mp1: correctly handle Clock Spreading Generator

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To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay 2019-01-30 13:07:06 +01:00 committed by Tom Rini
parent e74b74c528
commit bbd108a082
2 changed files with 12 additions and 6 deletions
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10
doc/device-tree-bindings/clock/st,stm32mp1.txt
View File

@ -132,15 +132,15 @@ Optional Properties:
frac = < 0x810 >;
};
st,pll@1 {
cfg = < 1 43 1 0 0 PQR(0,1,1)>;
csg = <10 20 1>;
cfg = < 1 43 1 0 0 PQR(0,1,1) >;
csg = < 10 20 1 >;
};
st,pll@2 {
cfg = < 2 85 3 13 3 0>;
csg = <10 20 SSCG_MODE_CENTER_SPREAD>;
cfg = < 2 85 3 13 3 0 >;
csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
};
st,pll@3 {
cfg = < 2 78 4 7 9 3>;
cfg = < 2 78 4 7 9 3 >;
};
st,pkcs = <
CLK_STGEN_HSE

8
drivers/clk/clk_stm32mp1.c
View File

@ -165,6 +165,7 @@
/* used for ALL PLLNCR registers */
#define RCC_PLLNCR_PLLON BIT(0)
#define RCC_PLLNCR_PLLRDY BIT(1)
#define RCC_PLLNCR_SSCG_CTRL BIT(2)
#define RCC_PLLNCR_DIVPEN BIT(4)
#define RCC_PLLNCR_DIVQEN BIT(5)
#define RCC_PLLNCR_DIVREN BIT(6)
@ -1319,7 +1320,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
{
const struct stm32mp1_clk_pll *pll = priv->data->pll;
writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
RCC_PLLNCR_DIVREN,
RCC_PLLNCR_PLLON);
}
static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
@ -1438,6 +1442,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
RCC_PLLNCSGR_SSCG_MODE_MASK);
writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
}
static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)