2016-09-27 00:09:26 +09:00
|
|
|
config ARCH_LS1012A
|
2016-10-05 06:31:47 +09:00
|
|
|
bool
|
2017-01-06 18:41:11 +09:00
|
|
|
select ARMV8_SET_SMPEN
|
2016-10-05 06:31:48 +09:00
|
|
|
select FSL_LSCH2
|
2016-10-05 10:03:08 +09:00
|
|
|
select SYS_FSL_DDR_BE
|
2016-09-27 00:09:26 +09:00
|
|
|
select SYS_FSL_MMDC
|
2016-09-27 00:09:27 +09:00
|
|
|
select SYS_FSL_ERRATUM_A010315
|
2017-11-13 17:14:48 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009798
|
|
|
|
select SYS_FSL_ERRATUM_A008997
|
|
|
|
select SYS_FSL_ERRATUM_A009007
|
|
|
|
select SYS_FSL_ERRATUM_A009008
|
2017-01-24 05:31:19 +09:00
|
|
|
select ARCH_EARLY_INIT_R
|
2017-01-24 05:31:20 +09:00
|
|
|
select BOARD_EARLY_INIT_F
|
2017-12-04 12:37:00 +09:00
|
|
|
imply PANIC_HANG
|
2016-09-27 00:09:27 +09:00
|
|
|
|
|
|
|
config ARCH_LS1043A
|
2016-10-05 06:31:47 +09:00
|
|
|
bool
|
2017-01-06 18:41:11 +09:00
|
|
|
select ARMV8_SET_SMPEN
|
2016-10-05 06:31:48 +09:00
|
|
|
select FSL_LSCH2
|
2016-12-29 01:43:40 +09:00
|
|
|
select SYS_FSL_DDR
|
2016-10-05 10:03:08 +09:00
|
|
|
select SYS_FSL_DDR_BE
|
|
|
|
select SYS_FSL_DDR_VER_50
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008850
|
2017-09-04 19:46:50 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008997
|
2017-09-04 19:46:51 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009007
|
2017-09-04 19:46:48 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009008
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009660
|
|
|
|
select SYS_FSL_ERRATUM_A009663
|
2017-09-04 19:46:49 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009798
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009929
|
|
|
|
select SYS_FSL_ERRATUM_A009942
|
2016-09-27 00:09:27 +09:00
|
|
|
select SYS_FSL_ERRATUM_A010315
|
2016-09-29 13:42:44 +09:00
|
|
|
select SYS_FSL_ERRATUM_A010539
|
2016-12-29 01:43:40 +09:00
|
|
|
select SYS_FSL_HAS_DDR3
|
|
|
|
select SYS_FSL_HAS_DDR4
|
2017-01-24 05:31:19 +09:00
|
|
|
select ARCH_EARLY_INIT_R
|
2017-01-24 05:31:20 +09:00
|
|
|
select BOARD_EARLY_INIT_F
|
2017-06-15 12:28:21 +09:00
|
|
|
imply SCSI
|
2017-12-08 22:36:19 +09:00
|
|
|
imply SCSI_AHCI
|
2017-08-05 07:34:34 +09:00
|
|
|
imply CMD_PCI
|
2016-09-27 00:09:26 +09:00
|
|
|
|
2016-09-27 00:09:24 +09:00
|
|
|
config ARCH_LS1046A
|
2016-10-05 06:31:47 +09:00
|
|
|
bool
|
2017-01-06 18:41:11 +09:00
|
|
|
select ARMV8_SET_SMPEN
|
2016-10-05 06:31:48 +09:00
|
|
|
select FSL_LSCH2
|
2016-12-29 01:43:40 +09:00
|
|
|
select SYS_FSL_DDR
|
2016-10-05 10:03:08 +09:00
|
|
|
select SYS_FSL_DDR_BE
|
|
|
|
select SYS_FSL_DDR_VER_50
|
2017-01-28 02:57:31 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008336
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008511
|
2017-03-23 19:14:40 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008850
|
2017-09-04 19:46:50 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008997
|
2017-09-04 19:46:51 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009007
|
2017-09-04 19:46:48 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009008
|
2017-09-04 19:46:49 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009798
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009801
|
|
|
|
select SYS_FSL_ERRATUM_A009803
|
|
|
|
select SYS_FSL_ERRATUM_A009942
|
|
|
|
select SYS_FSL_ERRATUM_A010165
|
2016-09-29 13:42:44 +09:00
|
|
|
select SYS_FSL_ERRATUM_A010539
|
2016-12-29 01:43:40 +09:00
|
|
|
select SYS_FSL_HAS_DDR4
|
2016-10-05 10:01:34 +09:00
|
|
|
select SYS_FSL_SRDS_2
|
2017-01-24 05:31:19 +09:00
|
|
|
select ARCH_EARLY_INIT_R
|
2017-01-24 05:31:20 +09:00
|
|
|
select BOARD_EARLY_INIT_F
|
2017-06-15 12:28:21 +09:00
|
|
|
imply SCSI
|
2017-12-08 22:36:19 +09:00
|
|
|
imply SCSI_AHCI
|
2016-09-27 00:09:26 +09:00
|
|
|
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
config ARCH_LS1088A
|
|
|
|
bool
|
|
|
|
select ARMV8_SET_SMPEN
|
|
|
|
select FSL_LSCH3
|
|
|
|
select SYS_FSL_DDR
|
|
|
|
select SYS_FSL_DDR_LE
|
|
|
|
select SYS_FSL_DDR_VER_50
|
2017-08-31 20:07:31 +09:00
|
|
|
select SYS_FSL_EC1
|
|
|
|
select SYS_FSL_EC2
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009803
|
|
|
|
select SYS_FSL_ERRATUM_A009942
|
|
|
|
select SYS_FSL_ERRATUM_A010165
|
|
|
|
select SYS_FSL_ERRATUM_A008511
|
|
|
|
select SYS_FSL_ERRATUM_A008850
|
2017-09-22 16:21:34 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009007
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
select SYS_FSL_HAS_CCI400
|
|
|
|
select SYS_FSL_HAS_DDR4
|
2017-08-31 20:07:31 +09:00
|
|
|
select SYS_FSL_HAS_RGMII
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
select SYS_FSL_HAS_SEC
|
|
|
|
select SYS_FSL_SEC_COMPAT_5
|
|
|
|
select SYS_FSL_SEC_LE
|
|
|
|
select SYS_FSL_SRDS_1
|
|
|
|
select SYS_FSL_SRDS_2
|
|
|
|
select FSL_TZASC_1
|
|
|
|
select ARCH_EARLY_INIT_R
|
|
|
|
select BOARD_EARLY_INIT_F
|
2017-11-02 13:20:47 +09:00
|
|
|
imply SCSI
|
2017-12-04 12:37:00 +09:00
|
|
|
imply PANIC_HANG
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
|
2016-10-05 06:31:47 +09:00
|
|
|
config ARCH_LS2080A
|
|
|
|
bool
|
2017-01-06 18:41:11 +09:00
|
|
|
select ARMV8_SET_SMPEN
|
2017-03-07 21:13:42 +09:00
|
|
|
select ARM_ERRATA_826974
|
|
|
|
select ARM_ERRATA_828024
|
|
|
|
select ARM_ERRATA_829520
|
|
|
|
select ARM_ERRATA_833471
|
2016-10-05 06:31:48 +09:00
|
|
|
select FSL_LSCH3
|
2016-12-29 01:43:40 +09:00
|
|
|
select SYS_FSL_DDR
|
2016-10-05 10:03:08 +09:00
|
|
|
select SYS_FSL_DDR_LE
|
|
|
|
select SYS_FSL_DDR_VER_50
|
2017-08-18 14:24:36 +09:00
|
|
|
select SYS_FSL_HAS_CCN504
|
2016-10-05 10:01:34 +09:00
|
|
|
select SYS_FSL_HAS_DP_DDR
|
2016-12-29 01:43:30 +09:00
|
|
|
select SYS_FSL_HAS_SEC
|
2016-12-29 01:43:40 +09:00
|
|
|
select SYS_FSL_HAS_DDR4
|
2016-12-29 01:43:30 +09:00
|
|
|
select SYS_FSL_SEC_COMPAT_5
|
2016-12-29 01:43:31 +09:00
|
|
|
select SYS_FSL_SEC_LE
|
2016-10-05 10:01:34 +09:00
|
|
|
select SYS_FSL_SRDS_2
|
2017-04-07 15:10:32 +09:00
|
|
|
select FSL_TZASC_1
|
|
|
|
select FSL_TZASC_2
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008336
|
|
|
|
select SYS_FSL_ERRATUM_A008511
|
|
|
|
select SYS_FSL_ERRATUM_A008514
|
|
|
|
select SYS_FSL_ERRATUM_A008585
|
2017-09-04 19:46:50 +09:00
|
|
|
select SYS_FSL_ERRATUM_A008997
|
2017-09-04 19:46:51 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009007
|
2017-09-04 19:46:48 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009008
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009635
|
|
|
|
select SYS_FSL_ERRATUM_A009663
|
2017-09-04 19:46:49 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009798
|
2016-12-29 01:43:41 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009801
|
|
|
|
select SYS_FSL_ERRATUM_A009803
|
|
|
|
select SYS_FSL_ERRATUM_A009942
|
|
|
|
select SYS_FSL_ERRATUM_A010165
|
2017-02-23 19:33:57 +09:00
|
|
|
select SYS_FSL_ERRATUM_A009203
|
2017-01-24 05:31:19 +09:00
|
|
|
select ARCH_EARLY_INIT_R
|
2017-01-24 05:31:20 +09:00
|
|
|
select BOARD_EARLY_INIT_F
|
2017-12-04 12:37:00 +09:00
|
|
|
imply PANIC_HANG
|
2016-10-05 06:31:48 +09:00
|
|
|
|
|
|
|
config FSL_LSCH2
|
|
|
|
bool
|
2017-08-11 14:39:14 +09:00
|
|
|
select SYS_FSL_HAS_CCI400
|
2016-12-29 01:43:30 +09:00
|
|
|
select SYS_FSL_HAS_SEC
|
|
|
|
select SYS_FSL_SEC_COMPAT_5
|
2016-12-29 01:43:31 +09:00
|
|
|
select SYS_FSL_SEC_BE
|
2016-10-05 10:01:34 +09:00
|
|
|
select SYS_FSL_SRDS_1
|
|
|
|
select SYS_HAS_SERDES
|
2016-10-05 06:31:48 +09:00
|
|
|
|
|
|
|
config FSL_LSCH3
|
|
|
|
bool
|
2016-10-05 10:01:34 +09:00
|
|
|
select SYS_FSL_SRDS_1
|
|
|
|
select SYS_HAS_SERDES
|
2016-10-05 06:31:48 +09:00
|
|
|
|
2017-03-07 02:02:25 +09:00
|
|
|
config FSL_MC_ENET
|
|
|
|
bool "Management Complex network"
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
depends on ARCH_LS2080A || ARCH_LS1088A
|
2017-03-07 02:02:25 +09:00
|
|
|
default y
|
|
|
|
select RESV_RAM
|
|
|
|
help
|
|
|
|
Enable Management Complex (MC) network
|
|
|
|
|
2016-10-05 06:31:48 +09:00
|
|
|
menu "Layerscape architecture"
|
|
|
|
depends on FSL_LSCH2 || FSL_LSCH3
|
2016-10-05 06:31:47 +09:00
|
|
|
|
2016-12-13 15:54:24 +09:00
|
|
|
config FSL_PCIE_COMPAT
|
|
|
|
string "PCIe compatible of Kernel DT"
|
|
|
|
depends on PCIE_LAYERSCAPE
|
|
|
|
default "fsl,ls1012a-pcie" if ARCH_LS1012A
|
|
|
|
default "fsl,ls1043a-pcie" if ARCH_LS1043A
|
|
|
|
default "fsl,ls1046a-pcie" if ARCH_LS1046A
|
|
|
|
default "fsl,ls2080a-pcie" if ARCH_LS2080A
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
default "fsl,ls1088a-pcie" if ARCH_LS1088A
|
2016-12-13 15:54:24 +09:00
|
|
|
help
|
|
|
|
This compatible is used to find pci controller node in Kernel DT
|
|
|
|
to complete fixup.
|
|
|
|
|
2017-01-17 19:31:15 +09:00
|
|
|
config HAS_FEATURE_GIC64K_ALIGN
|
|
|
|
bool
|
|
|
|
default y if ARCH_LS1043A
|
|
|
|
|
2017-01-17 19:31:16 +09:00
|
|
|
config HAS_FEATURE_ENHANCED_MSI
|
|
|
|
bool
|
|
|
|
default y if ARCH_LS1043A
|
2017-01-17 19:31:15 +09:00
|
|
|
|
2016-12-08 12:58:21 +09:00
|
|
|
menu "Layerscape PPA"
|
|
|
|
config FSL_LS_PPA
|
|
|
|
bool "FSL Layerscape PPA firmware support"
|
2016-12-08 12:58:22 +09:00
|
|
|
depends on !ARMV8_PSCI
|
2017-01-16 18:31:49 +09:00
|
|
|
select ARMV8_SEC_FIRMWARE_SUPPORT
|
2017-01-16 18:31:48 +09:00
|
|
|
select SEC_FIRMWARE_ARMV8_PSCI
|
2017-01-16 18:31:49 +09:00
|
|
|
select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
|
2016-12-08 12:58:21 +09:00
|
|
|
help
|
|
|
|
The FSL Primary Protected Application (PPA) is a software component
|
|
|
|
which is loaded during boot stage, and then remains resident in RAM
|
|
|
|
and runs in the TrustZone after boot.
|
|
|
|
Say y to enable it.
|
2017-05-16 00:52:00 +09:00
|
|
|
|
|
|
|
config SPL_FSL_LS_PPA
|
|
|
|
bool "FSL Layerscape PPA firmware support for SPL build"
|
|
|
|
depends on !ARMV8_PSCI
|
|
|
|
select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
|
|
|
|
select SEC_FIRMWARE_ARMV8_PSCI
|
|
|
|
select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
|
|
|
|
help
|
|
|
|
The FSL Primary Protected Application (PPA) is a software component
|
|
|
|
which is loaded during boot stage, and then remains resident in RAM
|
|
|
|
and runs in the TrustZone after boot. This is to load PPA during SPL
|
|
|
|
stage instead of the RAM version of U-Boot. Once PPA is initialized,
|
|
|
|
the rest of U-Boot (including RAM version) runs at EL2.
|
2017-01-16 18:31:49 +09:00
|
|
|
choice
|
|
|
|
prompt "FSL Layerscape PPA firmware loading-media select"
|
|
|
|
depends on FSL_LS_PPA
|
2017-03-17 17:12:33 +09:00
|
|
|
default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
|
|
|
|
default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
|
2017-01-16 18:31:49 +09:00
|
|
|
default SYS_LS_PPA_FW_IN_XIP
|
|
|
|
|
|
|
|
config SYS_LS_PPA_FW_IN_XIP
|
|
|
|
bool "XIP"
|
|
|
|
help
|
|
|
|
Say Y here if the PPA firmware locate at XIP flash, such
|
|
|
|
as NOR or QSPI flash.
|
|
|
|
|
2017-03-17 17:12:33 +09:00
|
|
|
config SYS_LS_PPA_FW_IN_MMC
|
|
|
|
bool "eMMC or SD Card"
|
|
|
|
help
|
|
|
|
Say Y here if the PPA firmware locate at eMMC/SD card.
|
|
|
|
|
|
|
|
config SYS_LS_PPA_FW_IN_NAND
|
|
|
|
bool "NAND"
|
|
|
|
help
|
|
|
|
Say Y here if the PPA firmware locate at NAND flash.
|
|
|
|
|
2017-01-16 18:31:49 +09:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
config SYS_LS_PPA_FW_ADDR
|
|
|
|
hex "Address of PPA firmware loading from"
|
|
|
|
depends on FSL_LS_PPA
|
2017-04-28 14:11:35 +09:00
|
|
|
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
|
2017-05-16 11:45:58 +09:00
|
|
|
default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
|
2017-04-28 16:17:24 +09:00
|
|
|
default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
|
2017-08-31 19:42:54 +09:00
|
|
|
default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
|
2017-05-16 11:45:58 +09:00
|
|
|
default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
|
|
|
|
default 0x400000 if SYS_LS_PPA_FW_IN_MMC
|
|
|
|
default 0x400000 if SYS_LS_PPA_FW_IN_NAND
|
2017-03-17 17:12:33 +09:00
|
|
|
|
2017-01-16 18:31:49 +09:00
|
|
|
help
|
|
|
|
If the PPA firmware locate at XIP flash, such as NOR or
|
|
|
|
QSPI flash, this address is a directly memory-mapped.
|
|
|
|
If it is in a serial accessed flash, such as NAND and SD
|
|
|
|
card, it is a byte offset.
|
2017-03-23 17:18:14 +09:00
|
|
|
|
|
|
|
config SYS_LS_PPA_ESBC_ADDR
|
|
|
|
hex "hdr address of PPA firmware loading from"
|
|
|
|
depends on FSL_LS_PPA && CHAIN_OF_TRUST
|
2017-08-16 20:13:28 +09:00
|
|
|
default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
|
|
|
|
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
|
|
|
|
default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
|
2017-08-16 20:13:29 +09:00
|
|
|
default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
|
|
|
|
default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
|
2017-11-22 12:31:26 +09:00
|
|
|
default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
|
2017-08-16 20:13:28 +09:00
|
|
|
default 0x680000 if SYS_LS_PPA_FW_IN_MMC
|
|
|
|
default 0x680000 if SYS_LS_PPA_FW_IN_NAND
|
2017-03-23 17:18:14 +09:00
|
|
|
help
|
|
|
|
If the PPA header firmware locate at XIP flash, such as NOR or
|
|
|
|
QSPI flash, this address is a directly memory-mapped.
|
|
|
|
If it is in a serial accessed flash, such as NAND and SD
|
|
|
|
card, it is a byte offset.
|
|
|
|
|
2017-04-20 08:39:11 +09:00
|
|
|
config LS_PPA_ESBC_HDR_SIZE
|
|
|
|
hex "Length of PPA ESBC header"
|
|
|
|
depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
|
|
|
|
default 0x2000
|
|
|
|
help
|
|
|
|
Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
|
|
|
|
NAND to memory to validate PPA image.
|
|
|
|
|
2016-12-08 12:58:21 +09:00
|
|
|
endmenu
|
|
|
|
|
2017-09-04 19:46:50 +09:00
|
|
|
config SYS_FSL_ERRATUM_A008997
|
|
|
|
bool "Workaround for USB PHY erratum A008997"
|
|
|
|
|
2017-09-04 19:46:51 +09:00
|
|
|
config SYS_FSL_ERRATUM_A009007
|
|
|
|
bool
|
|
|
|
help
|
|
|
|
Workaround for USB PHY erratum A009007
|
|
|
|
|
2017-09-04 19:46:48 +09:00
|
|
|
config SYS_FSL_ERRATUM_A009008
|
|
|
|
bool "Workaround for USB PHY erratum A009008"
|
|
|
|
|
2017-09-04 19:46:49 +09:00
|
|
|
config SYS_FSL_ERRATUM_A009798
|
|
|
|
bool "Workaround for USB PHY erratum A009798"
|
|
|
|
|
2016-09-27 00:09:27 +09:00
|
|
|
config SYS_FSL_ERRATUM_A010315
|
|
|
|
bool "Workaround for PCIe erratum A010315"
|
2016-09-29 13:42:44 +09:00
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_A010539
|
|
|
|
bool "Workaround for PIN MUX erratum A010539"
|
2016-10-05 06:31:48 +09:00
|
|
|
|
2016-10-05 06:45:01 +09:00
|
|
|
config MAX_CPUS
|
|
|
|
int "Maximum number of CPUs permitted for Layerscape"
|
|
|
|
default 4 if ARCH_LS1043A
|
|
|
|
default 4 if ARCH_LS1046A
|
|
|
|
default 16 if ARCH_LS2080A
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
default 8 if ARCH_LS1088A
|
2016-10-05 06:45:01 +09:00
|
|
|
default 1
|
|
|
|
help
|
|
|
|
Set this number to the maximum number of possible CPUs in the SoC.
|
|
|
|
SoCs may have multiple clusters with each cluster may have multiple
|
|
|
|
ports. If some ports are reserved but higher ports are used for
|
|
|
|
cores, count the reserved ports. This will allocate enough memory
|
|
|
|
in spin table to properly handle all cores.
|
|
|
|
|
2016-12-03 02:32:35 +09:00
|
|
|
config SECURE_BOOT
|
2017-01-05 03:32:08 +09:00
|
|
|
bool "Secure Boot"
|
2016-12-03 02:32:35 +09:00
|
|
|
help
|
|
|
|
Enable Freescale Secure Boot feature
|
|
|
|
|
2016-12-01 11:13:52 +09:00
|
|
|
config QSPI_AHB_INIT
|
|
|
|
bool "Init the QSPI AHB bus"
|
|
|
|
help
|
|
|
|
The default setting for QSPI AHB bus just support 3bytes addressing.
|
|
|
|
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
|
|
|
|
bus for those flashes to support the full QSPI flash size.
|
|
|
|
|
2017-08-11 14:39:14 +09:00
|
|
|
config SYS_CCI400_OFFSET
|
|
|
|
hex "Offset for CCI400 base"
|
|
|
|
depends on SYS_FSL_HAS_CCI400
|
|
|
|
default 0x3090000 if ARCH_LS1088A
|
|
|
|
default 0x180000 if FSL_LSCH2
|
|
|
|
help
|
|
|
|
Offset for CCI400 base
|
|
|
|
CCI400 base addr = CCSRBAR + CCI400_OFFSET
|
|
|
|
|
2016-10-05 06:45:54 +09:00
|
|
|
config SYS_FSL_IFC_BANK_COUNT
|
|
|
|
int "Maximum banks of Integrated flash controller"
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
|
2016-10-05 06:45:54 +09:00
|
|
|
default 4 if ARCH_LS1043A
|
|
|
|
default 4 if ARCH_LS1046A
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
default 8 if ARCH_LS2080A || ARCH_LS1088A
|
2016-10-05 06:45:54 +09:00
|
|
|
|
2017-08-11 14:39:14 +09:00
|
|
|
config SYS_FSL_HAS_CCI400
|
|
|
|
bool
|
|
|
|
|
2017-08-18 14:24:36 +09:00
|
|
|
config SYS_FSL_HAS_CCN504
|
|
|
|
bool
|
|
|
|
|
2016-10-05 06:46:50 +09:00
|
|
|
config SYS_FSL_HAS_DP_DDR
|
|
|
|
bool
|
|
|
|
|
2016-10-05 10:01:34 +09:00
|
|
|
config SYS_FSL_SRDS_1
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_SRDS_2
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_HAS_SERDES
|
|
|
|
bool
|
|
|
|
|
2017-04-07 15:10:32 +09:00
|
|
|
config FSL_TZASC_1
|
|
|
|
bool
|
|
|
|
|
|
|
|
config FSL_TZASC_2
|
|
|
|
bool
|
|
|
|
|
2016-10-05 06:31:48 +09:00
|
|
|
endmenu
|
2016-12-29 01:43:41 +09:00
|
|
|
|
2017-01-10 17:44:15 +09:00
|
|
|
menu "Layerscape clock tree configuration"
|
|
|
|
depends on FSL_LSCH2 || FSL_LSCH3
|
|
|
|
|
|
|
|
config SYS_FSL_CLK
|
|
|
|
bool "Enable clock tree initialization"
|
|
|
|
default y
|
|
|
|
|
|
|
|
config CLUSTER_CLK_FREQ
|
|
|
|
int "Reference clock of core cluster"
|
|
|
|
depends on ARCH_LS1012A
|
|
|
|
default 100000000
|
|
|
|
help
|
|
|
|
This number is the reference clock frequency of core PLL.
|
|
|
|
For most platforms, the core PLL and Platform PLL have the same
|
|
|
|
reference clock, but for some platforms, LS1012A for instance,
|
|
|
|
they are provided sepatately.
|
|
|
|
|
|
|
|
config SYS_FSL_PCLK_DIV
|
|
|
|
int "Platform clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 1 if ARCH_LS1046A
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 19:42:53 +09:00
|
|
|
default 1 if ARCH_LS1088A
|
2017-01-10 17:44:15 +09:00
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive Platform clock from
|
|
|
|
Platform PLL, in another word:
|
|
|
|
Platform_clk = Platform_PLL_freq / this_divider
|
|
|
|
|
|
|
|
config SYS_FSL_DSPI_CLK_DIV
|
|
|
|
int "DSPI clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive DSPI clock from Platform
|
2017-07-03 19:37:11 +09:00
|
|
|
clock, in another word DSPI_clk = Platform_clk / this_divider.
|
2017-01-10 17:44:15 +09:00
|
|
|
|
|
|
|
config SYS_FSL_DUART_CLK_DIV
|
|
|
|
int "DUART clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive DUART clock from Platform
|
|
|
|
clock, in another word DUART_clk = Platform_clk / this_divider.
|
|
|
|
|
|
|
|
config SYS_FSL_I2C_CLK_DIV
|
|
|
|
int "I2C clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive I2C clock from Platform
|
|
|
|
clock, in another word I2C_clk = Platform_clk / this_divider.
|
|
|
|
|
|
|
|
config SYS_FSL_IFC_CLK_DIV
|
|
|
|
int "IFC clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive IFC clock from Platform
|
|
|
|
clock, in another word IFC_clk = Platform_clk / this_divider.
|
|
|
|
|
|
|
|
config SYS_FSL_LPUART_CLK_DIV
|
|
|
|
int "LPUART clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive LPUART clock from Platform
|
|
|
|
clock, in another word LPUART_clk = Platform_clk / this_divider.
|
|
|
|
|
|
|
|
config SYS_FSL_SDHC_CLK_DIV
|
|
|
|
int "SDHC clock divider"
|
|
|
|
default 1 if ARCH_LS1043A
|
|
|
|
default 1 if ARCH_LS1012A
|
|
|
|
default 2
|
|
|
|
help
|
|
|
|
This is the divider that is used to derive SDHC clock from Platform
|
|
|
|
clock, in another word SDHC_clk = Platform_clk / this_divider.
|
|
|
|
endmenu
|
|
|
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2017-03-07 02:02:24 +09:00
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config RESV_RAM
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bool
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help
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Reserve memory from the top, tracked by gd->arch.resv_ram. This
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reserved RAM can be used by special driver that resides in memory
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after U-Boot exits. It's up to implementation to allocate and allow
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access to this reserved memory. For example, the reserved RAM can
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be at the high end of physical memory. The reserve RAM may be
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excluded from memory bank(s) passed to OS, or marked as reserved.
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2017-08-31 20:07:31 +09:00
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config SYS_FSL_EC1
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bool
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help
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Ethernet controller 1, this is connected to MAC3.
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Provides DPAA2 capabilities
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config SYS_FSL_EC2
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bool
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help
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Ethernet controller 2, this is connected to MAC4.
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Provides DPAA2 capabilities
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2016-12-29 01:43:41 +09:00
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config SYS_FSL_ERRATUM_A008336
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bool
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config SYS_FSL_ERRATUM_A008514
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bool
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config SYS_FSL_ERRATUM_A008585
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bool
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config SYS_FSL_ERRATUM_A008850
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bool
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2017-02-23 19:33:57 +09:00
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config SYS_FSL_ERRATUM_A009203
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bool
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2016-12-29 01:43:41 +09:00
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config SYS_FSL_ERRATUM_A009635
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bool
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config SYS_FSL_ERRATUM_A009660
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bool
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config SYS_FSL_ERRATUM_A009929
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bool
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2017-03-07 02:02:26 +09:00
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2017-08-31 20:07:31 +09:00
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config SYS_FSL_HAS_RGMII
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bool
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depends on SYS_FSL_EC1 || SYS_FSL_EC2
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2017-03-07 02:02:26 +09:00
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config SYS_MC_RSV_MEM_ALIGN
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hex "Management Complex reserved memory alignment"
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depends on RESV_RAM
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2017-12-08 14:40:40 +09:00
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default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
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2017-03-07 02:02:26 +09:00
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help
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Reserved memory needs to be aligned for MC to use. Default value
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is 512MB.
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2017-08-04 06:23:55 +09:00
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config SPL_LDSCRIPT
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default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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2017-10-23 11:09:21 +09:00
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config HAS_FSL_XHCI_USB
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bool
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default y if ARCH_LS1043A || ARCH_LS1046A
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help
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For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
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pins, select it when the pins are assigned to USB.
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