2016-09-27 00:09:26 +09:00
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config ARCH_LS1012A
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2016-10-05 06:31:47 +09:00
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bool
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2017-01-06 18:41:11 +09:00
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select ARMV8_SET_SMPEN
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2016-10-05 06:31:48 +09:00
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select FSL_LSCH2
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2016-10-05 10:03:08 +09:00
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select SYS_FSL_DDR_BE
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2016-09-27 00:09:26 +09:00
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select SYS_FSL_MMDC
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2016-09-27 00:09:27 +09:00
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select SYS_FSL_ERRATUM_A010315
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config ARCH_LS1043A
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2016-10-05 06:31:47 +09:00
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bool
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2017-01-06 18:41:11 +09:00
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select ARMV8_SET_SMPEN
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2016-10-05 06:31:48 +09:00
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select FSL_LSCH2
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2016-12-29 01:43:40 +09:00
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select SYS_FSL_DDR
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2016-10-05 10:03:08 +09:00
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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2016-12-29 01:43:41 +09:00
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select SYS_FSL_ERRATUM_A008850
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select SYS_FSL_ERRATUM_A009660
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009929
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select SYS_FSL_ERRATUM_A009942
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2016-09-27 00:09:27 +09:00
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select SYS_FSL_ERRATUM_A010315
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2016-09-29 13:42:44 +09:00
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select SYS_FSL_ERRATUM_A010539
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2016-12-29 01:43:40 +09:00
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_DDR4
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2016-09-27 00:09:26 +09:00
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2016-09-27 00:09:24 +09:00
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config ARCH_LS1046A
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2016-10-05 06:31:47 +09:00
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bool
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2017-01-06 18:41:11 +09:00
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select ARMV8_SET_SMPEN
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2016-10-05 06:31:48 +09:00
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select FSL_LSCH2
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2016-12-29 01:43:40 +09:00
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select SYS_FSL_DDR
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2016-10-05 10:03:08 +09:00
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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2016-12-29 01:43:41 +09:00
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select SYS_FSL_ERRATUM_A008511
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select SYS_FSL_ERRATUM_A009801
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select SYS_FSL_ERRATUM_A009803
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010165
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2016-09-29 13:42:44 +09:00
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select SYS_FSL_ERRATUM_A010539
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2016-12-29 01:43:40 +09:00
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select SYS_FSL_HAS_DDR4
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2016-10-05 10:01:34 +09:00
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select SYS_FSL_SRDS_2
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2016-09-27 00:09:26 +09:00
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2016-10-05 06:31:47 +09:00
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config ARCH_LS2080A
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bool
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2017-01-06 18:41:11 +09:00
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select ARMV8_SET_SMPEN
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2016-10-05 06:31:48 +09:00
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select FSL_LSCH3
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2016-12-29 01:43:40 +09:00
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select SYS_FSL_DDR
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2016-10-05 10:03:08 +09:00
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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2016-10-05 10:01:34 +09:00
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select SYS_FSL_HAS_DP_DDR
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2016-12-29 01:43:30 +09:00
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select SYS_FSL_HAS_SEC
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2016-12-29 01:43:40 +09:00
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select SYS_FSL_HAS_DDR4
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2016-12-29 01:43:30 +09:00
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select SYS_FSL_SEC_COMPAT_5
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2016-12-29 01:43:31 +09:00
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select SYS_FSL_SEC_LE
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2016-10-05 10:01:34 +09:00
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select SYS_FSL_SRDS_2
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2016-12-29 01:43:41 +09:00
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select SYS_FSL_ERRATUM_A008336
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select SYS_FSL_ERRATUM_A008511
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select SYS_FSL_ERRATUM_A008514
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select SYS_FSL_ERRATUM_A008585
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select SYS_FSL_ERRATUM_A009635
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009801
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select SYS_FSL_ERRATUM_A009803
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010165
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2016-10-05 06:31:48 +09:00
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config FSL_LSCH2
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bool
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2016-12-29 01:43:30 +09:00
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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2016-12-29 01:43:31 +09:00
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select SYS_FSL_SEC_BE
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2016-10-05 10:01:34 +09:00
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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2016-10-05 06:31:48 +09:00
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config FSL_LSCH3
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bool
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2016-10-05 10:01:34 +09:00
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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2016-10-05 06:31:48 +09:00
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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2016-10-05 06:31:47 +09:00
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2016-12-13 15:54:24 +09:00
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config FSL_PCIE_COMPAT
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string "PCIe compatible of Kernel DT"
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depends on PCIE_LAYERSCAPE
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default "fsl,ls1012a-pcie" if ARCH_LS1012A
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default "fsl,ls1043a-pcie" if ARCH_LS1043A
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default "fsl,ls1046a-pcie" if ARCH_LS1046A
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default "fsl,ls2080a-pcie" if ARCH_LS2080A
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help
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This compatible is used to find pci controller node in Kernel DT
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to complete fixup.
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2016-12-08 12:58:21 +09:00
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menu "Layerscape PPA"
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config FSL_LS_PPA
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bool "FSL Layerscape PPA firmware support"
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2016-12-08 12:58:22 +09:00
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depends on !ARMV8_PSCI
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2016-12-08 12:58:21 +09:00
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depends on ARCH_LS1043A || ARCH_LS1046A
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select FSL_PPA_ARMV8_PSCI
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help
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The FSL Primary Protected Application (PPA) is a software component
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which is loaded during boot stage, and then remains resident in RAM
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and runs in the TrustZone after boot.
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Say y to enable it.
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config FSL_PPA_ARMV8_PSCI
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bool "PSCI implementation in PPA firmware"
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depends on FSL_LS_PPA
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help
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This config enables the ARMv8 PSCI implementation in PPA firmware.
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This is a private PSCI implementation and different from those
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implemented under the common ARMv8 PSCI framework.
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endmenu
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2016-09-27 00:09:27 +09:00
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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2016-09-29 13:42:44 +09:00
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config SYS_FSL_ERRATUM_A010539
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bool "Workaround for PIN MUX erratum A010539"
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2016-10-05 06:31:48 +09:00
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2016-10-05 06:45:01 +09:00
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config MAX_CPUS
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int "Maximum number of CPUs permitted for Layerscape"
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 16 if ARCH_LS2080A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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2016-12-03 02:32:35 +09:00
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config SECURE_BOOT
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bool
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help
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Enable Freescale Secure Boot feature
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2016-12-01 11:13:52 +09:00
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config QSPI_AHB_INIT
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bool "Init the QSPI AHB bus"
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help
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The default setting for QSPI AHB bus just support 3bytes addressing.
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But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
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bus for those flashes to support the full QSPI flash size.
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2016-10-05 06:45:54 +09:00
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 8 if ARCH_LS2080A
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2016-10-05 06:46:50 +09:00
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config SYS_FSL_HAS_DP_DDR
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bool
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2016-10-05 10:01:34 +09:00
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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2016-10-05 06:31:48 +09:00
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endmenu
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2016-12-29 01:43:41 +09:00
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config SYS_FSL_ERRATUM_A008336
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bool
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config SYS_FSL_ERRATUM_A008514
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bool
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config SYS_FSL_ERRATUM_A008585
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bool
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config SYS_FSL_ERRATUM_A008850
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bool
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config SYS_FSL_ERRATUM_A009635
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bool
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config SYS_FSL_ERRATUM_A009660
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bool
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config SYS_FSL_ERRATUM_A009929
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bool
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