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armv8: QSPI: Add AHB bus 16MB+ size support

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The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Yuan Yao 2016-12-01 10:13:52 +08:00 committed by York Sun
parent 8545c5415f
commit dd2ad2f131
8 changed files with 55 additions and 0 deletions
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7
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
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@ -76,6 +76,13 @@ config SECURE_BOOT
help
Enable Freescale Secure Boot feature
config QSPI_AHB_INIT
bool "Init the QSPI AHB bus"
help
The default setting for QSPI AHB bus just support 3bytes addressing.
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

42
arch/arm/cpu/armv8/fsl-layerscape/soc.c
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@ -373,6 +373,45 @@ void fsl_lsch2_early_init_f(void)
}
#endif
#ifdef CONFIG_QSPI_AHB_INIT
/* Enable 4bytes address support and fast read */
int qspi_ahb_init(void)
{
u32 *qspi_lut, lut_key, *qspi_key;
qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
lut_key = in_be32(qspi_key);
if (lut_key == 0x5af05af0) {
/* That means the register is BE */
out_be32(qspi_key, 0x5af05af0);
/* Unlock the lut table */
out_be32(qspi_key + 1, 0x00000002);
out_be32(qspi_lut, 0x0820040c);
out_be32(qspi_lut + 1, 0x1c080c08);
out_be32(qspi_lut + 2, 0x00002400);
/* Lock the lut table */
out_be32(qspi_key, 0x5af05af0);
out_be32(qspi_key + 1, 0x00000001);
} else {
/* That means the register is LE */
out_le32(qspi_key, 0x5af05af0);
/* Unlock the lut table */
out_le32(qspi_key + 1, 0x00000002);
out_le32(qspi_lut, 0x0820040c);
out_le32(qspi_lut + 1, 0x1c080c08);
out_le32(qspi_lut + 2, 0x00002400);
/* Lock the lut table */
out_le32(qspi_key, 0x5af05af0);
out_le32(qspi_key + 1, 0x00000001);
}
return 0;
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@ -382,6 +421,9 @@ int board_late_init(void)
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
#endif
return 0;
}

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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@ -18,6 +18,7 @@
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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@ -19,6 +19,7 @@
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)

1
configs/ls1012afrdm_qspi_defconfig
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@ -34,3 +34,4 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_QSPI_AHB_INIT=y

1
configs/ls1012aqds_qspi_defconfig
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@ -38,3 +38,4 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_QSPI_AHB_INIT=y

1
configs/ls1012ardb_qspi_defconfig
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@ -38,3 +38,4 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_QSPI_AHB_INIT=y

1
configs/ls1046ardb_qspi_defconfig
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@ -24,3 +24,4 @@ CONFIG_SPI_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_QSPI_AHB_INIT=y