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arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to Kconfig

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Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
York Sun 2016-10-04 14:46:50 -07:00
parent 25af7dc193
commit fd6381029d
2 changed files with 8 additions and 3 deletions
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8
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -50,6 +50,11 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config NUM_DDR_CONTROLLERS
int "Maximum DDR controllers"
default 3 if ARCH_LS2080A
default 1
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@ -57,4 +62,7 @@ config SYS_FSL_IFC_BANK_COUNT
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
config SYS_FSL_HAS_DP_DDR
bool
endmenu

3
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -30,8 +30,6 @@
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
@ -150,7 +148,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */