Introduce initial hierarchy of device trees for Apalis iMX8X
System on Module.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
The used PMIC has been changed from RHOM BD71837 to NXP PCA9450A.
Adjust the device tree accordingly.
Remove the old ADC node as the ADC has been changed and has no longer
a separate power rail.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Reduce vital product data size to match the latest specification.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Removed aristainetos2, 2b, 2b-csl. This boards have been
recalled and destroyed.
Adapt board code to remove stuff not needed anymore.
Fix checkpatch warning, remove fdt_high and initrd_high
from default environment.
Signed-off-by: Heiko Schocher <hs@denx.de>
zu remove
Align the pin setup for sdhci0 with linux kernel.
This means to have slew rate enable and high drive strength.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Use the reset function to handle the hold boot bit in RCC
with device tree handle with MCU_HOLD_BOOT identifier.
This generic reset allows to remove the two specific properties:
- st,syscfg-holdboot
- st,syscfg-tz
This patch prepares alignment with kernel device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The QSPI CS2 is not used on DHCOM, remove the pinmux and flash@1.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
The uSD slot card-detect GPIO is connected to PG1, fix it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Add DT for DH PicoITX unit, which is a bare-bones carrier board for
the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom
board-to-board expansion connector.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Commit 4b2be78ab6 ("time: Fix get_ticks being non-monotonic")
puts in evidence that get_ticks is called before timer initialization.
Fix it by initializing timer before relocation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Device tree alignment with kernel v5.10-rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Since kernel v4.8-rc1, commit 05b23ebc2bd9 ("ARM: dts: armv7-m: remove skeleton.dtsi include"),
skeleton.dtsi file is no more included.
This synchronization is needed to avoid to get 2 memory node
in DTB file if, in DTS file, memory node is declared with the correct
syntax as following:
memory@90000000 {
device_type = "memory";
reg = <0x90000000 0x800000>;
};
Then in DTB, we will have the 2 memory nodes, which is incorrect and
cause misbehavior during DT parsing by U-boot:
memory {
device_type = "memory";
reg = <0x00 0x00>;
};
memory@90000000 {
device_type = "memory";
reg = <0x90000000 0x800000>;
};
Issue found when synchronizing MCU's STM32 DT from kernel v5.10-rc1.
When using fdtdec_setup_mem_size_base() or fdtdec_setup_memory_banksize()
API, first above memory node is found (with reg = <0x00 0x00>), so
gd->ram_size, gd->ram_base, gd->bd->bi_dram[bank].start and
gd->bd->bi_dram[bank].size are all set to 0 which avoid boards to boot.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit imports device tree files that are related to Allwinner V3
series from Linux commit 3650b228f83a ("Linux 5.10-rc1").
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Import updated device trees from Linux tag v5.9. This picks up new
hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI
files for the Pinebook and the Teres-I, since the ANX6345 bridge is
now supported upstream.
A couple of headers needed updates for recently-added hardware support.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Commit c4cea2bbf9 ("rockchip: Enable building a SPI ROM image on bob")
added an alias spi1 referring to spi@ff1d0000, however there was already
an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and
having both aliases present broke booting from SPI flash for this board.
Remove the spi0 alias, set the default bus for SPI flash to 1, and
enable support for numbered aliases in SPL so that it uses the same bus
numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash
on the rockpro64 board.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bbf9 ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific
MMC controller compatible.
This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi
to use this for SM1 based boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
- Add a new SMBIOS parser and enable it when booting from coreboot
- Fix up various driver names to avoid dtoc warnings
- Fully enable ACPI support on Google Chromebook Coral
- Add a way to set SMBIOS properties using the devicetree
- Update existing boards to use devicetree for SMBIOS using a new
default sysinfo driver
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---------------------
- new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM
- converted doc to reST
- fixes for verdin-imx8mm (Toradex)
- fixes for i.MX thermal driver
- mx7ulp: Align the PLL_USB frequency
- mx53: primary/secondary bmode
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
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Merge tag 'u-boot-imx-20201105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx for 2021.1
---------------------
- new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM
- converted doc to reST
- fixes for verdin-imx8mm (Toradex)
- fixes for i.MX thermal driver
- mx7ulp: Align the PLL_USB frequency
- mx53: primary/secondary bmode
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
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Merge tag 'u-boot-atmel-fixes-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel fixes for 2021.01 cycle:
This specific feature set includes the patches for DT required to fix
the warnings for newer DTC version (1.6.0+), i2c and spi bus unit
address.
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32"
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
GE B1x5v2 patient monitor series is similar to the CARESCAPE Monitor
series (GE Bx50). It consists of a carrier PCB used in combination
with a Congatec QMX6 SoM. This adds U-Boot support using device model
everywhere and SPL for memory initialization.
Proper configuration is provided as 'ge_b1x5v2_defconfig' and the
combined image u-boot-with-spi.imx can be flashed directly to 1024
byte offset to /dev/mtdblock0. Alternatively SPL and u-boot.imx can
be loaded separately via USB-OTG using e.g. imx_usb.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
PX30.Core needs to mount on top of this Carrier board for creating
complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose
carrier board with capacitive touch interface.
Genaral features:
- TFT 10.1" industrial, 1280x800 LVDS display
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
SOM's like PX30.Core needs to mount on top of this Carrier board
for creating complete PX30.Core C.TOUCH 2.0 board.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
General features:
- Rockchip PX30
- Up to 2GB DDR4
- eMMC 4 GB expandible
- rest of PX30 features
PX30.Core needs to mount on top of Engicam baseboards for creating
complete platform boards.
Possible baseboards are,
- EDIMM2.2
- C.TOUCH 2.0
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
SOM's like PX30.Core needs to mount on top of this Evaluation board
for creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board.
This will help to get serial out messages.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.
Cc: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
(Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
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Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.01-v2
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
Align node properties to kernel dts node.
The change of compatible property does not affect any currently
supported board.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Align node properties to kernel dts node.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.
With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt.
Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write
commands are failing. Increase frequency to 200Mhz to fix this issue.
Add bus-width = <8>, non-removable and disable-wp properties to the node
as this is eMMC.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Adding Z-turn board V5 to resolve the change between:
"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031
At this time the S25FL128SAGNFI003 doesn't work because of bug:
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
zynq-zturn was checked on V5 board, same error.
Maybe Z-turn board have the same problem (board with W25Q128BVFIG).
Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add basic support for the Kontron SMARC-sAL28 board. This includes just
the bare minimum to be able to bring up the board and boot linux.
For now, the Single and Dual PHY variant is supported. Other variants
will fall back to the basic variant.
In particular, there is no watchdog support for now. This means that you
have to disable the default watchdog, otherwise you'll end up in the
recovery bootloader. See the board README for details.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.
This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.
The Kconfig description is also updated accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
As the ownership is now Hitachi Power Grids, change the license string
and adapt the compatible string in DTS files. For kmeter1.dts we
change it to "keymile,KMETER1" for now, as this is then compliant with
what is submitted to the linux kernel. All other boards don't have
a upstreamed version in linux mainline.
Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a
System Control Processor, or SCP. ARM Trusted Firmware (ATF)
communicates with the SCP over SCPI to implement the PSCI system
suspend, shutdown and reset functionality. Currently, SCP firmware is
optional; the system will boot and run without it, but system suspend
will be unavailable.
Since all communication with the SCP is mediated by ATF, the only thing
U-Boot needs to do is load the firmware into SRAM. The SCP firmware
occupies the last 16KiB of SRAM A2, immediately following ATF.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since commit d879616e9e ("spl: fit: simplify logic for FDT loading for
non-OS boots"), the SPL looks at the "os" properties of FIT images to
determine where to append the FDT.
The "os" property of the "firmware" image also determines how to execute
the next stage of the boot process, as in 1d3790905d ("spl: atf:
introduce spl_invoke_atf and make bl31_entry private"). For this reason,
the next stage must be specified in "firmware", not in "loadables".
To support this additional functionality, and to properly model the boot
process, where ATF runs before U-Boot, add the "os" properties and swap
the firmware/loadable images in the FIT image.
Since this description was copied as an example in commit 70248d6a2916
("binman: Support generating FITs with multiple dtbs"), update those
examples as well for correctness and consistency.
Acked-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This consolidates the SoC-specific part at the top of the file to avoid
cluttering it up with preprocessor conditions.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use
binman"), if the BL31 environment variable was not defined, the firmware
would be loaded from a file "bl31.bin" in the current directory. Restore
that behavior by providing that as the default filename in case no entry
arg is provided, which will be the case if the environment variable is
unset.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Nodes should have a blank line separating them from sibling nodes and
properties. Add the necessary lines.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
- fsl_esdhc_imx cleanup
- not send cm13 if send_status is 0.
- Add reinit API
- Add mmc HS400 for fsl_esdhc
- Several cleanup for fsl_esdhc
- Add ADMA2 for sdhci
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.
The dts itself is imported from Linux.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Fix the actual board vendor and ease synching dts files from Linux.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Add initial U-Boot support for the iEi Puzzle-M801 board based on the
Marvell Armada 88F8040 SoC.
Currently supported hardware:
1x USB 3.0
4x Gigabit Ethernet
2x SFP+ (with NXP PCA9555 and NXP PCA9544)
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x EPSON RX8010 RTC
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Add properties related to eMMC HS400 mode.
mmc-hs400-1_8v;
bus-width = <8>;
They had been already in kernel dts file since the first
lx2160ardb dts patch.
b068890 arm64: dts: add LX2160ARDB board support
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver
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Merge tag 'u-boot-amlogic-20201005' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver
This imports the G12A & SM1 SoC and boards DT changes from the Linux
commit 9123e3a74ec7 ("Linux 5.9-rc1").
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the correcly architectured USB Glue node for Meson AXG and the
S400 board in -u-boot.dtsi until support in upstream Linux then
backported.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux
commit b3a9e3b9622a ("Linux 5.8-rc1").
This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for 2021.01 cycle:
This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
DT alignment with Linux kernel v5.9-rc4 for the STM32MP15x soc
device tree files and the STMicroelectronics boards device tree files.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The u-boot,dm-spl DT props are missing on AV96, hence the pinmux and
flash0 nodes are not included in the reduced SPL DT. This prevents
SPI NOR boot from working at all. Fix this by filling them in.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>