mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
- Assorted R-Car Gen3 updates
This commit is contained in:
Tom Rini
commit
adc0c39633
1960
arch/arm/dts/r8a774c0.dtsi
Normal file
1960
arch/arm/dts/r8a774c0.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
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@ -3,7 +3,19 @@ if RCAR_GEN3
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menu "Select Target SoC"
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config R8A774A1
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bool "Renesas SoC R8A774A1"
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bool "Renesas SoC R8A774A1"
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config R8A774B1
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bool "Renesas SoC R8A774B1"
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imply CLK_R8A774B1
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config R8A774C0
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bool "Renesas SoC R8A774C0"
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imply CLK_R8A774C0
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config R8A774E1
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bool "Renesas SoC R8A774E1"
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imply CLK_R8A774E1
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config R8A7795
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bool "Renesas SoC R8A7795"
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@ -55,6 +55,24 @@ config CLK_R8A774A1
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help
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Enable this to support the clocks on Renesas R8A774A1 SoC.
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config CLK_R8A774B1
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bool "Renesas R8A774B1 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A774B1 SoC.
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config CLK_R8A774C0
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bool "Renesas R8A774C0 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A774C0 SoC.
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config CLK_R8A774E1
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bool "Renesas R8A774E1 clock driver"
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depends on CLK_RCAR_GEN3
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help
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Enable this to support the clocks on Renesas R8A774E1 SoC.
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config CLK_R8A7795
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bool "Renesas R8A7795 clock driver"
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depends on CLK_RCAR_GEN3
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@ -1,6 +1,9 @@
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obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
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obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
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obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
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@ -41,6 +41,7 @@ enum clk_ids {
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RPCSRC,
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CLK_RINT,
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/* Module Clocks */
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@ -67,6 +68,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -97,6 +99,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
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DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
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DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
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DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
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DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC, 0x238),
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DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
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@ -200,6 +203,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
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DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
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DEF_MOD("rpc", 917, R8A774A1_CLK_RPC),
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DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
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DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
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DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
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336
drivers/clk/renesas/r8a774b1-cpg-mssr.c
Normal file
336
drivers/clk/renesas/r8a774b1-cpg-mssr.c
Normal file
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@ -0,0 +1,336 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*
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* Based on r8a7796-cpg-mssr.c
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL4,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a774b1_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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/* Core Clock Outputs */
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DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
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DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
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DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
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DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1),
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DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1),
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DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1),
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DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1),
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DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
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DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
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DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
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DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
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DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
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DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
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DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
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DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8),
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DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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};
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static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
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DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
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DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
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DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
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DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
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DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
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DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
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DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
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DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
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DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
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DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
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DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4),
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DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO),
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DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1),
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DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1),
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DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3),
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DEF_MOD("cmt3", 300, R8A774B1_CLK_R),
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DEF_MOD("cmt2", 301, R8A774B1_CLK_R),
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DEF_MOD("cmt1", 302, R8A774B1_CLK_R),
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DEF_MOD("cmt0", 303, R8A774B1_CLK_R),
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DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4),
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DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4),
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DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3),
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DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2),
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DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1),
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DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0),
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DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1),
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DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1),
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DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1),
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DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1),
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DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1),
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DEF_MOD("rwdt", 402, R8A774B1_CLK_R),
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DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3),
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DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2),
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DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2),
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DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1),
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DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1),
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DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1),
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DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1),
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DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1),
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DEF_MOD("thermal", 522, R8A774B1_CLK_CP),
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DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12),
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DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2),
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DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2),
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DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1),
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DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1),
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DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1),
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DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2),
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DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
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DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2),
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DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1),
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DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1),
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DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2),
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DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2),
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DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2),
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DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0),
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DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0),
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DEF_MOD("du3", 721, R8A774B1_CLK_S2D1),
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DEF_MOD("du1", 723, R8A774B1_CLK_S2D1),
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DEF_MOD("du0", 724, R8A774B1_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1),
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DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI),
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DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2),
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DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2),
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DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2),
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DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2),
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DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2),
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DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2),
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DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2),
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DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2),
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DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6),
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DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2),
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DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4),
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DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4),
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DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
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DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
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DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
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DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
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DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
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DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
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||||
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-----------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
/* RMSTPCR[0-11] is not present on RZ/G2N */
|
||||
static const struct mstp_stop_table r8a774b1_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x0, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0x0, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x0, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0x0, 0 },
|
||||
{ 0x80000184, 0x180, 0x0, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0x0, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0x0, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0x0, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x0, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0x0, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0x0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x0, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a774b1_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = {
|
||||
.core_clk = r8a774b1_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a774b1_core_clks),
|
||||
.mod_clk = r8a774b1_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a774b1_mod_clks),
|
||||
.mstp_table = r8a774b1_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table),
|
||||
.reset_node = "renesas,r8a774b1-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a774b1_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774b1_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774b1-cpg-mssr",
|
||||
.data = (ulong)&r8a774b1_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774b1) = {
|
||||
.name = "clk_r8a774b1",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774b1_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
308
drivers/clk/renesas/r8a774c0-cpg-mssr.c
Normal file
308
drivers/clk/renesas/r8a774c0-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a77990-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774C0_CLK_CANFD,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL0D4,
|
||||
CLK_PLL0D6,
|
||||
CLK_PLL0D8,
|
||||
CLK_PLL0D20,
|
||||
CLK_PLL0D24,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774c0_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
|
||||
DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
|
||||
DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1),
|
||||
DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
|
||||
DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
|
||||
DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
|
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
|
||||
DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
|
||||
DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
|
||||
DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("s0d1", R8A774C0_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d3", R8A774C0_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d6", R8A774C0_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12", R8A774C0_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24", R8A774C0_CLK_S0D24, CLK_S0, 24, 1),
|
||||
DEF_FIXED("s1d1", R8A774C0_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A774C0_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774C0_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774C0_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774C0_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774C0_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
|
||||
DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
|
||||
DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
|
||||
DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
|
||||
DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
|
||||
DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C),
|
||||
DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
|
||||
DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A774C0_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774C0_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774C0_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774C0_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("sdif3", 311, R8A774C0_CLK_SD3),
|
||||
DEF_MOD("sdif1", 313, R8A774C0_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774C0_CLK_SD0),
|
||||
DEF_MOD("pcie0", 319, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774C0_CLK_S3D1),
|
||||
|
||||
DEF_MOD("rwdt", 402, R8A774C0_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
|
||||
|
||||
DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif1", 519, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("thermal", 522, R8A774C0_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774C0_CLK_S3D4C),
|
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("vspd0", 623, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
|
||||
|
||||
DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1),
|
||||
|
||||
DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A774C0_CLK_S3D2),
|
||||
|
||||
DEF_MOD("gpio6", 906, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774C0_CLK_S3D2),
|
||||
|
||||
DEF_MOD("i2c7", 1003, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/1 x100/3 x100/3
|
||||
* 1 48 x 1 x100/1 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a774c0_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a774c0_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a774c0_cpg_mssr_info = {
|
||||
.core_clk = r8a774c0_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a774c0_core_clks),
|
||||
.mod_clk = r8a774c0_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a774c0_mod_clks),
|
||||
.mstp_table = r8a774c0_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a774c0_mstp_table),
|
||||
.reset_node = "renesas,r8a774c0-rst",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = ~0,
|
||||
.get_pll_config = r8a774c0_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774c0_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774c0-cpg-mssr",
|
||||
.data = (ulong)&r8a774c0_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774c0) = {
|
||||
.name = "clk_r8a774c0",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774c0_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
358
drivers/clk/renesas/r8a774e1-cpg-mssr.c
Normal file
358
drivers/clk/renesas/r8a774e1-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,358 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774e1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774E1_CLK_CANFD,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774e1_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A774E1_CLK_RPC),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
|
||||
DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
|
||||
DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A774E1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A774E1_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A774E1_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A774E1_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A774E1_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A774E1_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A774E1_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A774E1_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d2", R8A774E1_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774E1_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774E1_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774E1_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774E1_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774E1_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774E1_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A774E1_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
|
||||
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("tmu0", 125, R8A774E1_CLK_CP),
|
||||
DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("scif5", 202, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774E1_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774E1_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A774E1_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774E1_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774E1_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774E1_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A774E1_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A774E1_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A774E1_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774E1_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A774E1_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774E1_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774E1_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A774E1_CLK_S1D2),
|
||||
DEF_MOD("audmac0", 502, R8A774E1_CLK_S1D2),
|
||||
DEF_MOD("hscif4", 516, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A774E1_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A774E1_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774E1_CLK_S0D12),
|
||||
DEF_MOD("fcpvd1", 602, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("fcpvb1", 606, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpvb0", 607, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi1", 610, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpf1", 614, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vspbc", 624, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspbd", 626, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspi1", 630, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("ehci0", 703, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("csi20", 714, R8A774E1_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A774E1_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A774E1_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A774E1_CLK_S0D4),
|
||||
DEF_MOD("hdmi0", 729, R8A774E1_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A774E1_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("gpio7", 905, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("adg", 922, R8A774E1_CLK_S0D1),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774E1_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774E1_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
/* RMSTPCR[0-11] is not present on RZ/G2H */
|
||||
static const struct mstp_stop_table r8a774e1_mstp_table[] = {
|
||||
{ 0x00640800, 0x0, 0x0, 0 },
|
||||
{ 0xF3EE9390, 0x0, 0x0, 0 },
|
||||
{ 0x340FAFDC, 0x2040, 0x0, 0 },
|
||||
{ 0xD80C7CDF, 0x400, 0x0, 0 },
|
||||
{ 0x80000184, 0x180, 0x0, 0 },
|
||||
{ 0x40BFFF46, 0x0, 0x0, 0 },
|
||||
{ 0xE5FBEECF, 0x0, 0x0, 0 },
|
||||
{ 0x39FFFF0E, 0x0, 0x0, 0 },
|
||||
{ 0x01F19FF4, 0x0, 0x0, 0 },
|
||||
{ 0xFFDFFFFF, 0x0, 0x0, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0x0, 0 },
|
||||
{ 0x00000000, 0x0, 0x0, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a774e1_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = {
|
||||
.core_clk = r8a774e1_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a774e1_core_clks),
|
||||
.mod_clk = r8a774e1_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a774e1_mod_clks),
|
||||
.mstp_table = r8a774e1_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a774e1_mstp_table),
|
||||
.reset_node = "renesas,r8a774e1-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a774e1_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a774e1_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a774e1-cpg-mssr",
|
||||
.data = (ulong)&r8a774e1_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a774e1) = {
|
||||
.name = "clk_r8a774e1",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a774e1_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
|
|
@ -217,8 +217,8 @@
|
|||
#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
|
|
@ -433,6 +433,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
|
|||
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
|
||||
|
||||
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
|
||||
#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
|
||||
#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
|
||||
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
|
||||
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
|
||||
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
|
||||
|
|
@ -453,7 +455,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
|
|||
|
||||
#define PINMUX_MOD_SELS \
|
||||
\
|
||||
MOD_SEL0_30_29 \
|
||||
MOD_SEL1_31 \
|
||||
MOD_SEL0_30_29 MOD_SEL1_30 \
|
||||
MOD_SEL1_29 \
|
||||
MOD_SEL0_28 MOD_SEL1_28 \
|
||||
MOD_SEL0_27_26 \
|
||||
|
|
@ -619,7 +622,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
|
||||
PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
|
||||
PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
|
||||
PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
|
||||
PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
|
||||
PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
|
||||
PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
|
||||
|
|
@ -627,7 +630,7 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
|
||||
PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
|
||||
PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
|
||||
PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
|
||||
PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
|
||||
PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
|
||||
|
|
@ -1043,7 +1046,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
|
||||
PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
|
||||
PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
|
||||
|
|
@ -1052,7 +1055,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
|
||||
PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
|
||||
PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
|
||||
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
|
||||
|
||||
/* IPSR11 */
|
||||
|
|
@ -1070,13 +1073,13 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
|
||||
PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
|
||||
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
|
||||
|
||||
|
|
@ -1181,7 +1184,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
|
||||
PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
|
||||
PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
|
||||
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
|
||||
|
|
@ -1249,7 +1252,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
|
||||
PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
|
||||
PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
|
||||
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
|
||||
|
|
@ -1534,22 +1537,22 @@ static const unsigned int avb_avtp_pps_mux[] = {
|
|||
AVB_AVTP_PPS_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int avb_avtp_match_a_pins[] = {
|
||||
/* AVB_AVTP_MATCH_A */
|
||||
static const unsigned int avb_avtp_match_pins[] = {
|
||||
/* AVB_AVTP_MATCH */
|
||||
RCAR_GP_PIN(2, 24),
|
||||
};
|
||||
|
||||
static const unsigned int avb_avtp_match_a_mux[] = {
|
||||
AVB_AVTP_MATCH_A_MARK,
|
||||
static const unsigned int avb_avtp_match_mux[] = {
|
||||
AVB_AVTP_MATCH_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int avb_avtp_capture_a_pins[] = {
|
||||
/* AVB_AVTP_CAPTURE_A */
|
||||
static const unsigned int avb_avtp_capture_pins[] = {
|
||||
/* AVB_AVTP_CAPTURE */
|
||||
RCAR_GP_PIN(2, 25),
|
||||
};
|
||||
|
||||
static const unsigned int avb_avtp_capture_a_mux[] = {
|
||||
AVB_AVTP_CAPTURE_A_MARK,
|
||||
static const unsigned int avb_avtp_capture_mux[] = {
|
||||
AVB_AVTP_CAPTURE_MARK,
|
||||
};
|
||||
|
||||
/* - CAN ------------------------------------------------------------------ */
|
||||
|
|
@ -3794,8 +3797,8 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(avb_phy_int),
|
||||
SH_PFC_PIN_GROUP(avb_mii),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_pps),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_match_a),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_capture_a),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_match),
|
||||
SH_PFC_PIN_GROUP(avb_avtp_capture),
|
||||
SH_PFC_PIN_GROUP(can0_data),
|
||||
SH_PFC_PIN_GROUP(can1_data),
|
||||
SH_PFC_PIN_GROUP(can_clk),
|
||||
|
|
@ -4071,8 +4074,8 @@ static const char * const avb_groups[] = {
|
|||
"avb_phy_int",
|
||||
"avb_mii",
|
||||
"avb_avtp_pps",
|
||||
"avb_avtp_match_a",
|
||||
"avb_avtp_capture_a",
|
||||
"avb_avtp_match",
|
||||
"avb_avtp_capture",
|
||||
};
|
||||
|
||||
static const char * const can0_groups[] = {
|
||||
|
|
@ -4967,11 +4970,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_1_0 ))
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
|
||||
GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
|
||||
2, 2, 2, 1, 1, 2, 1, 4),
|
||||
GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
|
||||
1, 2, 2, 2, 1, 1, 2, 1, 4),
|
||||
GROUP(
|
||||
/* RESERVED 31, 30 */
|
||||
0, 0, 0, 0,
|
||||
MOD_SEL1_31
|
||||
MOD_SEL1_30
|
||||
MOD_SEL1_29
|
||||
MOD_SEL1_28
|
||||
/* RESERVED 27 */
|
||||
|
|
|
|||
|
|
@ -448,12 +448,13 @@ static const struct dm_spi_ops rpc_spi_ops = {
|
|||
};
|
||||
|
||||
static const struct udevice_id rpc_spi_ids[] = {
|
||||
{ .compatible = "renesas,rpc-r7s72100" },
|
||||
{ .compatible = "renesas,rpc-r8a7795" },
|
||||
{ .compatible = "renesas,rpc-r8a7796" },
|
||||
{ .compatible = "renesas,rpc-r8a77965" },
|
||||
{ .compatible = "renesas,rpc-r8a77970" },
|
||||
{ .compatible = "renesas,rpc-r8a77995" },
|
||||
{ .compatible = "renesas,rpc-r7s72100" },
|
||||
{ .compatible = "renesas,rcar-gen3-rpc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
61
include/dt-bindings/clock/r8a774c0-cpg-mssr.h
Normal file
61
include/dt-bindings/clock/r8a774c0-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a774c0 CPG Core Clocks */
|
||||
#define R8A774C0_CLK_Z2 0
|
||||
#define R8A774C0_CLK_ZG 1
|
||||
#define R8A774C0_CLK_ZTR 2
|
||||
#define R8A774C0_CLK_ZT 3
|
||||
#define R8A774C0_CLK_ZX 4
|
||||
#define R8A774C0_CLK_S0D1 5
|
||||
#define R8A774C0_CLK_S0D3 6
|
||||
#define R8A774C0_CLK_S0D6 7
|
||||
#define R8A774C0_CLK_S0D12 8
|
||||
#define R8A774C0_CLK_S0D24 9
|
||||
#define R8A774C0_CLK_S1D1 10
|
||||
#define R8A774C0_CLK_S1D2 11
|
||||
#define R8A774C0_CLK_S1D4 12
|
||||
#define R8A774C0_CLK_S2D1 13
|
||||
#define R8A774C0_CLK_S2D2 14
|
||||
#define R8A774C0_CLK_S2D4 15
|
||||
#define R8A774C0_CLK_S3D1 16
|
||||
#define R8A774C0_CLK_S3D2 17
|
||||
#define R8A774C0_CLK_S3D4 18
|
||||
#define R8A774C0_CLK_S0D6C 19
|
||||
#define R8A774C0_CLK_S3D1C 20
|
||||
#define R8A774C0_CLK_S3D2C 21
|
||||
#define R8A774C0_CLK_S3D4C 22
|
||||
#define R8A774C0_CLK_LB 23
|
||||
#define R8A774C0_CLK_CL 24
|
||||
#define R8A774C0_CLK_ZB3 25
|
||||
#define R8A774C0_CLK_ZB3D2 26
|
||||
#define R8A774C0_CLK_CR 27
|
||||
#define R8A774C0_CLK_CRD2 28
|
||||
#define R8A774C0_CLK_SD0H 29
|
||||
#define R8A774C0_CLK_SD0 30
|
||||
#define R8A774C0_CLK_SD1H 31
|
||||
#define R8A774C0_CLK_SD1 32
|
||||
#define R8A774C0_CLK_SD3H 33
|
||||
#define R8A774C0_CLK_SD3 34
|
||||
#define R8A774C0_CLK_RPC 35
|
||||
#define R8A774C0_CLK_RPCD2 36
|
||||
#define R8A774C0_CLK_ZA2 37
|
||||
#define R8A774C0_CLK_ZA8 38
|
||||
#define R8A774C0_CLK_Z2D 39
|
||||
#define R8A774C0_CLK_MSO 40
|
||||
#define R8A774C0_CLK_R 41
|
||||
#define R8A774C0_CLK_OSC 42
|
||||
#define R8A774C0_CLK_LV0 43
|
||||
#define R8A774C0_CLK_LV1 44
|
||||
#define R8A774C0_CLK_CSI0 45
|
||||
#define R8A774C0_CLK_CP 46
|
||||
#define R8A774C0_CLK_CPEX 47
|
||||
#define R8A774C0_CLK_CANFD 48
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
|
||||
25
include/dt-bindings/power/r8a774c0-sysc.h
Normal file
25
include/dt-bindings/power/r8a774c0-sysc.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A774C0_PD_CA53_CPU0 5
|
||||
#define R8A774C0_PD_CA53_CPU1 6
|
||||
#define R8A774C0_PD_A3VC 14
|
||||
#define R8A774C0_PD_3DG_A 17
|
||||
#define R8A774C0_PD_3DG_B 18
|
||||
#define R8A774C0_PD_CA53_SCU 21
|
||||
#define R8A774C0_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A774C0_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user