mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
arm: dts: socfpga: arria10: Move to use generic handoff dtsi
Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
parent
ed9c0823c5
commit
98c28a79b4
290
arch/arm/dts/socfpga_arria10-handoff.dtsi
Normal file
290
arch/arm/dts/socfpga_arria10-handoff.dtsi
Normal file
|
|
@ -0,0 +1,290 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <EOSC1_CLK_HZ>;
|
||||
clock-output-names = "altera_arria10_hps_eosc1-clk";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
|
||||
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/* Clock source: altera_arria10_hps_f2h_free */
|
||||
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <F2H_FREE_CLK_HZ>;
|
||||
clock-output-names = "altera_arria10_hps_f2h_free-clk";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
clkmgr@0xffd04000 {
|
||||
compatible = "altr,socfpga-a10-clk-init";
|
||||
reg = <0xffd04000 0x00000200>;
|
||||
reg-names = "soc_clock_manager_OCP_SLV";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
mainpll {
|
||||
vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
|
||||
vco1-denom = <MAINPLLGRP_VCO1_DENOM>;
|
||||
vco1-numer = <MAINPLLGRP_VCO1_NUMER>;
|
||||
mpuclk-cnt = <MAINPLLGRP_MPUCLK_CNT>;
|
||||
mpuclk-src = <MAINPLLGRP_MPUCLK_SRC>;
|
||||
nocclk-cnt = <MAINPLLGRP_NOCCLK_CNT>;
|
||||
nocclk-src = <MAINPLLGRP_NOCCLK_SRC>;
|
||||
cntr2clk-cnt = <MAINPLLGRP_CNTR2CLK_CNT>;
|
||||
cntr3clk-cnt = <MAINPLLGRP_CNTR3CLK_CNT>;
|
||||
cntr4clk-cnt = <MAINPLLGRP_CNTR4CLK_CNT>;
|
||||
cntr5clk-cnt = <MAINPLLGRP_CNTR5CLK_CNT>;
|
||||
cntr6clk-cnt = <MAINPLLGRP_CNTR6CLK_CNT>;
|
||||
cntr7clk-cnt = <MAINPLLGRP_CNTR7CLK_CNT>;
|
||||
cntr7clk-src = <MAINPLLGRP_CNTR7CLK_SRC>;
|
||||
cntr8clk-cnt = <MAINPLLGRP_CNTR8CLK_CNT>;
|
||||
cntr9clk-cnt = <MAINPLLGRP_CNTR9CLK_CNT>;
|
||||
cntr9clk-src = <MAINPLLGRP_CNTR9CLK_SRC>;
|
||||
cntr15clk-cnt = <MAINPLLGRP_CNTR15CLK_CNT>;
|
||||
nocdiv-l4mainclk = <MAINPLLGRP_NOCDIV_L4MAINCLK>;
|
||||
nocdiv-l4mpclk = <MAINPLLGRP_NOCDIV_L4MPCLK>;
|
||||
nocdiv-l4spclk = <MAINPLLGRP_NOCDIV_L4SPCLK>;
|
||||
nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
|
||||
nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
|
||||
nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
perpll {
|
||||
vco0-psrc = <PERPLLGRP_VCO0_PSRC>;
|
||||
vco1-denom = <PERPLLGRP_VCO1_DENOM>;
|
||||
vco1-numer = <PERPLLGRP_VCO1_NUMER>;
|
||||
cntr2clk-cnt = <PERPLLGRP_CNTR2CLK_CNT>;
|
||||
cntr2clk-src = <PERPLLGRP_CNTR2CLK_SRC>;
|
||||
cntr3clk-cnt = <PERPLLGRP_CNTR3CLK_CNT>;
|
||||
cntr3clk-src = <PERPLLGRP_CNTR3CLK_SRC>;
|
||||
cntr4clk-cnt = <PERPLLGRP_CNTR4CLK_CNT>;
|
||||
cntr4clk-src = <PERPLLGRP_CNTR4CLK_SRC>;
|
||||
cntr5clk-cnt = <PERPLLGRP_CNTR5CLK_CNT>;
|
||||
cntr5clk-src = <PERPLLGRP_CNTR5CLK_SRC>;
|
||||
cntr6clk-cnt = <PERPLLGRP_CNTR6CLK_CNT>;
|
||||
cntr6clk-src = <PERPLLGRP_CNTR6CLK_SRC>;
|
||||
cntr7clk-cnt = <PERPLLGRP_CNTR7CLK_CNT>;
|
||||
cntr8clk-cnt = <PERPLLGRP_CNTR8CLK_CNT>;
|
||||
cntr8clk-src = <PERPLLGRP_CNTR8CLK_SRC>;
|
||||
cntr9clk-cnt = <PERPLLGRP_CNTR9CLK_CNT>;
|
||||
emacctl-emac0sel = <PERPLLGRP_EMACCTL_EMAC0SEL>;
|
||||
emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
|
||||
emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
|
||||
gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
alteragrp {
|
||||
nocclk = <ALTERAGRP_NOCCLK>;
|
||||
mpuclk = <ALTERAGRP_MPUCLK>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
i_io48_pin_mux: pinmux@0xffd07000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0xffd07000 0x00000800>;
|
||||
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
shared {
|
||||
reg = <0xffd07000 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
pinctrl-single,pins =
|
||||
<0x00000000 PINMUX_SHARED_IO_Q1_1_SEL>,
|
||||
<0x00000004 PINMUX_SHARED_IO_Q1_2_SEL>,
|
||||
<0x00000008 PINMUX_SHARED_IO_Q1_3_SEL>,
|
||||
<0x0000000c PINMUX_SHARED_IO_Q1_4_SEL>,
|
||||
<0x00000010 PINMUX_SHARED_IO_Q1_5_SEL>,
|
||||
<0x00000014 PINMUX_SHARED_IO_Q1_6_SEL>,
|
||||
<0x00000018 PINMUX_SHARED_IO_Q1_7_SEL>,
|
||||
<0x0000001c PINMUX_SHARED_IO_Q1_8_SEL>,
|
||||
<0x00000020 PINMUX_SHARED_IO_Q1_9_SEL>,
|
||||
<0x00000024 PINMUX_SHARED_IO_Q1_10_SEL>,
|
||||
<0x00000028 PINMUX_SHARED_IO_Q1_11_SEL>,
|
||||
<0x0000002c PINMUX_SHARED_IO_Q1_12_SEL>,
|
||||
<0x00000030 PINMUX_SHARED_IO_Q2_1_SEL>,
|
||||
<0x00000034 PINMUX_SHARED_IO_Q2_2_SEL>,
|
||||
<0x00000038 PINMUX_SHARED_IO_Q2_3_SEL>,
|
||||
<0x0000003c PINMUX_SHARED_IO_Q2_4_SEL>,
|
||||
<0x00000040 PINMUX_SHARED_IO_Q2_5_SEL>,
|
||||
<0x00000044 PINMUX_SHARED_IO_Q2_6_SEL>,
|
||||
<0x00000048 PINMUX_SHARED_IO_Q2_7_SEL>,
|
||||
<0x0000004c PINMUX_SHARED_IO_Q2_8_SEL>,
|
||||
<0x00000050 PINMUX_SHARED_IO_Q2_9_SEL>,
|
||||
<0x00000054 PINMUX_SHARED_IO_Q2_10_SEL>,
|
||||
<0x00000058 PINMUX_SHARED_IO_Q2_11_SEL>,
|
||||
<0x0000005c PINMUX_SHARED_IO_Q2_12_SEL>,
|
||||
<0x00000060 PINMUX_SHARED_IO_Q3_1_SEL>,
|
||||
<0x00000064 PINMUX_SHARED_IO_Q3_2_SEL>,
|
||||
<0x00000068 PINMUX_SHARED_IO_Q3_3_SEL>,
|
||||
<0x0000006c PINMUX_SHARED_IO_Q3_4_SEL>,
|
||||
<0x00000070 PINMUX_SHARED_IO_Q3_5_SEL>,
|
||||
<0x00000074 PINMUX_SHARED_IO_Q3_6_SEL>,
|
||||
<0x00000078 PINMUX_SHARED_IO_Q3_7_SEL>,
|
||||
<0x0000007c PINMUX_SHARED_IO_Q3_8_SEL>,
|
||||
<0x00000080 PINMUX_SHARED_IO_Q3_9_SEL>,
|
||||
<0x00000084 PINMUX_SHARED_IO_Q3_10_SEL>,
|
||||
<0x00000088 PINMUX_SHARED_IO_Q3_11_SEL>,
|
||||
<0x0000008c PINMUX_SHARED_IO_Q3_12_SEL>,
|
||||
<0x00000090 PINMUX_SHARED_IO_Q4_1_SEL>,
|
||||
<0x00000094 PINMUX_SHARED_IO_Q4_2_SEL>,
|
||||
<0x00000098 PINMUX_SHARED_IO_Q4_3_SEL>,
|
||||
<0x0000009c PINMUX_SHARED_IO_Q4_4_SEL>,
|
||||
<0x000000a0 PINMUX_SHARED_IO_Q4_5_SEL>,
|
||||
<0x000000a4 PINMUX_SHARED_IO_Q4_6_SEL>,
|
||||
<0x000000a8 PINMUX_SHARED_IO_Q4_7_SEL>,
|
||||
<0x000000ac PINMUX_SHARED_IO_Q4_8_SEL>,
|
||||
<0x000000b0 PINMUX_SHARED_IO_Q4_9_SEL>,
|
||||
<0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
|
||||
<0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
|
||||
<0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
dedicated {
|
||||
reg = <0xffd07200 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
pinctrl-single,pins =
|
||||
<0x0000000c PINMUX_DEDICATED_IO_4_SEL>,
|
||||
<0x00000010 PINMUX_DEDICATED_IO_5_SEL>,
|
||||
<0x00000014 PINMUX_DEDICATED_IO_6_SEL>,
|
||||
<0x00000018 PINMUX_DEDICATED_IO_7_SEL>,
|
||||
<0x0000001c PINMUX_DEDICATED_IO_8_SEL>,
|
||||
<0x00000020 PINMUX_DEDICATED_IO_9_SEL>,
|
||||
<0x00000024 PINMUX_DEDICATED_IO_10_SEL>,
|
||||
<0x00000028 PINMUX_DEDICATED_IO_11_SEL>,
|
||||
<0x0000002c PINMUX_DEDICATED_IO_12_SEL>,
|
||||
<0x00000030 PINMUX_DEDICATED_IO_13_SEL>,
|
||||
<0x00000034 PINMUX_DEDICATED_IO_14_SEL>,
|
||||
<0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
|
||||
<0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
|
||||
<0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
dedicated_cfg {
|
||||
reg = <0xffd07200 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x003f3f3f>;
|
||||
pinctrl-single,pins =
|
||||
<0x00000100 CONFIG_IO_BANK_VSEL>,
|
||||
<0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
|
||||
<0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
|
||||
<0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
|
||||
<0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
|
||||
<0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
|
||||
<0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
|
||||
<0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
|
||||
<0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
|
||||
<0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
|
||||
<0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
|
||||
<0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
|
||||
<0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
|
||||
<0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
|
||||
<0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
|
||||
<0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
|
||||
<0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
|
||||
<0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
fpga {
|
||||
reg = <0xffd07400 0x00000100>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x00000001>;
|
||||
pinctrl-single,pins =
|
||||
<0x00000000 PINMUX_RGMII0_USEFPGA_SEL>,
|
||||
<0x00000004 PINMUX_RGMII1_USEFPGA_SEL>,
|
||||
<0x00000008 PINMUX_RGMII2_USEFPGA_SEL>,
|
||||
<0x0000000c PINMUX_I2C0_USEFPGA_SEL>,
|
||||
<0x00000010 PINMUX_I2C1_USEFPGA_SEL>,
|
||||
<0x00000014 PINMUX_I2CEMAC0_USEFPGA_SEL>,
|
||||
<0x00000018 PINMUX_I2CEMAC1_USEFPGA_SEL>,
|
||||
<0x0000001c PINMUX_I2CEMAC2_USEFPGA_SEL>,
|
||||
<0x00000020 PINMUX_NAND_USEFPGA_SEL>,
|
||||
<0x00000024 PINMUX_QSPI_USEFPGA_SEL>,
|
||||
<0x00000028 PINMUX_SDMMC_USEFPGA_SEL>,
|
||||
<0x0000002c PINMUX_SPIM0_USEFPGA_SEL>,
|
||||
<0x00000030 PINMUX_SPIM1_USEFPGA_SEL>,
|
||||
<0x00000034 PINMUX_SPIS0_USEFPGA_SEL>,
|
||||
<0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
|
||||
<0x0000003c PINMUX_UART0_USEFPGA_SEL>,
|
||||
<0x00000040 PINMUX_UART1_USEFPGA_SEL>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
i_noc: noc@0xffd10000 {
|
||||
compatible = "altr,socfpga-a10-noc";
|
||||
reg = <0xffd10000 0x00008000>;
|
||||
reg-names = "mpu_m0";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
firewall {
|
||||
mpu0 = <0x00000000 0x0000ffff>;
|
||||
l3-0 = <0x00000000 0x0000ffff>;
|
||||
fpga2sdram0-0 = <0x00000000 0x0000ffff>;
|
||||
fpga2sdram1-0 = <0x00000000 0x0000ffff>;
|
||||
fpga2sdram2-0 = <0x00000000 0x0000ffff>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
hps_fpgabridge0: fpgabridge@0 {
|
||||
compatible = "altr,socfpga-hps2fpga-bridge";
|
||||
init-val = <H2F_AXI_MASTER>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
hps_fpgabridge1: fpgabridge@1 {
|
||||
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
||||
init-val = <LWH2F_AXI_MASTER>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
hps_fpgabridge2: fpgabridge@2 {
|
||||
compatible = "altr,socfpga-fpga2hps-bridge";
|
||||
init-val = <F2H_AXI_SLAVE>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
hps_fpgabridge3: fpgabridge@3 {
|
||||
compatible = "altr,socfpga-fpga2sdram0-bridge";
|
||||
init-val = <F2SDRAM0_AXI_SLAVE>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
hps_fpgabridge4: fpgabridge@4 {
|
||||
compatible = "altr,socfpga-fpga2sdram1-bridge";
|
||||
init-val = <F2SDRAM1_AXI_SLAVE>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
hps_fpgabridge5: fpgabridge@5 {
|
||||
compatible = "altr,socfpga-fpga2sdram2-bridge";
|
||||
init-val = <F2SDRAM2_AXI_SLAVE>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
|
@ -3,7 +3,8 @@
|
|||
* Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
|
||||
#include "socfpga_arria10_socdk_sdmmc_handoff.h"
|
||||
#include "socfpga_arria10-handoff.dtsi"
|
||||
#include "socfpga_arria10_handoff_u-boot.dtsi"
|
||||
#include "socfpga_arria10_socdk-u-boot.dtsi"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,329 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Intel Corporation
|
||||
*
|
||||
*<auto-generated>
|
||||
* This code was generated by a tool based on
|
||||
* handoffs from both Qsys and Quartus.
|
||||
*
|
||||
* Changes to this file may be lost if
|
||||
* the code is regenerated.
|
||||
*</auto-generated>
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
|
||||
|
||||
/* Clock sources */
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* Clock source: altera_arria10_hps_eosc1 */
|
||||
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "altera_arria10_hps_eosc1-clk";
|
||||
};
|
||||
|
||||
/* Clock source: altera_arria10_hps_cb_intosc_ls */
|
||||
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <60000000>;
|
||||
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
|
||||
};
|
||||
|
||||
/* Clock source: altera_arria10_hps_f2h_free */
|
||||
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "altera_arria10_hps_f2h_free-clk";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
|
||||
* Version: 1.0
|
||||
* Binding: device
|
||||
*/
|
||||
i_clk_mgr: clock_manager@0xffd04000 {
|
||||
compatible = "altr,socfpga-a10-clk-init";
|
||||
reg = <0xffd04000 0x00000200>;
|
||||
reg-names = "soc_clock_manager_OCP_SLV";
|
||||
|
||||
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
|
||||
mainpll {
|
||||
vco0-psrc = <0>; /* Field: vco0.psrc */
|
||||
vco1-denom = <1>; /* Field: vco1.denom */
|
||||
vco1-numer = <191>; /* Field: vco1.numer */
|
||||
mpuclk-cnt = <0>; /* Field: mpuclk.cnt */
|
||||
mpuclk-src = <0>; /* Field: mpuclk.src */
|
||||
nocclk-cnt = <0>; /* Field: nocclk.cnt */
|
||||
nocclk-src = <0>; /* Field: nocclk.src */
|
||||
cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */
|
||||
cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
|
||||
cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */
|
||||
cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */
|
||||
cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */
|
||||
cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
|
||||
cntr7clk-src = <0>; /* Field: cntr7clk.src */
|
||||
cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
|
||||
cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
|
||||
cntr9clk-src = <0>; /* Field: cntr9clk.src */
|
||||
cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
|
||||
nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
|
||||
nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */
|
||||
nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */
|
||||
nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */
|
||||
nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */
|
||||
nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
|
||||
};
|
||||
|
||||
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
|
||||
perpll {
|
||||
vco0-psrc = <0>; /* Field: vco0.psrc */
|
||||
vco1-denom = <1>; /* Field: vco1.denom */
|
||||
vco1-numer = <159>; /* Field: vco1.numer */
|
||||
cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */
|
||||
cntr2clk-src = <1>; /* Field: cntr2clk.src */
|
||||
cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */
|
||||
cntr3clk-src = <1>; /* Field: cntr3clk.src */
|
||||
cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */
|
||||
cntr4clk-src = <1>; /* Field: cntr4clk.src */
|
||||
cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */
|
||||
cntr5clk-src = <1>; /* Field: cntr5clk.src */
|
||||
cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */
|
||||
cntr6clk-src = <1>; /* Field: cntr6clk.src */
|
||||
cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */
|
||||
cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */
|
||||
cntr8clk-src = <0>; /* Field: cntr8clk.src */
|
||||
cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */
|
||||
emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
|
||||
emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
|
||||
emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
|
||||
gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */
|
||||
};
|
||||
|
||||
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
|
||||
alteragrp {
|
||||
nocclk = <0x0384000b>; /* Register: nocclk */
|
||||
mpuclk = <0x03840001>; /* Register: mpuclk */
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
|
||||
* Version: 1.0
|
||||
* Binding: pinmux
|
||||
*/
|
||||
i_io48_pin_mux: pinmux@0xffd07000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0xffd07000 0x00000800>;
|
||||
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
|
||||
|
||||
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
|
||||
shared {
|
||||
reg = <0xffd07000 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
pinctrl-single,pins =
|
||||
<0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
|
||||
<0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
|
||||
<0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
|
||||
<0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
|
||||
<0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
|
||||
<0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
|
||||
<0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
|
||||
<0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */
|
||||
<0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */
|
||||
<0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */
|
||||
<0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */
|
||||
<0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */
|
||||
<0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */
|
||||
<0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */
|
||||
<0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */
|
||||
<0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */
|
||||
<0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */
|
||||
<0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */
|
||||
<0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */
|
||||
<0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */
|
||||
<0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */
|
||||
<0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */
|
||||
<0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */
|
||||
<0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */
|
||||
<0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */
|
||||
<0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */
|
||||
<0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */
|
||||
<0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */
|
||||
<0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */
|
||||
<0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */
|
||||
<0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */
|
||||
<0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */
|
||||
<0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */
|
||||
<0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */
|
||||
<0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */
|
||||
<0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */
|
||||
<0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */
|
||||
<0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */
|
||||
<0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */
|
||||
<0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */
|
||||
<0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */
|
||||
<0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */
|
||||
<0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */
|
||||
<0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */
|
||||
<0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */
|
||||
<0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */
|
||||
<0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */
|
||||
<0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */
|
||||
};
|
||||
|
||||
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
|
||||
dedicated {
|
||||
reg = <0xffd07200 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x0000000f>;
|
||||
pinctrl-single,pins =
|
||||
<0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */
|
||||
<0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */
|
||||
<0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */
|
||||
<0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */
|
||||
<0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */
|
||||
<0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */
|
||||
<0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */
|
||||
<0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */
|
||||
<0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */
|
||||
<0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */
|
||||
<0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */
|
||||
<0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */
|
||||
<0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */
|
||||
<0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */
|
||||
};
|
||||
|
||||
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
|
||||
dedicated_cfg {
|
||||
reg = <0xffd07200 0x00000200>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x003f3f3f>;
|
||||
pinctrl-single,pins =
|
||||
<0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */
|
||||
<0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */
|
||||
<0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */
|
||||
<0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */
|
||||
<0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */
|
||||
<0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */
|
||||
<0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */
|
||||
<0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */
|
||||
<0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */
|
||||
<0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */
|
||||
<0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */
|
||||
<0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */
|
||||
<0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */
|
||||
<0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */
|
||||
<0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */
|
||||
<0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */
|
||||
<0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */
|
||||
<0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */
|
||||
};
|
||||
|
||||
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
|
||||
fpga {
|
||||
reg = <0xffd07400 0x00000100>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x00000001>;
|
||||
pinctrl-single,pins =
|
||||
<0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */
|
||||
<0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */
|
||||
<0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */
|
||||
<0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */
|
||||
<0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */
|
||||
<0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */
|
||||
<0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */
|
||||
<0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */
|
||||
<0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */
|
||||
<0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */
|
||||
<0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */
|
||||
<0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */
|
||||
<0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */
|
||||
<0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */
|
||||
<0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */
|
||||
<0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */
|
||||
<0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Driver: altera_arria10_soc_noc_arria10_uboot_driver
|
||||
* Version: 1.0
|
||||
* Binding: device
|
||||
*/
|
||||
i_noc: noc@0xffd10000 {
|
||||
compatible = "altr,socfpga-a10-noc";
|
||||
reg = <0xffd10000 0x00008000>;
|
||||
reg-names = "mpu_m0";
|
||||
|
||||
firewall {
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
|
||||
*/
|
||||
mpu0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
|
||||
*/
|
||||
l3-0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
|
||||
*/
|
||||
fpga2sdram0-0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
|
||||
*/
|
||||
fpga2sdram1-0 = <0x00000000 0x0000ffff>;
|
||||
/*
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
|
||||
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
|
||||
*/
|
||||
fpga2sdram2-0 = <0x00000000 0x0000ffff>;
|
||||
};
|
||||
};
|
||||
|
||||
hps_fpgabridge0: fpgabridge@0 {
|
||||
compatible = "altr,socfpga-hps2fpga-bridge";
|
||||
init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge1: fpgabridge@1 {
|
||||
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
||||
init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge2: fpgabridge@2 {
|
||||
compatible = "altr,socfpga-fpga2hps-bridge";
|
||||
init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge3: fpgabridge@3 {
|
||||
compatible = "altr,socfpga-fpga2sdram0-bridge";
|
||||
init-val = <1>;
|
||||
};
|
||||
|
||||
hps_fpgabridge4: fpgabridge@4 {
|
||||
compatible = "altr,socfpga-fpga2sdram1-bridge";
|
||||
init-val = <0>;
|
||||
};
|
||||
|
||||
hps_fpgabridge5: fpgabridge@5 {
|
||||
compatible = "altr,socfpga-fpga2sdram2-bridge";
|
||||
init-val = <1>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user