rockchip: Add Engicam PX30.Core C.TOUCH 2.0
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki
Kever Yang
parent
d432975cec
commit
51656ae1d1
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@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
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dtb-$(CONFIG_ROCKCHIP_PX30) += \
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px30-evb.dtb \
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px30-firefly.dtb \
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px30-px30-core-ctouch2.dtb \
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px30-px30-core-edimm2.2.dtb \
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rk3326-odroid-go2.dtb
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@ -0,0 +1,22 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2020 Engicam srl
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* Copyright (c) 2020 Amarula Solutions
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "px30.dtsi"
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#include "px30-engicam-ctouch2.dtsi"
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#include "px30-px30-core.dtsi"
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/ {
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model = "Engicam PX30.Core C.TOUCH 2.0";
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compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
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"rockchip,px30";
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chosen {
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stdout-path = "serial2:115200n8";
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};
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};
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@ -20,6 +20,13 @@ config TARGET_PX30_CORE
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* PX30.Core needs to mount on top of EDIMM2.2 for creating complete
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PX30.Core EDIMM2.2 Starter Kit.
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PX30.Core CTOUCH2:
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* PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
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* CTOUCH2.0 is a general purpose Carrier board with capacitive
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touch interface support.
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* PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
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PX30.Core C.TOUCH Carrier board.
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config ROCKCHIP_BOOT_MODE_REG
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default 0xff010200
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@ -1,3 +1,9 @@
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PX30-Core-CTOUCH2.0
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M: Jagan Teki <jagan@amarulasolutions.com>
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M: Suniel Mahesh <sunil@amarulasolutions.com>
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S: Maintained
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F: configs/px30-core-ctouch2-px30_defconfig
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PX30-Core-EDIMM2.2
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M: Jagan Teki <jagan@amarulasolutions.com>
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M: Suniel Mahesh <sunil@amarulasolutions.com>
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@ -0,0 +1,108 @@
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CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SPL_TEXT_BASE=0x00000000
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CONFIG_ROCKCHIP_PX30=y
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CONFIG_TARGET_PX30_CORE=y
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CONFIG_DEBUG_UART_CHANNEL=1
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
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CONFIG_SPL_STACK_R_ADDR=0x600000
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CONFIG_DEBUG_UART_BASE=0xFF160000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
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CONFIG_DEBUG_UART=y
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CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
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# CONFIG_ANDROID_BOOT_IMAGE is not set
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_LOAD_FIT=y
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
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CONFIG_MISC_INIT_R=y
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_BOOTROM_SUPPORT=y
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_SPL_STACK_R=y
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# CONFIG_TPL_BANNER_PRINT is not set
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CONFIG_SPL_CRC32_SUPPORT=y
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CONFIG_SPL_ATF=y
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# CONFIG_TPL_FRAMEWORK is not set
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_LZMADEC is not set
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# CONFIG_CMD_UNZIP is not set
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CONFIG_CMD_GPT=y
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_MISC is not set
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# CONFIG_SPL_DOS_PARTITION is not set
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# CONFIG_ISO_PARTITION is not set
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CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_FASTBOOT_BUF_ADDR=0x800800
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CONFIG_FASTBOOT_BUF_SIZE=0x04000000
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_ROCKCHIP_OTP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_TPL_RAM=y
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CONFIG_ROCKCHIP_SDRAM_COMMON=y
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CONFIG_DM_RESET=y
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CONFIG_DM_RNG=y
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CONFIG_RNG_ROCKCHIP=y
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# CONFIG_SPECIFY_CONSOLE_INDEX is not set
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_DEBUG_UART_SKIP_INIT=y
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CONFIG_SOUND=y
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CONFIG_SYSRESET=y
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CONFIG_DM_THERMAL=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_DWC2_OTG=y
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CONFIG_DM_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_LCD=y
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CONFIG_SPL_TINY_MEMSET=y
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CONFIG_TPL_TINY_MEMSET=y
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CONFIG_LZO=y
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CONFIG_ERRNO_STR=y
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