- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
  platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
This commit is contained in:
Tom Rini 2020-10-29 09:10:24 -04:00
commit eca57cafa5
141 changed files with 2399 additions and 119 deletions

View File

@ -1620,6 +1620,16 @@ config TARGET_LS1046AFRWY
development platform that supports the QorIQ LS1046A
Layerscape Architecture processor.
config TARGET_SL28
bool "Support sl28"
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
select BINMAN
help
Support for Kontron SMARC-sAL28 board.
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
@ -1998,6 +2008,7 @@ source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"

View File

@ -1147,15 +1147,15 @@ int arch_early_init_r(void)
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
* Now if a dpmac is enabled by serdes bits then it takes precedence
* over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
* that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
* then the dpmac is SGMII and not RGMII.
* Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
* precedence over SerDes protocol. i.e. in LX2160A if we select serdes
* protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
* RGMII, then the dpmac is RGMII and not SGMII.
*
* Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
* fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
* or not? if it is (fsl_serdes_init has already enabled the dpmac),
* then don't enable it.
* Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
* function of SOC, the dpmac will be enabled as RGMII even if it was
* also enabled before as SGMII. If ECx_PMUX is not configured for
* RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
*/
fsl_rgmii_init();
#endif

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@ -0,0 +1,67 @@
#
# Copyright 2020 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
Specifying extra IOMMU mappings for PCI controllers
This feature can be enabled through the PCI_IOMMU_EXTRA_MAPPINGS Kconfig option.
The "pci_iommu_extra" env var or "pci-iommu-extra" device tree property (to be
used for example in more static scenarios such as hardwired PCI endpoints that
get initialized later in the system setup) allows two things:
- for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number
of VFs that will ever be created for it
- for hot-plug case, specify the B.D.F with which the device will show up on
the PCI bus
The env var consists of a list of <bdf>,<action> pairs for a certain pci bus
identified by its controller's base register address, as defined in the "reg"
property in the device tree.
pci_iommu_extra = pci@<addr1>,<bdf>,<action>,<bdf>,<action>,
pci@<addr2>,<bdf>,<action>,<bdf>,<action>,...
where:
<addr> is the base register address of the pci controller for which the
subsequent <bdf>,<action> pairs apply
<bdf> identifies to which B.D.F the action applies to
<action> can be:
- "vfs=<number>" to specify that for the PCI EP identified previously by
the <bdf> to include mappings for <number> of VFs.
The variant "noari_vfs=<number>" is available to disable taking ARI into
account.
- "hp" to specify that on this <bdf> there will be a hot-plugged device so
it needs a mapping
The device tree property must be placed under the correct pci controller node
and only the bdf and action pairs need to be specified, like this:
pci-iommu-extra = "<bdf>,<action>,<bdf>,<action>,...";
Note: the env var has priority over the device tree property.
For example, given this configuration on bus 6:
=> pci 6
Scanning PCI devices on bus 6
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
06.00.00 0x8086 0x1572 Network controller 0x00
06.00.01 0x8086 0x1572 Network controller 0x00
The following u-boot env var will create iommu mappings for 3 VFs for each PF:
=> setenv pci_iommu_extra pci@0x3800000,6.0.0,vfs=3,6.0.1,vfs=3
For the device tree case, this would be specified like this:
pci-iommu-extra = "6.0.0,vfs=3,6.0.1,vfs=3";
To add an iommu mapping for a hot-plugged device, please see following example:
=> setenv pci_iommu_extra pci@0x3800000,2.16.0,hp
For the device tree case, this would be specified like this:
pci-iommu-extra = "2.16.0,hp";

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@ -437,13 +437,52 @@ __weak void fdt_fixup_ecam(void *blob)
}
#endif
/*
* If it is a non-E part the crypto is disabled on the following SoCs:
* - LS1043A
* - LS1088A
* - LS2080A
* - LS2088A
* and their personalities.
*
* On all other SoCs just the export-controlled ciphers are disabled, that
* means that the following is still working:
* - hashing (using MDHA - message digest hash accelerator)
* - random number generation (using RNG4)
* - cyclic redundancy checking (using CRCA)
* - runtime integrity checker (RTIC)
*
* The linux driver will figure out what is available and what is not.
* Therefore, we just remove the crypto node on the SoCs which have no crypto
* support at all.
*/
static bool crypto_is_disabled(unsigned int svr)
{
if (IS_E_PROCESSOR(svr))
return false;
if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A)))
return true;
if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1088A)))
return true;
if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2080A)))
return true;
if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS2088A)))
return true;
return false;
}
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
if (crypto_is_disabled(svr))
fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
else {

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@ -424,6 +424,9 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1012a-2g5rdb.dtb \
fsl-ls1012a-frdm.dtb \
fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
fsl-ls1028a-kontron-sl28-var3.dtb \
fsl-ls1028a-kontron-sl28-var4.dtb \
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb

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@ -0,0 +1,135 @@
// SPDX-License-Identifier: GPL-2.0+
#include <config.h>
/ {
aliases {
mmc0 = &esdhc0;
mmc1 = &esdhc1;
i2c0 = &i2c0;
i2c1 = &i2c3;
i2c2 = &i2c4;
rtc0 = &rtc;
ethernet0 = &enetc0;
ethernet1 = &enetc1;
ethernet2 = &enetc2;
ethernet3 = &enetc6;
};
binman {
filename = "u-boot.rom";
pad-byte = <0xff>;
u-boot-spl {
};
fit {
offset = <CONFIG_SPL_PAD_TO>;
description = "FIT image with multiple configurations";
images {
uboot {
description = "U-Boot";
type = "firmware";
os = "u-boot";
arch = "arm";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
u-boot-nodtb {
};
};
fdt-1 {
description = "fsl-ls1028a-kontron-sl28";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb";
};
};
fdt-2 {
description = "fsl-ls1028a-kontron-sl28-var3";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb";
};
};
fdt-3 {
description = "fsl-ls1028a-kontron-sl28-var4";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = "arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb";
};
};
};
configurations {
default = "conf-1";
conf-1 {
description = "fsl-ls1028a-kontron-sl28";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-1";
};
conf-2 {
description = "fsl-ls1028a-kontron-sl28-var3";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-2";
};
conf-3 {
description = "fsl-ls1028a-kontron-sl28-var4";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-3";
};
};
};
};
};
&i2c0 {
rtc: rtc@32 {
};
};
&fspi {
u-boot,dm-pre-reloc;
flash@0 {
u-boot,dm-pre-reloc;
};
};
&dspi2 {
u-boot,dm-pre-reloc;
};
&esdhc0 {
u-boot,dm-pre-reloc;
};
&esdhc1 {
u-boot,dm-pre-reloc;
};
&serial0 {
u-boot,dm-pre-reloc;
};
&sysclk {
u-boot,dm-pre-reloc;
};

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@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"

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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
/ {
model = "Kontron SMARC-sAL28 (Single PHY)";
compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a";
};

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@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0+
#include "fsl-ls1028a-kontron-sl28-u-boot.dtsi"

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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* This is for the network variant 4 which has two ethernet ports. It
* extends the base and provides one more port connected via RGMII.
*
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
#include <dt-bindings/net/qca-ar803x.h>
/ {
model = "Kontron SMARC-sAL28 (Dual PHY)";
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};
&enetc1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};
&mdio0 {
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
vddio-supply = <&vddh>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};

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@ -0,0 +1,189 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "Kontron SMARC-sAL28";
compatible = "kontron,sl28", "fsl,ls1028a";
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &lpuart1;
spi0 = &fspi;
spi1 = &dspi2;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&dspi2 {
status = "okay";
};
&enetc0 {
phy-handle = <&phy0>;
phy-mode = "sgmii";
status = "okay";
};
&enetc2 {
status = "disabled";
};
&enetc6 {
status = "disabled";
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&fspi {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
m25p,fast-read;
spi-max-frequency = <133000000>;
reg = <0>;
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
partition@0 {
reg = <0x000000 0x010000>;
label = "rcw";
read-only;
};
partition@10000 {
reg = <0x010000 0x0f0000>;
label = "failsafe bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x040000>;
label = "failsafe DP firmware";
read-only;
};
partition@140000 {
reg = <0x140000 0x0a0000>;
label = "failsafe trusted firmware";
read-only;
};
partition@1e0000 {
reg = <0x1e0000 0x020000>;
label = "reserved";
read-only;
};
partition@200000 {
reg = <0x200000 0x010000>;
label = "configuration store";
};
partition@210000 {
reg = <0x210000 0x0f0000>;
label = "bootloader";
};
partition@300000 {
reg = <0x300000 0x040000>;
label = "DP firmware";
};
partition@340000 {
reg = <0x340000 0x0a0000>;
label = "trusted firmware";
};
partition@3e0000 {
reg = <0x3e0000 0x020000>;
label = "bootloader environment";
};
};
};
&i2c0 {
status = "okay";
rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&lpuart1 {
status = "okay";
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@5 {
reg = <0x5>;
eee-broken-1000t;
eee-broken-100tx;
};
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};

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@ -396,7 +396,7 @@ struct ccsr_gur {
#define FSL_CHASSIS3_EC2_REGSR 27
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x0000000C
#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16

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@ -379,6 +379,7 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
{
int ret, vdd_last, vdd_target = vdd;
int count = 100, temp = 0;
unsigned char value;
/* Scale up to the LTC resolution is 1/4096V */
vdd = (vdd * 4096) / 1000;
@ -391,16 +392,51 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
/* Write the desired voltage code to the regulator */
#ifndef CONFIG_DM_I2C
/* Check write protect state */
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_WRITE_PROTECT, 1,
(void *)&value, sizeof(value));
if (ret)
goto exit;
if (value != EN_WRITE_ALL_CMD) {
value = EN_WRITE_ALL_CMD;
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_WRITE_PROTECT, 1,
(void *)&value, sizeof(value));
if (ret)
goto exit;
}
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
PMBUS_CMD_PAGE_PLUS_WRITE, 1,
(void *)&buff, sizeof(buff));
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
if (!ret)
if (!ret) {
/* Check write protect state */
ret = dm_i2c_read(dev,
PMBUS_CMD_WRITE_PROTECT,
(void *)&value, sizeof(value));
if (ret)
goto exit;
if (value != EN_WRITE_ALL_CMD) {
value = EN_WRITE_ALL_CMD;
ret = dm_i2c_write(dev,
PMBUS_CMD_WRITE_PROTECT,
(void *)&value, sizeof(value));
if (ret)
goto exit;
}
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
(void *)&buff, 5);
(void *)&buff, sizeof(buff));
}
#endif
exit:
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@ -892,7 +928,7 @@ exit:
static int print_vdd(void)
{
int vdd_last, ret, i2caddress;
int vdd_last, ret, i2caddress = 0;
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {

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@ -18,6 +18,25 @@
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
#define IR_VDD_STEP_UP 5
/* LTC3882 */
#define PMBUS_CMD_WRITE_PROTECT 0x10
/*
* WRITE_PROTECT command supported values
* 0x80: Disable all writes except WRITE_PROTECT, PAGE,
* STORE_USER_ALL and MFR_EE_UNLOCK commands.
* 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL,
* MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands.
* Individual faults can also be cleared by writing a 1 to the
* respective status bit.
* 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL,
* MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG
* and VOUT_COMMAND commands. Individual faults can be cleared by
* writing a 1 to the respective status bit.
* 0x00: Enables write to all commands
*/
#define EN_WRITE_ALL_CMD (0)
int adjust_vdd(ulong vdd_override);
#endif /* __VID_H_ */

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@ -0,0 +1,18 @@
if TARGET_SL28
config SYS_BOARD
default "sl28"
config SYS_VENDOR
default "kontron"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "kontron_sl28"
config SYS_TEXT_BASE
default 0x96000000
endif

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@ -0,0 +1,7 @@
Kontron SMARC-sAL28 board
M: Michael Walle <michael@walle.cc>
S: Maintained
F: arch/arm/dts/fsl-ls1028a-kontron-sl28-*
F: board/kontron/sl28/
F: configs/kontron_sl28_defconfig
F: include/configs/kontron_sl28.h

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@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
ifndef CONFIG_SPL_BUILD
obj-y += sl28.o cmds.o
endif
obj-y += common.o ddr.o
obj-$(CONFIG_SPL_BUILD) += spl.o

178
board/kontron/sl28/cmds.c Normal file
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@ -0,0 +1,178 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* sl28 extension commands
*
* Copyright (c) 2020 Kontron Europe GmbH
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <linux/delay.h>
#define CPLD_I2C_ADDR 0x4a
#define REG_UFM_CTRL 0x02
#define UFM_CTRL_DCLK BIT(1)
#define UFM_CTRL_DIN BIT(2)
#define UFM_CTRL_PROGRAM BIT(3)
#define UFM_CTRL_ERASE BIT(4)
#define UFM_CTRL_DSHIFT BIT(5)
#define UFM_CTRL_DOUT BIT(6)
#define UFM_CTRL_BUSY BIT(7)
static int ufm_shift_data(struct udevice *dev, u16 data_in, u16 *data_out)
{
int i;
int ret;
u16 data = 0;
/* latch data */
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, 0);
if (ret < 0)
return ret;
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
if (ret < 0)
return ret;
/* assert drshift */
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
UFM_CTRL_DSHIFT | UFM_CTRL_DCLK);
if (ret < 0)
return ret;
/* clock 16 data bits, reverse order */
for (i = 15; i >= 0; i--) {
u8 din = (data_in & (1 << i)) ? UFM_CTRL_DIN : 0;
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DSHIFT
| din);
if (ret < 0)
return ret;
if (data_out) {
ret = dm_i2c_reg_read(dev, REG_UFM_CTRL);
if (ret < 0)
return ret;
if (ret & UFM_CTRL_DOUT)
data |= (1 << i);
}
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
UFM_CTRL_DSHIFT | UFM_CTRL_DCLK | din);
if (ret < 0)
return ret;
}
/* deassert drshift */
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
if (ret < 0)
return ret;
if (data_out)
*data_out = data;
return ret;
}
static int ufm_erase(struct udevice *dev)
{
int ret;
/* erase, tEPMX is 500ms */
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
UFM_CTRL_DCLK | UFM_CTRL_ERASE);
if (ret < 0)
return ret;
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
if (ret < 0)
return ret;
mdelay(500);
return 0;
}
static int ufm_program(struct udevice *dev)
{
int ret;
/* program, tPPMX is 100us */
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
UFM_CTRL_DCLK | UFM_CTRL_PROGRAM);
if (ret < 0)
return ret;
ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
if (ret < 0)
return ret;
udelay(100);
return 0;
}
static int ufm_write(struct udevice *dev, u16 data)
{
int ret;
ret = ufm_shift_data(dev, data, NULL);
if (ret < 0)
return ret;
ret = ufm_erase(dev);
if (ret < 0)
return ret;
return ufm_program(dev);
}
static int ufm_read(struct udevice *dev, u16 *data)
{
return ufm_shift_data(dev, 0, data);
}
static int do_sl28_nvm(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct udevice *dev;
u16 nvm;
int ret;
char *endp;
if (i2c_get_chip_for_busnum(0, CPLD_I2C_ADDR, 1, &dev))
return CMD_RET_FAILURE;
if (argc > 1) {
nvm = simple_strtoul(argv[1], &endp, 16);
if (*endp != '\0') {
printf("ERROR: argument is not a valid number\n");
ret = -EINVAL;
goto out;
}
/*
* We swap all bits, because the a zero bit in hardware means the
* feature is enabled. But this is hard for the user.
*/
nvm ^= 0xffff;
ret = ufm_write(dev, nvm);
if (ret)
goto out;
printf("New settings will be activated after the next power cycle!\n");
} else {
ret = ufm_read(dev, &nvm);
if (ret)
goto out;
nvm ^= 0xffff;
printf("%04hx\n", nvm);
}
return CMD_RET_SUCCESS;
out:
printf("command failed (%d)\n", ret);
return CMD_RET_FAILURE;
}
static char sl28_help_text[] =
"nvm [<hex>] - display/set the 16 non-volatile bits\n";
U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text,
U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm));

View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/arch-fsl-layerscape/soc.h>
int board_early_init_f(void)
{
fsl_lsch3_early_init_f();
return 0;
}

98
board/kontron/sl28/ddr.c Normal file
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@ -0,0 +1,98 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
#define DCFG_GPPORCR1 0x20
#define GPPORCR1_MEM_MASK (0x7 << 5)
#define GPPORCR1_MEM_512MB_CS0 (0x0 << 5)
#define GPPORCR1_MEM_1GB_CS0 (0x1 << 5)
#define GPPORCR1_MEM_2GB_CS0 (0x2 << 5)
#define GPPORCR1_MEM_4GB_CS0_1 (0x3 << 5)
#define GPPORCR1_MEM_4GB_CS0_2 (0x4 << 5)
#define GPPORCR1_MEM_8GB_CS0_1_2_3 (0x5 << 5)
#define GPPORCR1_MEM_8GB_CS0_1 (0x6 << 5)
static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
.cs[0].bnds = 0x0000007f,
.cs[0].config = 0x80044402,
.cs[1].bnds = 0x008000ff,
.cs[1].config = 0x80004402,
.timing_cfg_0 = 0x9011010c,
.timing_cfg_3 = 0x010c1000,
.timing_cfg_1 = 0xbcb48c66,
.timing_cfg_2 = 0x0fc0d118,
.ddr_sdram_cfg = 0xe70c000c,
.ddr_sdram_cfg_2 = 0x24401111,
.ddr_sdram_mode = 0x00441c70,
.ddr_sdram_mode_3 = 0x00001c70,
.ddr_sdram_mode_5 = 0x00001c70,
.ddr_sdram_mode_7 = 0x00001c70,
.ddr_sdram_mode_2 = 0x00180000,
.ddr_sdram_mode_4 = 0x00180000,
.ddr_sdram_mode_6 = 0x00180000,
.ddr_sdram_mode_8 = 0x00180000,
.ddr_sdram_interval = 0x0c30030c,
.ddr_data_init = 0xdeadbeef,
.ddr_sdram_clk_cntl = 0x02400000,
.timing_cfg_4 = 0x00000001,
.timing_cfg_5 = 0x04401400,
.ddr_zq_cntl = 0x89080600,
.ddr_wrlvl_cntl = 0x8675f606,
.ddr_wrlvl_cntl_2 = 0x04080700,
.ddr_wrlvl_cntl_3 = 0x00000009,
.ddr_cdr1 = 0x80040000,
.ddr_cdr2 = 0x0000bc01,
};
int fsl_initdram(void)
{
u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
phys_size_t dram_size;
switch (gpporcr1 & GPPORCR1_MEM_MASK) {
case GPPORCR1_MEM_2GB_CS0:
dram_size = 0x80000000;
ddr_cfg_regs.cs[1].bnds = 0;
ddr_cfg_regs.cs[1].config = 0;
ddr_cfg_regs.cs[1].config_2 = 0;
break;
case GPPORCR1_MEM_4GB_CS0_1:
dram_size = 0x100000000ULL;
break;
case GPPORCR1_MEM_512MB_CS0:
dram_size = 0x20000000;
fallthrough; /* for now */
case GPPORCR1_MEM_1GB_CS0:
dram_size = 0x40000000;
fallthrough; /* for now */
case GPPORCR1_MEM_4GB_CS0_2:
dram_size = 0x100000000ULL;
fallthrough; /* for now */
case GPPORCR1_MEM_8GB_CS0_1:
case GPPORCR1_MEM_8GB_CS0_1_2_3:
dram_size = 0x200000000ULL;
fallthrough; /* for now */
default:
panic("Unsupported memory configuration (%08x)\n",
gpporcr1 & GPPORCR1_MEM_MASK);
break;
}
if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
gd->ram_size = dram_size;
return 0;
}

68
board/kontron/sl28/sl28.c Normal file
View File

@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <fsl_ddr.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#include <fsl_immap.h>
#include <netdev.h>
#include <fdtdec.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
if (CONFIG_IS_ENABLED(FSL_CAAM))
sec_init();
return 0;
}
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
int checkboard(void)
{
printf("EL: %d\n", current_el());
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int nbanks = CONFIG_NR_DRAM_BANKS;
int i;
ft_cpu_setup(blob, bd);
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < nbanks; i++) {
base[i] = gd->bd->bi_dram[i].start;
size[i] = gd->bd->bi_dram[i].size;
}
fdt_fixup_memory_banks(blob, base, size, nbanks);
fdt_fixup_icid(blob);
return 0;
}

32
board/kontron/sl28/spl.c Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/io.h>
#include <asm/spl.h>
#define DCFG_RCWSR25 0x160
#define GPINFO_HW_VARIANT_MASK 0xff
int sl28_variant(void)
{
return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
}
int board_fit_config_name_match(const char *name)
{
int variant = sl28_variant();
switch (variant) {
case 3:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
case 4:
return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
default:
return strcmp(name, "fsl-ls1028a-kontron-sl28");
}
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_SPI;
}

View File

@ -1074,6 +1074,14 @@ config CMD_CLONE
initial flashing by external block device without network
or usb support.
config CMD_OPTEE_RPMB
bool "Enable read/write support on RPMB via OPTEE"
depends on SUPPORT_EMMC_RPMB && OPTEE
help
Enable the commands for reading, writing persistent named values
in the Replay Protection Memory Block partition in eMMC by
using Persistent Objects in OPTEE
config CMD_MTD
bool "mtd"
depends on MTD

View File

@ -98,6 +98,7 @@ obj-$(CONFIG_CMD_MISC) += misc.o
obj-$(CONFIG_CMD_MDIO) += mdio.o
obj-$(CONFIG_CMD_SLEEP) += sleep.o
obj-$(CONFIG_CMD_MMC) += mmc.o
obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_CMD_MTD) += mtd.o
obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o

272
cmd/optee_rpmb.c Normal file
View File

@ -0,0 +1,272 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
#include <command.h>
#include <common.h>
#include <env.h>
#include <errno.h>
#include <image.h>
#include <malloc.h>
#include <mmc.h>
#include <tee.h>
#include <tee/optee_ta_avb.h>
static struct udevice *tee;
static u32 session;
static int avb_ta_open_session(void)
{
const struct tee_optee_ta_uuid uuid = TA_AVB_UUID;
struct tee_open_session_arg arg;
int rc;
tee = tee_find_device(tee, NULL, NULL, NULL);
if (!tee)
return -ENODEV;
memset(&arg, 0, sizeof(arg));
tee_optee_ta_uuid_to_octets(arg.uuid, &uuid);
rc = tee_open_session(tee, &arg, 0, NULL);
if (!rc)
session = arg.session;
return 0;
}
static int invoke_func(u32 func, ulong num_param, struct tee_param *param)
{
struct tee_invoke_arg arg;
if (!tee)
if (avb_ta_open_session())
return -ENODEV;
memset(&arg, 0, sizeof(arg));
arg.func = func;
arg.session = session;
if (tee_invoke_func(tee, &arg, num_param, param))
return -EFAULT;
switch (arg.ret) {
case TEE_SUCCESS:
return 0;
case TEE_ERROR_OUT_OF_MEMORY:
case TEE_ERROR_STORAGE_NO_SPACE:
return -ENOSPC;
case TEE_ERROR_ITEM_NOT_FOUND:
return -EIO;
case TEE_ERROR_TARGET_DEAD:
/*
* The TA has paniced, close the session to reload the TA
* for the next request.
*/
tee_close_session(tee, session);
tee = NULL;
return -EIO;
default:
return -EIO;
}
}
static int read_persistent_value(const char *name,
size_t buffer_size,
u8 *out_buffer,
size_t *out_num_bytes_read)
{
int rc = 0;
struct tee_shm *shm_name;
struct tee_shm *shm_buf;
struct tee_param param[2];
size_t name_size = strlen(name) + 1;
if (!tee)
if (avb_ta_open_session())
return -ENODEV;
rc = tee_shm_alloc(tee, name_size,
TEE_SHM_ALLOC, &shm_name);
if (rc)
return -ENOMEM;
rc = tee_shm_alloc(tee, buffer_size,
TEE_SHM_ALLOC, &shm_buf);
if (rc) {
rc = -ENOMEM;
goto free_name;
}
memcpy(shm_name->addr, name, name_size);
memset(param, 0, sizeof(param));
param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
param[0].u.memref.shm = shm_name;
param[0].u.memref.size = name_size;
param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT;
param[1].u.memref.shm = shm_buf;
param[1].u.memref.size = buffer_size;
rc = invoke_func(TA_AVB_CMD_READ_PERSIST_VALUE,
2, param);
if (rc)
goto out;
if (param[1].u.memref.size > buffer_size) {
rc = -EINVAL;
goto out;
}
*out_num_bytes_read = param[1].u.memref.size;
memcpy(out_buffer, shm_buf->addr, *out_num_bytes_read);
out:
tee_shm_free(shm_buf);
free_name:
tee_shm_free(shm_name);
return rc;
}
static int write_persistent_value(const char *name,
size_t value_size,
const u8 *value)
{
int rc = 0;
struct tee_shm *shm_name;
struct tee_shm *shm_buf;
struct tee_param param[2];
size_t name_size = strlen(name) + 1;
if (!tee) {
if (avb_ta_open_session())
return -ENODEV;
}
if (!value_size)
return -EINVAL;
rc = tee_shm_alloc(tee, name_size,
TEE_SHM_ALLOC, &shm_name);
if (rc)
return -ENOMEM;
rc = tee_shm_alloc(tee, value_size,
TEE_SHM_ALLOC, &shm_buf);
if (rc) {
rc = -ENOMEM;
goto free_name;
}
memcpy(shm_name->addr, name, name_size);
memcpy(shm_buf->addr, value, value_size);
memset(param, 0, sizeof(param));
param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
param[0].u.memref.shm = shm_name;
param[0].u.memref.size = name_size;
param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
param[1].u.memref.shm = shm_buf;
param[1].u.memref.size = value_size;
rc = invoke_func(TA_AVB_CMD_WRITE_PERSIST_VALUE,
2, param);
if (rc)
goto out;
out:
tee_shm_free(shm_buf);
free_name:
tee_shm_free(shm_name);
return rc;
}
int do_optee_rpmb_read(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
const char *name;
size_t bytes;
size_t bytes_read;
void *buffer;
char *endp;
if (argc != 3)
return CMD_RET_USAGE;
name = argv[1];
bytes = simple_strtoul(argv[2], &endp, 10);
if (*endp && *endp != '\n')
return CMD_RET_USAGE;
buffer = malloc(bytes);
if (!buffer)
return CMD_RET_FAILURE;
if (read_persistent_value(name, bytes, buffer, &bytes_read) == 0) {
printf("Read %zu bytes, value = %s\n", bytes_read,
(char *)buffer);
free(buffer);
return CMD_RET_SUCCESS;
}
printf("Failed to read persistent value\n");
free(buffer);
return CMD_RET_FAILURE;
}
int do_optee_rpmb_write(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
const char *name;
const char *value;
if (argc != 3)
return CMD_RET_USAGE;
name = argv[1];
value = argv[2];
if (write_persistent_value(name, strlen(value) + 1,
(const uint8_t *)value) == 0) {
printf("Wrote %zu bytes\n", strlen(value) + 1);
return CMD_RET_SUCCESS;
}
printf("Failed to write persistent value\n");
return CMD_RET_FAILURE;
}
static struct cmd_tbl cmd_optee_rpmb[] = {
U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_optee_rpmb_read, "", ""),
U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_optee_rpmb_write, "", ""),
};
static int do_optee_rpmb(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
struct cmd_tbl *cp;
cp = find_cmd_tbl(argv[1], cmd_optee_rpmb, ARRAY_SIZE(cmd_optee_rpmb));
argc--;
argv++;
if (!cp || argc > cp->maxargs)
return CMD_RET_USAGE;
if (flag == CMD_FLAG_REPEAT)
return CMD_RET_FAILURE;
return cp->cmd(cmdtp, flag, argc, argv);
}
U_BOOT_CMD (
optee_rpmb, 29, 0, do_optee_rpmb,
"Provides commands for testing secure storage on RPMB on OPTEE",
"read_pvalue <name> <bytes> - read a persistent value <name>\n"
"optee_rpmb write_pvalue <name> <value> - write a persistent value <name>\n"
);

View File

@ -0,0 +1,107 @@
CONFIG_ARM=y
CONFIG_TARGET_SL28=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x3e0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x18010000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_SIZE_LIMIT=0x20000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_PSCI_RESET is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-kontron-sl28"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RNG=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST=""
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SCSI_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_DM_MMC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_NXP_FSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
CONFIG_OF_LIBFDT_OVERLAY=y

View File

@ -61,3 +61,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -61,3 +61,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -62,3 +62,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -63,3 +63,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -62,3 +62,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -68,3 +68,5 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -84,3 +84,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -75,3 +75,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -84,3 +84,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -66,3 +66,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -68,3 +68,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -67,3 +67,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -67,3 +67,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -55,3 +55,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -60,3 +60,5 @@ CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -73,3 +73,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -73,3 +73,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -88,3 +88,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -72,3 +72,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -74,3 +74,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -74,3 +74,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -73,3 +73,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -87,3 +87,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -85,3 +85,5 @@ CONFIG_USB_STORAGE=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -61,3 +61,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -72,3 +72,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -66,3 +66,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -68,3 +68,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -69,3 +69,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -71,3 +71,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -80,3 +80,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -82,3 +82,5 @@ CONFIG_USB_XHCI_DWC3=y
# CONFIG_VIDEO_FSL_DCU_FB is not set
# CONFIG_VIDEO is not set
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -84,3 +84,5 @@ CONFIG_WDT_SP805=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -89,3 +89,5 @@ CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -91,3 +91,5 @@ CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -81,3 +81,5 @@ CONFIG_WDT_SP805=y
CONFIG_RSA=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -90,3 +90,5 @@ CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -68,3 +68,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -70,3 +70,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -84,3 +84,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -69,3 +69,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -65,3 +65,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -85,3 +85,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -79,3 +79,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -71,3 +71,5 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -78,3 +78,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -61,3 +61,5 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -61,3 +61,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -80,3 +80,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -81,3 +81,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -80,3 +80,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -62,3 +62,5 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -65,3 +65,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -68,3 +68,5 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -69,3 +69,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -71,3 +71,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -73,3 +73,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -79,3 +79,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -69,3 +69,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -89,3 +89,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -84,3 +84,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -71,3 +71,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -81,3 +81,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -81,3 +81,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -64,3 +64,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -67,3 +67,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -86,3 +86,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_SPL_GZIP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -78,3 +78,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -80,3 +80,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -63,3 +63,5 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -68,3 +68,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

View File

@ -72,3 +72,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CMD_NVME=y
CONFIG_NVME=y

Some files were not shown because too many files have changed in this diff Show More