i.MX6SX ROM implements unified table sections.
The HAB function table is at offset 0x100. Update
the HAB function pointers accordingly.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
The mx6sl/mx6sx has 2 OTG and 1 host. So they have name
"USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes
the USB base address name to "USBOH3", which causes the driver
failed to build for mx6sl/mx6sx.
This patch uniform the address name to "USB_BASE_ADDR" for all
mx6 series.
Signed-off-by: Ye.Li <B37916@freescale.com>
Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
Instead of waiting for a fixed period of time and hoping for the best
that the DRAM will start, read back an EMI status register which tells
us exactly when the DRAM started.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
According to i.MX23 datasheet Table 32-17, we must wait for the supply
to settle before disabling the current limiter. Indeed, not waiting a
little here causes the system to crash at times.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <yorksun@freescale.com>
This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILE
Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.
Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Using CPU_HAS_PCR micro to present the SoC has pcr
(peripheral control register).
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
When use pcr (peripheral control register), then we won't need
to care about the peripheral ID.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
At the high level, the problem is that we set gd multiple times (and
still do, even after the commit we're reverting). We set important
parts of gd to the copy which is not above stack but rather in the data
section. For the release, we're going to revert this change and for the
next release we shall correct things to only, really, set gd once to an
appropriate location and ensure that comments about it are correct too.
This reverts commit f0c3a6c4ad.
Acked-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Cc: David Feng <fenghua@phytium.com.cn>
This patch moves mx35 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx35 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx35 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This patch moves mx31 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx31 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx31 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Helmut Raiger <helmut.raiger@hale.at>
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The boards using CONFIG_SYS_DV_NOR_BOOT_CFG (i.e. calimain,
da850evm_direct_nor and enbw_cmc) had the _start symbol defined after
the CONFIG_SYS_DV_NOR_BOOT_CFG word rather than before it in
arch/arm/lib/vectors.S. Because of that, if by lack of luck
'gd->mon_len = (ulong)&__bss_end - (ulong)_start' (see setup_mon_len())
was a multiple of 4 kiB (see reserve_uboot()), then the last BSS word
overlapped the first word of the following reserved RAM area (or went
beyond the top of RAM without such an area) after relocation because
__image_copy_start did not match _start (see relocate_code()).
This was broken by commit 41623c9 'arm: move exception handling out of
start.S files', which defined _start twice (before and after the
CONFIG_SYS_DV_NOR_BOOT_CFG word), then by commit 0a26e1d 'arm: fix a
double-definition error of _start symbol', which kept the definition of
the _start symbol after the CONFIG_SYS_DV_NOR_BOOT_CFG word. This new
commit fixes this issue by restoring the original behavior, i.e. by
defining the _start symbol before the CONFIG_SYS_DV_NOR_BOOT_CFG word.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Some boards, like mx31pdk and tx25, require the beginning of the SPL
code to be position-independent. For these two boards, this is because
they use the i.MX external NAND boot, which starts by executing the
first NAND Flash page from the NFC page buffer. The SPL then needs to
copy itself to its actual link address in order to free the NFC page
buffer and use it to load the non-SPL image from Flash before running
it. This means that the SPL runtime address differs from its link
address between the reset and the initial copy performed by
board_init_f(), so this part of the SPL binary must be
position-independent.
This requirement was broken by commit 41623c9 'arm: move exception
handling out of start.S files', which used an absolute address to branch
to the reset routine. This new commit restores the original behavior,
which just performed a relative branch. This fixes the boot of mx31pdk
and tx25.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Reported-by: Helmut Raiger <helmut.raiger@hale.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: John Rigby <jcrigby@gmail.com>
Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
Commit 224beb833e add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.
The console alias needs to be set up to indicate which port is used for
the console.
Also add a binding file since this is missing.
Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console
Signed-off-by: Simon Glass <sjg@chromium.org>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit fa9c021632 ("mx6: add example DTB for mx6qsabreauto") introduced
'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains
the 'model' and 'compatible' strings.
After this commit the final binary is also changed from 'u-boot.imx' to
'u-boot-dtb.imx', which may confuse users.
So revert it until a more complete and useful device tree could be provided.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.
Refactor the calculation.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]
Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.
[1] http://clang.llvm.org/docs/UsersManual.html
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Just before calling board_init_f, crt0.S has already
reserved space for the initial gd on the stack. There
should be no need to allocate it again.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
RPLL is needed to drive the LCD panel on Exynos5420 based boards.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This config is valid for two devices:
- Odroid X2,
- Odroid U3.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This is a standard description for Odroid boards.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On an Odroid U3 board, the SOC is unable to reset the eMMC card
in the DWMMC mode by the cpu software reset. Manual reset of the card
by switching proper gpio pin - fixes this issue.
Such solution needs to add a call to pre reset function.
This is done by the reset_misc() function, which is called before reset_cpu().
The function reset_misc() is a weak function.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Changes v4:
- arch/arm/reset: fix weak function attribute to proper style
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This change fixes the bad gpio configuration for the exynos dwmmc.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Beomho Seo <beomho.seo@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but
by mistake, here is used shift instead of mask, so correct it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The QS Systems TQMa6 board support was added by commit cb07d74e
and lost by commit e82abaeb.
Commit e82abaeb merged the IMX branch based on pre-Kconfig
and the mainline based on post-Kconfig, simply deleting
the boards.cfg file. As a result, some boards added just before
the merge were lost.
This commit adds Kconfig, defconfig, MAINTAINERS for TQMa6 board
to work on the Kconfig infrastructure.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Nomadik board select menu to nomadik/Kconfig.
Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="nomadik").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Orion5x board select menu to orion5x/Kconfig.
Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="orion5x").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Keystone board select menu to keystone/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="keystone").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP5 board select menu to omap5/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap5").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP4 board select menu to omap4/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap4").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP3 board select menu to omap3/Kconfig.
Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap3
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Davinci board select menu to davinci/Kconfig.
Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="davinci").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the KirkWood board select menu to kirkwood/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="kirkwood").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Prafulla Wadasdkar <prafulla@marvell.com>
Cc: Luka Perkov <luka@openwrt.org>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Rmobile board select menu to rmobile/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="rmobile").
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.
Insert the Tegra SoC select menu between the arch select and the
board select.
Architecture select
|-- Tegra Platform (Tegra)
|- Tegra SoC select (Tegra20 / 30 / 114 / 124)
|- Board select
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:
config TEGRA
bool
select SPL
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Zynq board select menu to zynq/Kconfig.
Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="zynq").
Refactor board/xilinx/zynq/MAINTAINERS too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
The Documentation/arm64/booting.txt document says that pass in x1/x2/x3
as 0 as they are reserved for future use.
Signed-off-by: Tom Rini <trini@ti.com>
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.
The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.
Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
However ep9315 don't use
interrupt vectors during startup, but _startup symbol is used inside uboot to
calculate actual monitor size.
Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.
Signed-off-by: Pavel Machek <pavel@denx.de>
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match hardware.
Signed-off-by: Pavel Machek <pavel@denx.de>
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so it is safe enough to enable gpio
on all DRA7 boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
And also set appropriate SYSBOOT configurations:
SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */
SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */
SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */
SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */
Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.
Tom suggested to remove this board.
Remove also omap1510_udc.c because this is the last board
to enable it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
Add support for one FEC port initially.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
style happened, so convert it now so that it can build again.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.
Signed-off-by: Marek Vasut <marex@denx.de>
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
Do not specify own zynq specific SPL macros
because there is no need for that.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This adds board support for the Toradex Colibri T30 module.
Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In at least Tegra124, the Tegra memory controller (MC) has a register
that controls the memory size. Read this to determine the memory size
rather than requiring this to be redundantly encoded into the ODMDATA.
This way, changes to the BCT (i.e. MC configuration) automatically
updated SW's view of the memory size, without requiring manual changes
to the ODMDATA.
Future work potentially required:
* Clip the memory size to architectural limits; U-Boot probably doesn't
and won't support either LPAE or Tegra's "swiss cheese" memory layout,
at least one of which would be required for >2GB RAM.
* Subtract out any carveout required by firmware on future SoCs.
Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed. For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed).
This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
aristainetos board was merged in u-boot-imx before
Kconfig was integrated, but it is not yet
mainline.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
In the case if the 'dram_para' struct does not specify the exact bus
width or chip density, just use a trial and error method to find a
usable configuration.
Because all the major bugs in the DRAM initialization sequence are
now hopefully fixed, it should be safe to re-initialize the DRAM
controller multiple times until we get it configured right. The
original Allwinner's boot0 bootloader also used a similar
autodetection trick.
The DDR3 spec contains the package pinout and addressing table for
different possible chip densities. It appears to be impossible to
distinguish between a single chip with 16 I/O data lines and a pair
of chips with 8 I/O data lines in the case if they provide the same
storage capacity. Because a single 16-bit chip has a higher density
than a pair of equivalent 8-bit chips, it has stricter refresh timings.
So in the case of doubt, we assume that 16-bit chips are used.
Additionally, only Allwinner A20 has all A0-A15 address lines and
can support densities up to 8192. The older Allwinner A10 and
Allwinner A13 can only support densities up to 4096.
We deliberately leave out DDR2, dual-rank configurations and the
special case of a 8-bit chip with density 8192. None of these
configurations seem to have been ever used in real devices. And no
new devices are likely to use these exotic configurations (because
only up to 2GB of RAM can be populated in any case).
This DRAM autodetection feature potentially allows to have a single
low performance fail-safe DDR3 initialiazation for a universal single
bootloader binary, which can be compatible with all Allwinner
A10/A13/A20 based devices (if the ifdefs are replaced with a runtime
SoC type detection).
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such hardware actually exists.
As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.
So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.
Also we allow to enable the active DQS gating window mode, which
works better than the passive mode in practice. The DDR3 spec
says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
The DQS window has to be opened during preamble and closed during
postamble. In the passive window mode, the gating window is opened
and closed by just using the gating delay settings. And because
of the 1/4 cycle delay granularity, accurately hitting the 0.3
cycle long postamble is a bit tough. In the active window mode,
the gating window is auto-closing with the help of monitoring
the DQS line, which relaxes the gating delay accuracy requirements.
But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors ("found no result" and "found more than one
possible result"). Both are handled now.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This configures the PLL5P clock frequency to something in the ballpark
of 1GHz and allows more choices for MBUS and G2D clock frequency
selection (using their own divisors). In particular, it enables the use
of 2/3 clock speed ratio between MBUS and DRAM.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
speed. Allwinner A13 uses only 16-bit data bus width to connect the
external DRAM, which is halved compared to the 32-bit data bus of sun4i
(Allwinner A10), so it does not make much sense to clock a wider
internal bus at a very high speed. The Allwinner A13 manual specifies
300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer
sun7i hardware (Allwinner A20) has a full width 32-bit external memory
interface again, but still keeps the MBUS clock speed configurable.
Clocking MBUS too low inhibits memory performance and one has to find
the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors:
http://linux-sunxi.org/A10_DRAM_Controller_Performance
This patch introduces a new 'mbus_clock' parameter for the 'dram_para'
struct and uses it as a desired MBUS clock speed target. If 'mbus_clock'
is not set, 300 MHz is used by default to match the older hardcoded
settings.
PLL5P and PLL6 are both evaluated as possible clock sources. Preferring
the one, which can provide higher clock frequency that is lower or
equal to the 'mbus_clock' target. In the case of a tie, PLL5P has
higher priority.
Attempting to set the MBUS clock speed has no effect on sun4i, but does
no harm either.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:
http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0
The new code supports both of the impedance configuration modes:
- If the higher bits of the 'zq' parameter in the 'dram_para' struct
are zero, then the lowest 8 bits are used as the ZPROG value, where
two divisors encoded in lower and higher 4 bits. One divisor is
used for calibrating the termination impedance, and another is used
for the output impedance.
- If bits 27:8 in the 'zq' parameters are non-zero, then they are
used as the pre-defined ZDATA value instead of performing the ZQ
calibration.
Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We can safely remove it, because none of the currently supported
boards uses these features.
The existing implementation had multiple problems:
- unnecessary code duplication between sun4i/sun5i/sun7i
- ZQ calibration was never initiated explicitly, and could be
only triggered by setting the highest bit in the 'zq' parameter
in the 'dram_para' struct (this was never actually done for
any of the known Allwinner devices).
- even if the ZQ calibration could be started, no attempts were
made to wait for its completion, or checking whether the
default automatically initiated ZQ calibration is still
in progress
- ODT was only ever enabled on sun4i, but not on sun5i/sun7i
Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.
The impedance and ODT configuration code will be re-introdeced in
one of the next comits.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.
The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i hardware (even the default register value
0x00c80064 is identical). Except that the counter is ticking a bit
slower on sun7i (3 DRAM clock cycles instead of 2), resulting in
longer actual delays for the same settings.
This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i
SoC variants and not just for sun7i alone. Also an explicit udelay(500)
is added immediately after DDR3 reset for extra safety. This is a
duplicated functionality. But since we don't have perfect documentation,
it may be reasonable to play safe. Half a millisecond boot time increase
is not that significant. Boot time can be always optimized later.
Preferebly by the people, who have the hardware equipment to check the
actual signals on the RESET and CKE lines and verify all the timings.
The old code did not configure the SDR_IDCR register for sun4i/sun5i,
but performed the DDR3 reset very early for sun4i/sun5i. This resulted
in a larger time gap between the DDR3 reset and the DDR3 initialization
steps and reduced the chances of CKE delay timing violation to cause
real troubles.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.
This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
this means that DRAM is currently in self-refresh mode and retaining the
old data. Since we have no idea what to do in this situation yet, just
set this register to 0 and initialize DRAM in the same way as on any
normal reboot (discarding whatever was stored there).
This part of code was apparently used by the Allwinner boot0 bootloader
to handle resume from the so-called super-standby mode. But this
particular code got somehow mangled on the way from the boot0 bootloader
to the u-boot-sunxi bootloader and has no chance of doing anything even
remotely sane. For example:
1. in the original boot0 code we had "mctl_write_w(SDR_DPCR,
0x16510000)" (write to the register) and in the u-boot it now looks
like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the
register)
2. in the original boot0 code it was issuing three commands "0x12, 0x17,
0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry,
Self-Refresh entry, Refresh)
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of this implementation is that the DQS gating window can be
successfully found for almost every DLL delay adjustment setup that
gets tried. Thus making it unable to see any real difference between
'good' and 'bad' settings.
Also this code was supposed to be only activated by setting the highest
bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board
dram configuration). But none of the linux-sunxi devices has ever used
it for real. Basically, this code is just a dead weight.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Remove the duplicated argument to | in two places. Reported
by Coccinelle (http://coccinelle.lip6.fr/).
Signed-off-by: Maxin B. John <maxin.john@enea.com>
The vectors section contains the _start symbol which is used as the
program entry point. Add it to the linker script in same fashion as done
for regular u-boot. This allows for correct generation of an spl elf
with a non-zero entry point.
A similar change was applied to sunxi platform in
"sunxi: Fix u-boot-spl.lds to refer to .vectors"
(sha1: 9e5f80d823)
This also allows for placement of the vector table at the hivecs
location by setting the TEXT_BASE to 0xffff0000.
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of
register CCM_CIMR corresponds to bit 19 so fix its definition accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
According to the Reference Manual the 'wb_per_at_lpm' field of register
CCM_CLPCR corresponds to bit 16 so fix its definition accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
