Ye.Li 4aa7ac30a7 iMX6: Disable the L2 before chaning the PL310 latency ... The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>		2014-09-09 16:30:40 +02:00
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cpu	iMX6: Disable the L2 before chaning the PL310 latency	2014-09-09 16:30:40 +02:00
dts	ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chip	2014-09-05 20:37:07 +09:00
imx-common	ARM: mx6: Prevent overflow in DRAM size detection	2014-08-20 12:21:57 +02:00
include/asm	arm: mx6: add get_cpu_type()	2014-09-09 15:35:00 +02:00
lib	arm:reset: call the reset_misc() before the cpu reset	2014-09-05 13:58:49 +09:00
config.mk	kconfig: delete redundant CONFIG_${ARCH} definition	2014-07-30 14:42:02 -04:00
Kconfig	arm: mx6: add support for Compulab cm-fx6 CoM	2014-09-09 15:35:43 +02:00