Siarhei Siamashka 013f2d7469 sunxi: dram: Use divisor P=1 for PLL5 ... This configures the PLL5P clock frequency to something in the ballpark of 1GHz and allows more choices for MBUS and G2D clock frequency selection (using their own divisors). In particular, it enables the use of 2/3 clock speed ratio between MBUS and DRAM. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>		2014-08-12 08:42:33 +02:00
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cpu	sunxi: dram: Use divisor P=1 for PLL5	2014-08-12 08:42:33 +02:00
dts	Merge remote-tracking branch 'u-boot-samsung/master'	2014-07-01 20:52:51 +02:00
imx-common	Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'	2014-06-30 23:00:34 +02:00
include/asm	sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)	2014-08-12 08:42:33 +02:00
lib	arm: Support pre-relocation malloc()	2014-08-04 05:24:35 -06:00
config.mk	kconfig: delete redundant CONFIG_${ARCH} definition	2014-07-30 14:42:02 -04:00
Kconfig	kconfig: add board Kconfig and defconfig files	2014-07-30 08:48:01 -04:00