The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: expanded commit message]
[wens@csie.org: add pin bank M and expand comments]
[wens@csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used
with a micro SD breakout board. On the A23, this is the only way to
use uart0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The watchdog on sun6i/sun8i has a different layout.
Add the new layout and fix up the setup functions so that reset works.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.
Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.
Move the register definitions to a separate file to facilitate
supporting newer SoCs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.
When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a new sun6i machine that supports UART and MMC.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
[wens@csie.org: reorder #ifs by SUN?I]
[wens@csie.org: replace magic numbers with GPIO definitions]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
This includes changes from the following commits from u-boot-sunxi:
a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.
This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We have already defined macros for pull-up/down values in the
GPIO header. Use them instead of magic numbers when configuring
the UART pins.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86.
Those architectures should "select" HAVE_PRIVATE_LIBGCC and
CONFIG_USE_PRIVATE_LIBGCC should depend on it.
Currently, this option is enabled on Tegra boards and x86 architecture.
Move the definition from header files to Kconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic support for the Marvell DB-MV784MP-GP evaulation
board. This is the first board that uses the recently created
Armada XP 78460 SoC support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
This basic support for the Marvell Armada XP is base on the existing kirkwood
support. Which has been generatized by moving some common files into
common marvell locations.
This is in preparation for the upcoming Armada XP MV78460 support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Additionally the SDRAM address decoding register address is not hard coded
in the C code any more. A define is introduced for this base address.
This makes is possible to use those gpio functions from other MVEBU SoC's
as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This makes is possible to use this SPI driver from other MVEBU SoC's as well.
As the upcoming Armada XP support will do.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This makes is possible to use those gpio functions from other MVEBU SoC's as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
These mbus functions are ported from Barebox. The Barebox version is
ported from Linux. These functions will be first used by the upcoming
Armada XP support. Later other Marvell SoC's will be adopted to use
these functions as well (Kirkwood, Orion).
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
This patch does the following:
- Rename defines and registers to not use kirkwood
- Remove unused defines
- Use clrsetbits() accessor functions
- Coding style cleanup
- Clear 25MHZ bit in timer controller register init for Armada XP
There is no functional change for kirkwood. At least not intentionally.
This will be used by the upcoming Armada XP support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This move makes it possible to use this kirkwood SPI driver from other
MVEBU platforms as well. This will be used by the upcoming Armada XP
support.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
By moving some kirkwood files into a Marvell common directory, those files
can be used by other Marvell platforms as well. The name mvebu is taken
from the Linux kernel source tree. It has been chosen there to represent
the SoC's from the Marvell EBU (Engineering Business Unit). Those SoC's
currently are:
Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x
This will be used by the upcoming Armada XP (MV78460) platform support.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Convert the BCM2835 GPIO driver to use driver model, and switch over
Raspberry Pi to use this, since it is the only board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
GPIOs should be requested before use. Without this, driver model will
not permit the GPIO to be used.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This converts the Tegra SPI drivers to use driver model. This is tested
on:
- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore
(not tested on Tegra124)
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
All boards with a SPI interface have a suitable spi alias except the tegra30
boards. Add these missing aliases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Adjust this board to use the driver model soft_spi implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.
A few device tree additions are needed to make the SPI flash available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Convert the exynos GPIO driver to driver model. This implements the generic
GPIO interface but not the extra Exynos-specific functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
With driver model GPIOs must be requested before use. Make sure this is
done correctly.
(Note that the soft SPI part of universal is omitted, since this driver
is about to be replaced with a driver-model-aware version)
Signed-off-by: Simon Glass <sjg@chromium.org>
The wrong header is being included, thus requiring the code to re-declare
the generic GPIO interface in each GPIO header.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
The pinctrl bindings used by Linux are an incomplete description of the
hardware. It is possible in most cases to determine the register address
of each, but not in all cases. By adding an additional property we can
fix this, and avoid adding a table to U-Boot for every single Exynos
SOC.
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't include the pinctrl functions for U-Boot as they use up quite
a bit of space and are not used.
We could instead perhaps eliminate this material with fdtgrep, but so far
this tool has not made it to upstream.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bring in required device tree files for pinctrl from Linux v3.14. These
are initially unchanged and have a number of pieces not needed by U-Boot.
Note that exynos5420 is renamed to exynos54xx here since we want to
support exynos5422 also.
Signed-off-by: Simon Glass <sjg@chromium.org>
