Commit Graph

12037 Commits

Author SHA1 Message Date
Ley Foon Tan
594cacf063 arm: socfpga: agilex: Add SPL for Agilex SoC
Add SPL support for Agilex SoC.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
a6e5b06bea arm: agilex: Add clock handoff offset for Agilex
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
b4a20cb300 arm: socfpga: agilex: Add clock wrapper functions
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
c168fc71a3 clk: agilex: Add clock driver for Agilex
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
20322cea64 arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
38229994af arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
975f66bb57 arm: socfpga: agilex: Add system manager support
Add system manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
2fd1dc5593 arm: socfpga: Move Stratix10 and Agilex system manager common code
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
50278d4ade arm: socfpga: agilex: Add reset manager support
Add reset manager support for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
fd5374aa29 arm: socfpga: Move Stratix10 and Agilex reset manager common code
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.

Remove unused RSTMGR_XXX defines.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
8b7962a349 arm: socfpga: Move firewall code to firewall file
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.

SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
2145e611fc arm: socfpga: agilex: Add base address for Intel Agilex SoC
Add base address for Intel Agilex SoC.

Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
94172c7961 arm: socfpga: Convert clock manager from struct to defines
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
db5741f7a8 arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
bb25aca134 arm: socfpga: Convert reset manager from struct to defines
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
dd72cbd9e9 arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Tom Rini
5a8fa095cb Merge branch 'next'
Bring in the following merges:

commit 8fbbec12f7
Merge: 87f69f467a 63618e71e8
Author: Tom Rini <trini@konsulko.com>
Date:   Fri Jan 3 09:48:47 2020 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

    - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support

commit 87f69f467a
Merge: c0912f9bbf 4466b99703
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 24 08:18:19 2019 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next

    - Enable DM driver on ppc/km boards
    - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
      T104x, P4080, P2041, P2020, P1020, P3041
    - Some updates in mpc85xx-ddr driver, km boards

commit c0912f9bbf
Merge: 533c9f5714 a1d6dc3f84
Author: Tom Rini <trini@konsulko.com>
Date:   Wed Dec 18 07:20:19 2019 -0500

    Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

    - Various x86 common codes updated for TPL/SPL
    - I2C designware driver updated for PCI
    - ICH SPI driver updated to support Apollo Lake
    - Add Intel FSP2 base support
    - Intel Apollo Lake platform specific drivers support
    - Add a new board Google Chromebook Coral

commit 533c9f5714
Merge: 553cb06887 033e18b47b
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 17 07:53:08 2019 -0500

    Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

    i2c: for next
    - misc: i2c_eeprom:
      Add partition support and add ability to query size
      of eeprom device and partitions
    - i2c common:
      add support for offset overflow in to address and add
      sandbox tests for it.

commit 553cb06887
Merge: f39abbbc53 b4f98b3b16
Author: Tom Rini <trini@konsulko.com>
Date:   Thu Dec 12 08:18:59 2019 -0500

    Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next

    buildman improvements including toolchain environment feature
    sandbox unicode support in serial
2020-01-06 17:07:49 -05:00
Lokesh Vutla
40109f4d7e arm: mach-k3: Enable WA for R5F deadlock
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
  cacheable write back/write allocate memory region and later
  on software execute barrier operation (DSB or DMB). R5F may
  hang at the barrier instruction.
2.When software is performing a mix of load and store operations
  within a tight loop and store operations are all writing to
  cacheable write back/write allocates memory regions, R5F may
  hang at one of the load instruction.

To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-03 09:47:11 -05:00
Lokesh Vutla
196d3e4017 arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
2020-01-03 09:47:10 -05:00
Tom Rini
28aa6dc29a Merge tag 'u-boot-rockchip-20191231' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix latest mainline kernel for rk3308
- Update rk3288-evb config to suport OP-TEE
- Fix for firefly-px30 DEBUG_UART channel and make it standalone
- Script make_fit_atf add python3 support
- Fix rk3328 timer with correct COUNTER_FREQUENCY
- Fix rk3328 ATF support with enable spl-fifo-mode
2020-01-02 10:28:26 -05:00
Robert P. J. Day
e852b30b23 arch/arm/Kconfig: typo/grammar/punctuation fixes
Various (mostly minor) spelling, grammar and punctuation tweaks for
arch/arm/Kconfig.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2020-01-02 10:27:23 -05:00
Pankaj Bansal
ba7c966c0f pci: layerscape: move PCIE related CONFIG to PCI Kconfig
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02 14:36:57 +05:30
Kever Yang
fa2047c473 rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc
Since mmc to sram can't do dma, add patch to prevent aborts transfering
TF-A parts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-31 15:57:55 +08:00
Tom Rini
6cb87cbb14 Fixes for 2020.01
-----------------
 - Fixes for Nitrogen6x
 - Fix corruption for mx51evk
 - colibri i.MX6: fix broken ESDHC conversion
 - mx6sxsabresd: fix broken mmcdev
 - imx6q_logic: cleanup boot sequence
 - update ATF for imx8mq_evk
 - pfuze: fix pmic_get()
 
 Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
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Merge tag 'u-boot-imx-20191228' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------
- Fixes for Nitrogen6x
- Fix corruption for mx51evk
- colibri i.MX6: fix broken ESDHC conversion
- mx6sxsabresd: fix broken mmcdev
- imx6q_logic: cleanup boot sequence
- update ATF for imx8mq_evk
- pfuze: fix pmic_get()

Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
2019-12-28 08:07:16 -05:00
Troy Kisky
61d7e2bcc7 ARM: i.MX6: TARGET_NITROGEN6X: add 'select MX6QDL'
This fixes commit <91435cd40d30> "ARM: i.MX6: exclude the ARM errata
 from i.MX6 UP system"

for nitrogen6x. The above commit removed the errata for the board
since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS

This restores the errata configs.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-12-27 14:28:42 +01:00
Jorge Ramirez-Ortiz
e97bdfa5da tools/imximage: share DCD information via Kconfig
IMX based platforms can have the DCD table located on different
addresses due to differences in their memory maps (ie iMX7ULP).

This information is required by the user to sign the images for secure
boot so continue making it accessible via mkimage.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2019-12-27 12:55:59 +01:00
Thomas Hebb
d4e4187b8c rockchip: add description for TPL_ROCKCHIP_COMMON_BOARD
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but
this one doesn't for some reason. Add a description to make the menu
easier to read.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27 14:26:13 +08:00
Kever Yang
3176d47d35 rockchip: px30-firefly add standalone dts
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot
proper will use the dts setting to do the IOMUX init, and a separate dts
is needed for px30-firefly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27 14:26:13 +08:00
Jack Mitchell
6d06ea3423 rockchip: make_fit_atf: explicitly use python3
On a distribution with no python2 installed and no
python->python3 symlink the script will fail to execute.
Specify python3 explicitly as it's already a requirement
to build u-boot.

Signed-off-by: Jack Mitchell <ml@embed.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27 14:26:13 +08:00
Kever Yang
7c337710fc rockchip: fit_spl_optee: get text and optee base from build
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x60000000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26 20:34:28 +08:00
Wasim Khan
7cd4272821 armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160A
Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM
for lx2160a.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Kuldeep Singh
ce3bead608 fsl-lsch3: soc: Enable AHB read support for Flexspi controller
Enable AHB support for Flexspi controller interface meaning
memory can be accessed via md command using absolute addresses

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Kuldeep Singh
0b6c3706ab fsl-lsch3: Add FlexSPI address space in immap_lsch3
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2019-12-26 16:00:20 +05:30
Alex Marginean
3499dd033c ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Vabhav Sharma
c1ead04bc4 arm64: lx2160a: dts: Fix UART node status
LX2160A PL011 UART driver fetch IP block values using
platform data from board file instead of device tree.

Modified UART nodes in device tree to disable state.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Ran Wang
0cfa00cdb9 armv8: Add workaround for USB erratum A-050106
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Michael Walle
055aa33ff9 armv8: layerscape: fix SPL multi DTB loading
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Heinrich Schuchardt
421e7a41c6 sunxi: remove __packed from struct sunxi_prcm_reg
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:

  CC      arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
  163 |  sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
      |                     ^~~~~~~~~~~~~~~~~~~~~~~~~

Remove __packed attribute from struct sunxi_prcm_reg.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-18 20:19:58 +05:30
Diego Rondini
e7c15b7ab8 sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2
Orangepi Zero Plus 2 is an open-source single-board computer, available
in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
here, as the H5 is already supported.

H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply

Sync dts from linux v5.2 commit:
"ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry"
(sha1: 75f9a058838be9880afd75c4cb14e1bf4fe34a0b)
Commit:
"ARM: dts: sun8i: h3: Refactor the pinctrl node names"
(sha1: a4dc791974e568a15f7f37131729b1a6912f4811)
has been avoided as it breaks U-Boot build.

Signed-off-by: Diego Rondini <diego.rondini@kynetics.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18 20:14:16 +05:30
Heinrich Schuchardt
9bd34a69a4 sunxi: psci: avoid error address-of-packed-member
Compiling with GCC 9.2.1 leads to build errors:

arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
  144 |  sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
      |                     ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
  144 |  sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
      |                                              ^~~~~~~~~~~~~~~~~~~~

Use memcpy() and void* pointers to resolve the problem caused by packing
the struct sunxi_cpucfg_reg.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18 20:13:34 +05:30
Patrick Delaunay
16fec9b0bc stm32mp1: remove the imply BOOTSTAGE
This patch is only a temporarily workaround for crash introduced by
commit ac9cd4805c ("bootstage: Correct relocation algorithm").

The crash occurs because the bootstage struct is not correctly aligned
when BOOTSTAGE feature is activated.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18 11:58:36 +01:00
Patrick Delaunay
eee15806fc stm32mp1: imply CMD_CLS
Activate by default the command CLS (clear screen);
this command used in pxe or sysboot command (DISTRO support)
when the "menu background" keyword is present.

This patch avoid the warning "Unknown command 'cls'"
with extlinux.conf:

# Generic Distro Configuration file generated by OpenEmbedded
menu title Select the boot mode
MENU BACKGROUND /splash.bmp
TIMEOUT 20
DEFAULT stm32mp157c-ev1-emmc
LABEL stm32mp157c-ev1-emmc
	KERNEL /uImage
	FDT /stm32mp157c-ev1.dtb
	APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200

  ...
  Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf
  614 bytes read in 36 ms (16.6 KiB/s)
  Retrieving file: /splash.bmp
  46180 bytes read in 40 ms (1.1 MiB/s)
  Unknown command 'cls' - try 'help'
  Select the boot mode
  1:	stm32mp157c-ev1-sdcard
  ...

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18 11:52:35 +01:00
Simon Glass
bcee8d6764 dm: gpio: Allow control of GPIO uclass in SPL
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Hannes Schmelzer
05767707a8 dts: am335x-brsmarc1/xre1: insert phy_id again
commit 3b3e8a37d3
("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id")

did sync with recent linux kernel and replaced therefore the 'phy_id'
property with a phy-handle pointing to the mdio.

This is OK for linux, but introduces trouble with the already running
vxWorks on this target.

So this commit here re-inerts the phy_id property beside the phy-handle
property to be compatible with both.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-12-13 13:01:12 -05:00
Suman Anna
1045ff4d1a ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCs
The commit 1b42ab3eda ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.

The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-09 14:00:24 -05:00
Tom Rini
ac1ca99926 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net 2019-12-09 13:48:22 -05:00
Vignesh Raghavendra
4886f1cb59 arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes
Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Nevo Hed
06f555274e arm: dts: armada-cp110-*dtsi: add xmdio nodes
Based on upstream-linux
See https://github.com/torvalds/linux/commit/f66b2aff.

However made the XSMI register window 0x16 (22) bytes per my reading
of the functional spec.  Similar commits in Marvels own repo bump it
to 0x200 (512) bytes but I did not see the reasoning for that.

https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/4d932b4.

Also added device-name attributes to prevent ambiguity in the `mdio`
command.

Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
5efb69298b arm: dts: k3-am654-base-board-u-boot: change cpsw2g interface mode to rgmii-rxid
The AM654 SoC doesn't allow to disabling RGMII TX internal delay in CPSW2G
MAC. Hence, change CPSW2G interface mode to "rgmii-rxid" - RGMII with
internal RX delay provided by the PHY, the MAC will add an TX delay in this
case.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Joe Hershberger
fb8977c5be net: Always build the string_to_enetaddr() helper
Part of the env cleanup moved this out of the environment code and into
the net code. However, this helper is sometimes needed even when the net
stack isn't included.

Move the helper to lib/net_utils.c like it's similarly-purposed
string_to_ip(). Also rename the moved function to similar naming.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Ondrej Jirman <megous@megous.com>
2019-12-09 09:47:41 -06:00