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Fixes for 2020.01 

-----------------
 - Fixes for Nitrogen6x
 - Fix corruption for mx51evk
 - colibri i.MX6: fix broken ESDHC conversion
 - mx6sxsabresd: fix broken mmcdev
 - imx6q_logic: cleanup boot sequence
 - update ATF for imx8mq_evk
 - pfuze: fix pmic_get()
 
 Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
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Merge tag 'u-boot-imx-20191228' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------
- Fixes for Nitrogen6x
- Fix corruption for mx51evk
- colibri i.MX6: fix broken ESDHC conversion
- mx6sxsabresd: fix broken mmcdev
- imx6q_logic: cleanup boot sequence
- update ATF for imx8mq_evk
- pfuze: fix pmic_get()

Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
This commit is contained in:
Tom Rini 2019-12-28 08:07:16 -05:00
parent 831f06fe9a fff7b33ce5
commit 6cb87cbb14
17 changed files with 279 additions and 209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/mach-imx/Kconfig
View File

@ -113,3 +113,14 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
depends on IMX8MN
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
default 0x00910000 if !ARCH_MX7ULP
default 0x2f010000 if ARCH_MX7ULP
help
Indicates where the Device Configuration Data, a binary table used by
the ROM code to configure the device at early boot stage, is located.
This information is shared with the user via mkimage -l just so the
image can be signed.

1
arch/arm/mach-imx/mx6/Kconfig
View File

@ -424,6 +424,7 @@ config TARGET_NITROGEN6X
imply USB_ETHER_MCS7830
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
select MX6QDL
config TARGET_OPOS6ULDEV
bool "Armadeus OPOS6ULDev board"

370
board/boundary/nitrogen6x/nitrogen6x.c
View File

@ -57,6 +57,8 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_SLOW)
@ -67,6 +69,56 @@ DECLARE_GLOBAL_DATA_PTR;
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
/* Prevent compiler error if gpio number 08 or 09 is used */
#define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
#define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) { \
.scl = { \
.i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
pad_ctrl), \
.gpio_mode = NEW_PAD_CTRL( \
cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
pad_ctrl), \
.gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp)) \
}, \
.sda = { \
.i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
pad_ctrl), \
.gpio_mode = NEW_PAD_CTRL( \
cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
pad_ctrl), \
.gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp)) \
} \
}
#define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl) \
_I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
#if defined(CONFIG_MX6QDL)
#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl) \
I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl), \
I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl)
#define I2C_PADS_INFO_ENTRY_SPACING 2
#define IOMUX_PAD_CTRL(name, pad_ctrl) \
NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl), \
NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
#else
#define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl) \
I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp, \
sda_pad, sda_bank, sda_gp, pad_ctrl)
#define I2C_PADS_INFO_ENTRY_SPACING 1
#define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
#endif
int dram_init(void)
{
gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
@ -75,140 +127,105 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1, SGTL5000 */
static struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
static struct i2c_pads_info i2c_pads[] = {
/* I2C1, SGTL5000 */
I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
/* I2C2 Camera, MIPI */
I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
I2C_PAD_CTRL),
/* I2C3, J15 - RGB connector */
I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
};
/* I2C2 Camera, MIPI */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3, J15 - RGB connector */
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
#define I2C_BUS_CNT 3
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
};
static iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const misc_pads[] = {
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
/* OTG Power enable */
MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
};
/* wl1271 pads on nitrogen6x */
static iomux_v3_cfg_t const wl12xx_pads[] = {
(MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(WEAK_PULLDOWN),
(MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(OUTPUT_40OHM),
(MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
| MUX_PAD_CTRL(OUTPUT_40OHM),
IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
@ -217,17 +234,17 @@ static iomux_v3_cfg_t const wl12xx_pads[] = {
/* Button assignments for J14 */
static iomux_v3_cfg_t const button_pads[] = {
/* Menu */
MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
/* Back */
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
/* Labelled Search (mapped to Power under Android) */
MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
/* Home */
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
/* Volume Down */
MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
/* Volume Up */
MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
};
static void setup_iomux_enet(void)
@ -239,7 +256,7 @@ static void setup_iomux_enet(void)
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
SETUP_IOMUX_PADS(enet_pads1);
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
@ -247,24 +264,24 @@ static void setup_iomux_enet(void)
gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
SETUP_IOMUX_PADS(enet_pads2);
udelay(100); /* Wait 100 us before using mii interface */
}
static iomux_v3_cfg_t const usb_pads[] = {
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
SETUP_IOMUX_PADS(uart1_pads);
SETUP_IOMUX_PADS(uart2_pads);
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
SETUP_IOMUX_PADS(usb_pads);
/* Reset USB hub */
gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
@ -314,12 +331,10 @@ int board_mmc_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
SETUP_IOMUX_PADS(usdhc3_pads);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
SETUP_IOMUX_PADS(usdhc4_pads);
break;
default:
printf("Warning: you configured more USDHC controllers"
@ -345,16 +360,15 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
static iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
};
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
SETUP_IOMUX_PADS(ecspi1_pads);
}
#endif
@ -424,52 +438,51 @@ free_bus:
static void setup_buttons(void)
{
imx_iomux_v3_setup_multiple_pads(button_pads,
ARRAY_SIZE(button_pads));
SETUP_IOMUX_PADS(button_pads);
}
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
MX6_PAD_DI0_PIN4__GPIO4_IO20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
};
static void do_enable_hdmi(struct display_info_t const *dev)
@ -507,9 +520,7 @@ static void enable_lvds_jeida(struct display_info_t const *dev)
static void enable_rgb(struct display_info_t const *dev)
{
imx_iomux_v3_setup_multiple_pads(
rgb_pads,
ARRAY_SIZE(rgb_pads));
SETUP_IOMUX_PADS(rgb_pads);
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
@ -810,8 +821,7 @@ static void setup_display(void)
writel(reg, &iomux->gpr[3]);
/* backlights off until needed */
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
SETUP_IOMUX_PADS(backlight_pads);
gpio_direction_input(LVDS_BACKLIGHT_GP);
gpio_direction_input(RGB_BACKLIGHT_GP);
}
@ -819,24 +829,24 @@ static void setup_display(void)
static iomux_v3_cfg_t const init_pads[] = {
/* SGTL5000 sys_mclk */
NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
/* J5 - Camera MCLK */
NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
/* wl1271 pads on nitrogen6x */
/* WL12XX_WL_IRQ_GP */
NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
/* WL12XX_WL_ENABLE_GP */
NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
/* WL12XX_BT_ENABLE_GP */
NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
/* USB otg power */
NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
};
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
@ -871,8 +881,8 @@ int board_early_init_f(void)
set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
gpio_direction_input(WL12XX_WL_IRQ_GP);
imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
SETUP_IOMUX_PADS(wl12xx_pads);
SETUP_IOMUX_PADS(init_pads);
setup_buttons();
#if defined(CONFIG_VIDEO_IPUV3)
@ -893,12 +903,20 @@ int overwrite_console(void)
int board_init(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct i2c_pads_info *p = i2c_pads;
int i;
int stride = 1;
#if defined(CONFIG_MX6QDL)
stride = 2;
if (!is_mx6dq() && !is_mx6dqp())
p += 1;
#endif
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
IOMUXC_GPR1_OTG_ID_GPIO1);
imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
SETUP_IOMUX_PADS(misc_pads);
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
@ -906,11 +924,11 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
SETUP_IOMUX_PADS(usdhc2_pads);
for (i = 0; i < I2C_BUS_CNT; i++) {
setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
p += stride;
}
#ifdef CONFIG_SATA
setup_sata();

2
board/freescale/common/pfuze.c
View File

@ -136,7 +136,7 @@ struct udevice *pfuze_common_init(void)
int ret;
unsigned int reg, dev_id, rev_id;
ret = pmic_get("pfuze100", &dev);
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return NULL;

2
board/freescale/imx8mq_evk/README
View File

@ -11,7 +11,7 @@ Get and Build the ARM Trusted firmware
======================================
Note: srctree is U-Boot source directory
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
branch: imx_4.14.62_1.0.0_beta
branch: imx_4.19.35_1.0.0
$ make PLAT=imx8mq bl31
$ cp build/imx8mq/release/bl31.bin $(srctree)

54
board/logicpd/imx6/imx6logic.c
View File

@ -156,29 +156,49 @@ void board_boot_order(u32 *spl_boot_list)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1-SOM
* 0x2 SD2-Baseboard
*/
u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
unsigned int bmode = readl(&src_base->sbmr2);
reg &= 0x3; /* Only care about bottom 2 bits */
switch (reg) {
case 0:
spl_boot_list[0] = BOOT_DEVICE_MMC1;
/* If bmode is serial or USB phy is active, return serial */
if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
spl_boot_list[0] = BOOT_DEVICE_BOARD;
return;
}
switch (boot_mode >> IMX6_BMODE_SHIFT) {
case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
spl_boot_list[0] = BOOT_DEVICE_NAND;
break;
case 1:
spl_boot_list[0] = BOOT_DEVICE_MMC2;
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1-SOM
* 0x2 SD2-Baseboard
*/
reg &= 0x3; /* Only care about bottom 2 bits */
switch (reg) {
case 0:
spl_boot_list[0] = BOOT_DEVICE_MMC1;
break;
case 1:
spl_boot_list[0] = BOOT_DEVICE_MMC2;
break;
}
break;
default:
/* By default use USB downloader */
spl_boot_list[0] = BOOT_DEVICE_BOARD;
break;
}
/* If we cannot find a valid MMC/SD card, try NAND */
spl_boot_list[1] = BOOT_DEVICE_NAND;
/* As a last resort, use serial downloader */
spl_boot_list[2] = BOOT_DEVICE_BOARD;
spl_boot_list[1] = BOOT_DEVICE_BOARD;
}
static void ccgr_init(void)

4
board/toradex/colibri_imx6/colibri_imx6.c
View File

@ -83,7 +83,7 @@ iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* Colibri MMC */
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@ -304,7 +304,7 @@ int board_ehci_hcd_init(int port)
}
#endif
#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC */
struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},

2
configs/mx51evk_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x97800000
CONFIG_TARGET_MX51EVK=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"

6
drivers/ddr/imx/imx8m/ddr_init.c
View File

@ -24,7 +24,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp, initial_drate, target_freq;
printf("DDRINFO: start DRAM init\n");
debug("DDRINFO: start DRAM init\n");
/* Step1: Follow the power up procedure */
if (is_imx8mq()) {
@ -109,7 +109,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
tmp = reg32_read(DDRPHY_CalBusy(0));
} while ((tmp & 0x1));
printf("DDRINFO:ddrphy calibration done\n");
debug("DDRINFO:ddrphy calibration done\n");
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
@ -161,7 +161,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
/* enable port 0 */
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
printf("DDRINFO: ddrmix config done\n");
debug("DDRINFO: ddrmix config done\n");
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);

3
drivers/rtc/rx8010sj.c
View File

@ -349,7 +349,7 @@ void rtc_init(void)
static int rx8010sj_probe(struct udevice *dev)
{
rx8010sj_rtc_init(&dev);
rx8010sj_rtc_init(dev);
return 0;
}
@ -364,6 +364,7 @@ static const struct rtc_ops rx8010sj_rtc_ops = {
static const struct udevice_id rx8010sj_rtc_ids[] = {
{ .compatible = "epson,rx8010sj-rtc" },
{ .compatible = "epson,rx8010" },
{ }
};

2
drivers/rtc/s35392a.c
View File

@ -350,6 +350,8 @@ static const struct rtc_ops s35392a_rtc_ops = {
static const struct udevice_id s35392a_rtc_ids[] = {
{ .compatible = "sii,s35392a-rtc" },
{ .compatible = "sii,s35392a" },
{ .compatible = "s35392a" },
{ }
};

2
include/configs/imx8mm_evk.h
View File

@ -39,7 +39,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image.itb\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
"console=ttymxc1,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fit=try\0" \

2
include/configs/imx8mn_evk.h
View File

@ -42,7 +42,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image.itb\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
"console=ttymxc1,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fit=try\0" \

2
include/configs/imx8mq_evk.h
View File

@ -103,7 +103,7 @@
CONFIG_MFG_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image\0" \
"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
"console=ttymxc0,115200\0" \
"fdt_addr=0x43000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \

13
include/configs/mx51evk.h
View File

@ -182,6 +182,19 @@
/*-----------------------------------------------------------------------
* environment organization
*/
/*
* Environment starts at CONFIG_ENV_OFFSET=0xC0000 = 768k = 768 * 1024 = 786432
*
* Detect overlap between U-Boot image and environment area in build-time
*
* CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
* CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
*
* Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
* write the direct value here
*/
#define CONFIG_BOARD_SIZE_LIMIT 785408
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif

4
include/configs/mx6sxsabresd.h
View File

@ -54,9 +54,9 @@
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
"mmcdev=2\0" \
"mmcdev=3\0" \
"mmcpart=1\0" \
"finduuid=part uuid mmc 2:2 uuid\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \

8
tools/imximage.c
View File

@ -11,9 +11,13 @@
#include "imagetool.h"
#include <image.h>
#include "imximage.h"
#include <generated/autoconf.h>
#define UNDEFINED 0xFFFFFFFF
#if !defined(CONFIG_IMX_DCD_ADDR)
#define CONFIG_IMX_DCD_ADDR 0x00910000
#endif
/*
* Supported commands for configuration file
*/
@ -524,8 +528,8 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n",
(uint32_t)fhdr_v2->self, 0,
(uint32_t)(fhdr_v2->csf - fhdr_v2->self));
printf("DCD Blocks: 0x00910000 0x%08x 0x%08x\n",
offs, be16_to_cpu(dcdlen));
printf("DCD Blocks: 0x%08x 0x%08x 0x%08x\n",
offs, CONFIG_IMX_DCD_ADDR, be16_to_cpu(dcdlen));
}
} else {
imx_header_v2_t *next_hdr_v2;