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arm: socfpga: agilex: Add clock wrapper functions

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Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Ley Foon Tan 2019-11-27 15:55:23 +08:00 committed by Marek Vasut
parent c168fc71a3
commit b4a20cb300
4 changed files with 105 additions and 0 deletions
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4
arch/arm/mach-socfpga/Makefile
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@ -39,6 +39,10 @@ obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
endif
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o

85
arch/arm/mach-socfpga/clock_manager_agilex.c Normal file
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@ -0,0 +1,85 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*
*/
#include <clk.h>
#include <common.h>
#include <dm.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
#include <dt-bindings/clock/agilex-clock.h>
DECLARE_GLOBAL_DATA_PTR;
static ulong cm_get_rate_dm(u32 id)
{
struct udevice *dev;
struct clk clk;
ulong rate;
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(socfpga_agilex_clk),
&dev);
if (ret)
return 0;
clk.id = id;
ret = clk_request(dev, &clk);
if (ret < 0)
return 0;
rate = clk_get_rate(&clk);
clk_free(&clk);
if ((rate == (unsigned long)-ENOSYS) ||
(rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
return 0;
}
return rate;
}
static u32 cm_get_rate_dm_khz(u32 id)
{
return cm_get_rate_dm(id) / 1000;
}
unsigned long cm_get_mpu_clk_hz(void)
{
return cm_get_rate_dm(AGILEX_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
}
u32 cm_get_qspi_controller_clk_hz(void)
{
return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
cm_get_rate_dm_khz(AGILEX_MPU_CLK));
printf("L4 Main %8d kHz\n",
cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
}

2
arch/arm/mach-socfpga/include/mach/clock_manager.h
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@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void);
#include <asm/arch/clock_manager_arria10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include <asm/arch/clock_manager_s10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include <asm/arch/clock_manager_agilex.h>
#endif
#endif /* _CLOCK_MANAGER_H_ */

14
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h Normal file
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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*/
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
unsigned long cm_get_mpu_clk_hz(void);
#include <asm/arch/clock_manager_soc64.h>
#include "../../../../../drivers/clk/altera/clk-agilex.h"
#endif /* _CLOCK_MANAGER_AGILEX_ */