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clk: agilex: Add clock driver for Agilex
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
20322cea64
commit
c168fc71a3
@ -245,7 +245,12 @@ void socfpga_get_managers_addr(void)
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if (ret)
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hang();
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#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
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ret = socfpga_get_base_addr("intel,agilex-clkmgr",
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&socfpga_clkmgr_base);
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#else
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ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
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#endif
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if (ret)
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hang();
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}
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@ -3,4 +3,5 @@
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# Copyright (C) 2018 Marek Vasut <marex@denx.de>
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#
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obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
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579
drivers/clk/altera/clk-agilex.c
Normal file
579
drivers/clk/altera/clk-agilex.c
Normal file
@ -0,0 +1,579 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dm/util.h>
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#include <dt-bindings/clock/agilex-clock.h>
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#include <asm/arch/clock_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct socfpga_clk_platdata {
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void __iomem *regs;
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};
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
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cm_wait_for_fsm();
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}
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static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
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cm_wait_for_fsm();
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}
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#define MEMBUS_MAINPLL 0
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#define MEMBUS_PERPLL 1
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#define MEMBUS_TIMEOUT 1000
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#define MEMBUS_ADDR_CLKSLICE 0x27
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#define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80
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static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
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int timeout)
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{
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int cnt = 0;
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u32 req_status;
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if (pll == MEMBUS_MAINPLL)
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req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
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else
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req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
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while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
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if (pll == MEMBUS_MAINPLL)
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req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
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else
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req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
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cnt++;
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}
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if (cnt >= timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
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u32 addr_offset, u32 wdat, int timeout)
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{
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u32 addr;
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u32 val;
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addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
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val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
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(wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
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if (pll == MEMBUS_MAINPLL)
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
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else
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
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debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
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return membus_wait_for_req(plat, pll, timeout);
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}
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static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
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u32 addr_offset, u32 *rdata, int timeout)
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{
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u32 addr;
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u32 val;
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addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
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val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
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if (pll == MEMBUS_MAINPLL)
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
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else
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
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*rdata = 0;
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if (membus_wait_for_req(plat, pll, timeout))
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return -ETIMEDOUT;
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if (pll == MEMBUS_MAINPLL)
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*rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
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else
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*rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
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debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
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return 0;
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}
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static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
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{
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u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
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mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
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arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
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drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
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refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
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mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
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if (!mscnt)
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mscnt = 1;
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hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
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CLKMGR_VCOCALIB_HSCNT_CONST;
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vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
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((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
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CLKMGR_VCOCALIB_MSCNT_MASK);
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/* Dump all the pll calibration settings for debug purposes */
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debug("mdiv : %d\n", mdiv);
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debug("arefclkdiv : %d\n", arefclkdiv);
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debug("drefclkdiv : %d\n", drefclkdiv);
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debug("refclkdiv : %d\n", refclkdiv);
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debug("mscnt : %d\n", mscnt);
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debug("hscnt : %d\n", hscnt);
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debug("vcocalib : 0x%08x\n", vcocalib);
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return vcocalib;
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*/
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static void clk_basic_init(struct udevice *dev,
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const struct cm_config * const cfg)
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{
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struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
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u32 vcocalib;
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u32 rdata;
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if (!cfg)
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return;
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/* Put both PLLs in bypass */
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clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
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clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
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/* Put both PLLs in Reset and Power Down */
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CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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/* setup main PLL dividers where calculate the vcocalib value */
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vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
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CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
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CLKMGR_MAINPLL_PLLGLOB);
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CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
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CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
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CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
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CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
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CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
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CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
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CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
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/* setup peripheral PLL dividers where calculate the vcocalib value */
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vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
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CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
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CLKMGR_PERPLL_PLLGLOB);
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CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
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CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
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CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
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CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
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CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
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CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
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/* Take both PLL out of reset and power up */
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CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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/* Membus programming to set mainpll and perripll to
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* source synchronous mode
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*/
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membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
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MEMBUS_TIMEOUT);
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membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,
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(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
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MEMBUS_TIMEOUT);
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membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
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MEMBUS_TIMEOUT);
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membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,
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(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
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MEMBUS_TIMEOUT);
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cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
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/* Configure ping pong counters in altera group */
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CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
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CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
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CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
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CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
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CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
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CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
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CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
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CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
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CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
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CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
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CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
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CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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CLKMGR_MAINPLL_PLLGLOB);
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CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
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CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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CLKMGR_PERPLL_PLLGLOB);
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/* Take all PLLs out of bypass */
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clk_write_bypass_mainpll(plat, 0);
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clk_write_bypass_perpll(plat, 0);
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/* Clear the loss of lock bits (write 1 to clear) */
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CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
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CLKMGR_INTER_PERPLLLOST_MASK |
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CLKMGR_INTER_MAINPLLLOST_MASK);
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/* Take all ping pong counters out of reset */
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CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
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CLKMGR_ALT_EXTCNTRST_ALLCNTRST);
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/* Out of boot mode */
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clk_write_ctrl(plat,
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CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
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}
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static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
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u32 pllglob_reg, u32 pllm_reg)
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{
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u64 fref, arefdiv, mdiv, reg, vco;
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reg = CM_REG_READL(plat, pllglob_reg);
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fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
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CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
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switch (fref) {
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case CLKMGR_VCO_PSRC_EOSC1:
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fref = cm_get_osc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_INTOSC:
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fref = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_F2S:
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fref = cm_get_fpga_clk_hz();
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break;
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}
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arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
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CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
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mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
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vco = fref / arefdiv;
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vco = vco * mdiv;
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return vco;
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}
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static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
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{
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return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLM);
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}
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static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
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{
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return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLM);
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}
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static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
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{
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u32 clksrc = CM_REG_READL(plat, reg);
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return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
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}
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static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
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u32 main_reg, u32 per_reg)
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{
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u64 clock;
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u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
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switch (clklsrc) {
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case CLKMGR_CLKSRC_MAIN:
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clock = clk_get_main_vco_clk_hz(plat);
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clock /= (CM_REG_READL(plat, main_reg) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_PER:
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clock = clk_get_per_vco_clk_hz(plat);
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clock /= (CM_REG_READL(plat, per_reg) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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default:
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return 0;
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}
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return clock;
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}
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|
||||
static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
|
||||
CLKMGR_MAINPLL_PLLC0,
|
||||
CLKMGR_PERPLL_PLLC0);
|
||||
|
||||
clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
|
||||
CLKMGR_CLKCNT_MSK);
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
|
||||
CLKMGR_MAINPLL_PLLC1,
|
||||
CLKMGR_PERPLL_PLLC1);
|
||||
}
|
||||
|
||||
static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
u64 clock = clk_get_l3_main_clk_hz(plat);
|
||||
|
||||
clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
|
||||
CLKMGR_NOCDIV_L4MAIN_OFFSET) &
|
||||
CLKMGR_NOCDIV_DIVIDER_MASK);
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
|
||||
CLKMGR_MAINPLL_PLLC3,
|
||||
CLKMGR_PERPLL_PLLC3);
|
||||
|
||||
clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
|
||||
CLKMGR_CLKCNT_MSK);
|
||||
|
||||
return clock / 4;
|
||||
}
|
||||
|
||||
static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
u64 clock = clk_get_l3_main_clk_hz(plat);
|
||||
|
||||
clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
|
||||
CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
|
||||
CLKMGR_NOCDIV_DIVIDER_MASK);
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
u64 clock = clk_get_l3_main_clk_hz(plat);
|
||||
|
||||
clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
|
||||
CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
|
||||
CLKMGR_NOCDIV_DIVIDER_MASK);
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
|
||||
{
|
||||
if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
|
||||
return clk_get_l3_main_clk_hz(plat) / 2;
|
||||
|
||||
return clk_get_l3_main_clk_hz(plat) / 4;
|
||||
}
|
||||
|
||||
static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
|
||||
{
|
||||
bool emacsel_a;
|
||||
u32 ctl;
|
||||
u32 ctr_reg;
|
||||
u32 clock;
|
||||
u32 div;
|
||||
u32 reg;
|
||||
|
||||
/* Get EMAC clock source */
|
||||
ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
|
||||
if (emac_id == AGILEX_EMAC0_CLK)
|
||||
ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
|
||||
CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
|
||||
else if (emac_id == AGILEX_EMAC1_CLK)
|
||||
ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
|
||||
CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
|
||||
else if (emac_id == AGILEX_EMAC2_CLK)
|
||||
ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
|
||||
CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
|
||||
else
|
||||
return 0;
|
||||
|
||||
if (ctl) {
|
||||
/* EMAC B source */
|
||||
emacsel_a = false;
|
||||
ctr_reg = CLKMGR_ALTR_EMACBCTR;
|
||||
} else {
|
||||
/* EMAC A source */
|
||||
emacsel_a = true;
|
||||
ctr_reg = CLKMGR_ALTR_EMACACTR;
|
||||
}
|
||||
|
||||
reg = CM_REG_READL(plat, ctr_reg);
|
||||
clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
|
||||
>> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
|
||||
div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
|
||||
>> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
|
||||
|
||||
switch (clock) {
|
||||
case CLKMGR_CLKSRC_MAIN:
|
||||
clock = clk_get_main_vco_clk_hz(plat);
|
||||
if (emacsel_a) {
|
||||
clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &
|
||||
CLKMGR_CLKCNT_MSK);
|
||||
} else {
|
||||
clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
|
||||
CLKMGR_CLKCNT_MSK);
|
||||
}
|
||||
break;
|
||||
|
||||
case CLKMGR_CLKSRC_PER:
|
||||
clock = clk_get_per_vco_clk_hz(plat);
|
||||
if (emacsel_a) {
|
||||
clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &
|
||||
CLKMGR_CLKCNT_MSK);
|
||||
} else {
|
||||
clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
|
||||
CLKMGR_CLKCNT_MSK);
|
||||
}
|
||||
break;
|
||||
|
||||
case CLKMGR_CLKSRC_OSC1:
|
||||
clock = cm_get_osc_clk_hz();
|
||||
break;
|
||||
|
||||
case CLKMGR_CLKSRC_INTOSC:
|
||||
clock = cm_get_intosc_clk_hz();
|
||||
break;
|
||||
|
||||
case CLKMGR_CLKSRC_FPGA:
|
||||
clock = cm_get_fpga_clk_hz();
|
||||
break;
|
||||
}
|
||||
|
||||
clock /= 1 + div;
|
||||
|
||||
return clock;
|
||||
}
|
||||
|
||||
static ulong socfpga_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
|
||||
|
||||
switch (clk->id) {
|
||||
case AGILEX_MPU_CLK:
|
||||
return clk_get_mpu_clk_hz(plat);
|
||||
case AGILEX_L4_MAIN_CLK:
|
||||
return clk_get_l4_main_clk_hz(plat);
|
||||
case AGILEX_L4_SYS_FREE_CLK:
|
||||
return clk_get_l4_sys_free_clk_hz(plat);
|
||||
case AGILEX_L4_MP_CLK:
|
||||
return clk_get_l4_mp_clk_hz(plat);
|
||||
case AGILEX_L4_SP_CLK:
|
||||
return clk_get_l4_sp_clk_hz(plat);
|
||||
case AGILEX_SDMMC_CLK:
|
||||
return clk_get_sdmmc_clk_hz(plat);
|
||||
case AGILEX_EMAC0_CLK:
|
||||
case AGILEX_EMAC1_CLK:
|
||||
case AGILEX_EMAC2_CLK:
|
||||
return clk_get_emac_clk_hz(plat, clk->id);
|
||||
case AGILEX_USB_CLK:
|
||||
return clk_get_l4_mp_clk_hz(plat);
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
}
|
||||
|
||||
static int socfpga_clk_probe(struct udevice *dev)
|
||||
{
|
||||
const struct cm_config *cm_default_cfg = cm_get_default_config();
|
||||
|
||||
clk_basic_init(dev, cm_default_cfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
|
||||
fdt_addr_t addr;
|
||||
|
||||
addr = devfdt_get_addr(dev);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->regs = (void __iomem *)addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops socfpga_clk_ops = {
|
||||
.get_rate = socfpga_clk_get_rate,
|
||||
};
|
||||
|
||||
static const struct udevice_id socfpga_clk_match[] = {
|
||||
{ .compatible = "intel,agilex-clkmgr" },
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(socfpga_agilex_clk) = {
|
||||
.name = "clk-agilex",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = socfpga_clk_match,
|
||||
.ops = &socfpga_clk_ops,
|
||||
.probe = socfpga_clk_probe,
|
||||
.ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),
|
||||
};
|
||||
237
drivers/clk/altera/clk-agilex.h
Normal file
237
drivers/clk/altera/clk-agilex.h
Normal file
@ -0,0 +1,237 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 Intel Corporation <www.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef _CLK_AGILEX_
|
||||
#define _CLK_AGILEX_
|
||||
|
||||
#define CM_REG_READL(plat, reg) \
|
||||
readl((plat)->regs + (reg))
|
||||
|
||||
#define CM_REG_WRITEL(plat, data, reg) \
|
||||
writel(data, (plat)->regs + (reg))
|
||||
|
||||
#define CM_REG_CLRBITS(plat, reg, clear) \
|
||||
clrbits_le32((plat)->regs + (reg), (clear))
|
||||
|
||||
#define CM_REG_SETBITS(plat, reg, set) \
|
||||
setbits_le32((plat)->regs + (reg), (set))
|
||||
|
||||
struct cm_config {
|
||||
/* main group */
|
||||
u32 main_pll_mpuclk;
|
||||
u32 main_pll_nocclk;
|
||||
u32 main_pll_nocdiv;
|
||||
u32 main_pll_pllglob;
|
||||
u32 main_pll_fdbck;
|
||||
u32 main_pll_pllc0;
|
||||
u32 main_pll_pllc1;
|
||||
u32 main_pll_pllc2;
|
||||
u32 main_pll_pllc3;
|
||||
u32 main_pll_pllm;
|
||||
|
||||
/* peripheral group */
|
||||
u32 per_pll_emacctl;
|
||||
u32 per_pll_gpiodiv;
|
||||
u32 per_pll_pllglob;
|
||||
u32 per_pll_fdbck;
|
||||
u32 per_pll_pllc0;
|
||||
u32 per_pll_pllc1;
|
||||
u32 per_pll_pllc2;
|
||||
u32 per_pll_pllc3;
|
||||
u32 per_pll_pllm;
|
||||
|
||||
/* altera group */
|
||||
u32 alt_emacactr;
|
||||
u32 alt_emacbctr;
|
||||
u32 alt_emacptpctr;
|
||||
u32 alt_gpiodbctr;
|
||||
u32 alt_sdmmcctr;
|
||||
u32 alt_s2fuser0ctr;
|
||||
u32 alt_s2fuser1ctr;
|
||||
u32 alt_psirefctr;
|
||||
|
||||
/* incoming clock */
|
||||
u32 hps_osc_clk_hz;
|
||||
u32 fpga_clk_hz;
|
||||
u32 spare[3];
|
||||
};
|
||||
|
||||
/* Clock Manager registers */
|
||||
#define CLKMGR_CTRL 0
|
||||
#define CLKMGR_STAT 4
|
||||
#define CLKMGR_TESTIOCTRL 8
|
||||
#define CLKMGR_INTRGEN 0x0c
|
||||
#define CLKMGR_INTRMSK 0x10
|
||||
#define CLKMGR_INTRCLR 0x14
|
||||
#define CLKMGR_INTRSTS 0x18
|
||||
#define CLKMGR_INTRSTK 0x1c
|
||||
#define CLKMGR_INTRRAW 0x20
|
||||
|
||||
/* Clock Manager Main PPL group registers */
|
||||
#define CLKMGR_MAINPLL_EN 0x24
|
||||
#define CLKMGR_MAINPLL_ENS 0x28
|
||||
#define CLKMGR_MAINPLL_ENR 0x2c
|
||||
#define CLKMGR_MAINPLL_BYPASS 0x30
|
||||
#define CLKMGR_MAINPLL_BYPASSS 0x34
|
||||
#define CLKMGR_MAINPLL_BYPASSR 0x38
|
||||
#define CLKMGR_MAINPLL_MPUCLK 0x3c
|
||||
#define CLKMGR_MAINPLL_NOCCLK 0x40
|
||||
#define CLKMGR_MAINPLL_NOCDIV 0x44
|
||||
#define CLKMGR_MAINPLL_PLLGLOB 0x48
|
||||
#define CLKMGR_MAINPLL_FDBCK 0x4c
|
||||
#define CLKMGR_MAINPLL_MEM 0x50
|
||||
#define CLKMGR_MAINPLL_MEMSTAT 0x54
|
||||
#define CLKMGR_MAINPLL_PLLC0 0x58
|
||||
#define CLKMGR_MAINPLL_PLLC1 0x5c
|
||||
#define CLKMGR_MAINPLL_VCOCALIB 0x60
|
||||
#define CLKMGR_MAINPLL_PLLC2 0x64
|
||||
#define CLKMGR_MAINPLL_PLLC3 0x68
|
||||
#define CLKMGR_MAINPLL_PLLM 0x6c
|
||||
#define CLKMGR_MAINPLL_FHOP 0x70
|
||||
#define CLKMGR_MAINPLL_SSC 0x74
|
||||
#define CLKMGR_MAINPLL_LOSTLOCK 0x78
|
||||
|
||||
/* Clock Manager Peripheral PPL group registers */
|
||||
#define CLKMGR_PERPLL_EN 0x7c
|
||||
#define CLKMGR_PERPLL_ENS 0x80
|
||||
#define CLKMGR_PERPLL_ENR 0x84
|
||||
#define CLKMGR_PERPLL_BYPASS 0x88
|
||||
#define CLKMGR_PERPLL_BYPASSS 0x8c
|
||||
#define CLKMGR_PERPLL_BYPASSR 0x90
|
||||
#define CLKMGR_PERPLL_EMACCTL 0x94
|
||||
#define CLKMGR_PERPLL_GPIODIV 0x98
|
||||
#define CLKMGR_PERPLL_PLLGLOB 0x9c
|
||||
#define CLKMGR_PERPLL_FDBCK 0xa0
|
||||
#define CLKMGR_PERPLL_MEM 0xa4
|
||||
#define CLKMGR_PERPLL_MEMSTAT 0xa8
|
||||
#define CLKMGR_PERPLL_PLLC0 0xac
|
||||
#define CLKMGR_PERPLL_PLLC1 0xb0
|
||||
#define CLKMGR_PERPLL_VCOCALIB 0xb4
|
||||
#define CLKMGR_PERPLL_PLLC2 0xb8
|
||||
#define CLKMGR_PERPLL_PLLC3 0xbc
|
||||
#define CLKMGR_PERPLL_PLLM 0xc0
|
||||
#define CLKMGR_PERPLL_FHOP 0xc4
|
||||
#define CLKMGR_PERPLL_SSC 0xc8
|
||||
#define CLKMGR_PERPLL_LOSTLOCK 0xcc
|
||||
|
||||
/* Clock Manager Altera group registers */
|
||||
#define CLKMGR_ALTR_JTAG 0xd0
|
||||
#define CLKMGR_ALTR_EMACACTR 0xd4
|
||||
#define CLKMGR_ALTR_EMACBCTR 0xd8
|
||||
#define CLKMGR_ALTR_EMACPTPCTR 0xdc
|
||||
#define CLKMGR_ALTR_GPIODBCTR 0xe0
|
||||
#define CLKMGR_ALTR_SDMMCCTR 0xe4
|
||||
#define CLKMGR_ALTR_S2FUSER0CTR 0xe8
|
||||
#define CLKMGR_ALTR_S2FUSER1CTR 0xec
|
||||
#define CLKMGR_ALTR_PSIREFCTR 0xf0
|
||||
#define CLKMGR_ALTR_EXTCNTRST 0xf4
|
||||
|
||||
#define CLKMGR_CTRL_BOOTMODE BIT(0)
|
||||
|
||||
#define CLKMGR_STAT_BUSY BIT(0)
|
||||
#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
|
||||
#define CLKMGR_STAT_MAIN_TRANS BIT(9)
|
||||
#define CLKMGR_STAT_PERPLL_LOCKED BIT(16)
|
||||
#define CLKMGR_STAT_PERF_TRANS BIT(17)
|
||||
#define CLKMGR_STAT_BOOTMODE BIT(24)
|
||||
#define CLKMGR_STAT_BOOTCLKSRC BIT(25)
|
||||
|
||||
#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
|
||||
(CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
|
||||
|
||||
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
|
||||
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
|
||||
#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
|
||||
#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
|
||||
|
||||
#define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
|
||||
#define CLKMGR_CLKSRC_OFFSET 16
|
||||
#define CLKMGR_CLKSRC_MAIN 0
|
||||
#define CLKMGR_CLKSRC_PER 1
|
||||
#define CLKMGR_CLKSRC_OSC1 2
|
||||
#define CLKMGR_CLKSRC_INTOSC 3
|
||||
#define CLKMGR_CLKSRC_FPGA 4
|
||||
#define CLKMGR_CLKCNT_MSK GENMASK(10, 0)
|
||||
|
||||
#define CLKMGR_BYPASS_MAINPLL_ALL 0x7
|
||||
#define CLKMGR_BYPASS_PERPLL_ALL 0x7f
|
||||
|
||||
#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
|
||||
#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
|
||||
#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
|
||||
#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
|
||||
#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
|
||||
#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
|
||||
#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3
|
||||
|
||||
#define CLKMGR_PLLGLOB_PD_MASK BIT(0)
|
||||
#define CLKMGR_PLLGLOB_RST_MASK BIT(1)
|
||||
#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8)
|
||||
#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12)
|
||||
#define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8)
|
||||
#define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27)
|
||||
#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8
|
||||
#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12
|
||||
#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
|
||||
#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24
|
||||
#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
|
||||
#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
|
||||
#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
|
||||
|
||||
#define CLKMGR_VCO_PSRC_EOSC1 0
|
||||
#define CLKMGR_VCO_PSRC_INTOSC 1
|
||||
#define CLKMGR_VCO_PSRC_F2S 2
|
||||
|
||||
#define CLKMGR_MEM_REQ_SET_MSK BIT(24)
|
||||
#define CLKMGR_MEM_WR_SET_MSK BIT(25)
|
||||
#define CLKMGR_MEM_ERR_MSK BIT(26)
|
||||
#define CLKMGR_MEM_WDAT_LSB_OFFSET 16
|
||||
#define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0)
|
||||
#define CLKMGR_MEM_ADDR_START 0x00004000
|
||||
|
||||
#define CLKMGR_PLLCX_EN_SET_MSK BIT(27)
|
||||
#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28)
|
||||
|
||||
#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16)
|
||||
#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16
|
||||
#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0)
|
||||
#define CLKMGR_VCOCALIB_MSCNT_CONST 100
|
||||
#define CLKMGR_VCOCALIB_HSCNT_CONST 4
|
||||
|
||||
#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
|
||||
|
||||
#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
|
||||
|
||||
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
|
||||
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
|
||||
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
|
||||
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
|
||||
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27)
|
||||
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28
|
||||
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28)
|
||||
|
||||
#define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16
|
||||
#define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16)
|
||||
#define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0
|
||||
#define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0)
|
||||
|
||||
#define CLKMGR_ALT_EXTCNTRST_EMACACNTRST BIT(0)
|
||||
#define CLKMGR_ALT_EXTCNTRST_EMACBCNTRST BIT(1)
|
||||
#define CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST BIT(2)
|
||||
#define CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST BIT(3)
|
||||
#define CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST BIT(4)
|
||||
#define CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST BIT(5)
|
||||
#define CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST BIT(6)
|
||||
#define CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST BIT(7)
|
||||
#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST \
|
||||
(CLKMGR_ALT_EXTCNTRST_EMACACNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_EMACBCNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST | \
|
||||
CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST)
|
||||
#endif /* _CLK_AGILEX_ */
|
||||
71
include/dt-bindings/clock/agilex-clock.h
Normal file
71
include/dt-bindings/clock/agilex-clock.h
Normal file
@ -0,0 +1,71 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019, Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __AGILEX_CLOCK_H
|
||||
#define __AGILEX_CLOCK_H
|
||||
|
||||
/* fixed rate clocks */
|
||||
#define AGILEX_OSC1 0
|
||||
#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
|
||||
#define AGILEX_CB_INTOSC_LS_CLK 2
|
||||
#define AGILEX_L4_SYS_FREE_CLK 3
|
||||
#define AGILEX_F2S_FREE_CLK 4
|
||||
|
||||
/* PLL clocks */
|
||||
#define AGILEX_MAIN_PLL_CLK 5
|
||||
#define AGILEX_MAIN_PLL_C0_CLK 6
|
||||
#define AGILEX_MAIN_PLL_C1_CLK 7
|
||||
#define AGILEX_MAIN_PLL_C2_CLK 8
|
||||
#define AGILEX_MAIN_PLL_C3_CLK 9
|
||||
#define AGILEX_PERIPH_PLL_CLK 10
|
||||
#define AGILEX_PERIPH_PLL_C0_CLK 11
|
||||
#define AGILEX_PERIPH_PLL_C1_CLK 12
|
||||
#define AGILEX_PERIPH_PLL_C2_CLK 13
|
||||
#define AGILEX_PERIPH_PLL_C3_CLK 14
|
||||
#define AGILEX_MPU_FREE_CLK 15
|
||||
#define AGILEX_MPU_CCU_CLK 16
|
||||
#define AGILEX_BOOT_CLK 17
|
||||
|
||||
/* fixed factor clocks */
|
||||
#define AGILEX_L3_MAIN_FREE_CLK 18
|
||||
#define AGILEX_NOC_FREE_CLK 19
|
||||
#define AGILEX_S2F_USR0_CLK 20
|
||||
#define AGILEX_NOC_CLK 21
|
||||
#define AGILEX_EMAC_A_FREE_CLK 22
|
||||
#define AGILEX_EMAC_B_FREE_CLK 23
|
||||
#define AGILEX_EMAC_PTP_FREE_CLK 24
|
||||
#define AGILEX_GPIO_DB_FREE_CLK 25
|
||||
#define AGILEX_SDMMC_FREE_CLK 26
|
||||
#define AGILEX_S2F_USER0_FREE_CLK 27
|
||||
#define AGILEX_S2F_USER1_FREE_CLK 28
|
||||
#define AGILEX_PSI_REF_FREE_CLK 29
|
||||
|
||||
/* Gate clocks */
|
||||
#define AGILEX_MPU_CLK 30
|
||||
#define AGILEX_MPU_PERIPH_CLK 31
|
||||
#define AGILEX_L4_MAIN_CLK 32
|
||||
#define AGILEX_L4_MP_CLK 33
|
||||
#define AGILEX_L4_SP_CLK 34
|
||||
#define AGILEX_CS_AT_CLK 35
|
||||
#define AGILEX_CS_TRACE_CLK 36
|
||||
#define AGILEX_CS_PDBG_CLK 37
|
||||
#define AGILEX_CS_TIMER_CLK 38
|
||||
#define AGILEX_S2F_USER0_CLK 39
|
||||
#define AGILEX_EMAC0_CLK 40
|
||||
#define AGILEX_EMAC1_CLK 41
|
||||
#define AGILEX_EMAC2_CLK 42
|
||||
#define AGILEX_EMAC_PTP_CLK 43
|
||||
#define AGILEX_GPIO_DB_CLK 44
|
||||
#define AGILEX_NAND_CLK 45
|
||||
#define AGILEX_PSI_REF_CLK 46
|
||||
#define AGILEX_S2F_USER1_CLK 47
|
||||
#define AGILEX_SDMMC_CLK 48
|
||||
#define AGILEX_SPI_M_CLK 49
|
||||
#define AGILEX_USB_CLK 50
|
||||
#define AGILEX_NAND_X_CLK 51
|
||||
#define AGILEX_NAND_ECC_CLK 52
|
||||
#define AGILEX_NUM_CLKS 53
|
||||
|
||||
#endif /* __AGILEX_CLOCK_H */
|
||||
Loading…
Reference in New Issue
Block a user