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arm: socfpga: Move Stratix10 and Agilex reset manager common code
Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
8b7962a349
commit
fd5374aa29
@ -44,7 +44,7 @@ void socfpga_per_reset_all(void);
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/reset_manager_arria10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
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#include <asm/arch/reset_manager_s10.h>
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#include <asm/arch/reset_manager_soc64.h>
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#endif
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#endif /* _RESET_MANAGER_H_ */
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@ -1,95 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _RESET_MANAGER_S10_
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#define _RESET_MANAGER_S10_
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void reset_cpu(ulong addr);
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int cpu_has_been_warmreset(void);
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void socfpga_bridges_reset(int enable);
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void socfpga_per_reset(u32 reset, int set);
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void socfpga_per_reset_all(void);
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#define RSTMGR_S10_STATUS 0x00
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#define RSTMGR_S10_MPUMODRST 0x20
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#define RSTMGR_S10_PER0MODRST 0x24
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#define RSTMGR_S10_PER1MODRST 0x28
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#define RSTMGR_S10_BRGMODRST 0x2c
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#define RSTMGR_MPUMODRST_CORE0 0
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#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
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#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
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#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
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/* Watchdogs and MPU warm reset mask */
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#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
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/*
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* Define a reset identifier, from which a permodrst bank ID
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* and reset ID can be extracted using the subsequent macros
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* RSTMGR_RESET() and RSTMGR_BANK().
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*/
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#define RSTMGR_BANK_OFFSET 8
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#define RSTMGR_BANK_MASK 0x7
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#define RSTMGR_RESET_OFFSET 0
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#define RSTMGR_RESET_MASK 0x1f
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#define RSTMGR_DEFINE(_bank, _offset) \
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((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
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/* Extract reset ID from the reset identifier. */
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#define RSTMGR_RESET(_reset) \
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(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
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/* Extract bank ID from the reset identifier. */
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#define RSTMGR_BANK(_reset) \
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(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
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/*
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* SocFPGA Stratix10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
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#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
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#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
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#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
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#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
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#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
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#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
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#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
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#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
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#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
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#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
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#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
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#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
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#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
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#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
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#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
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#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
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#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
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#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
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#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
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#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
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/* Create a human-readable reference to SoCFPGA reset. */
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#define SOCFPGA_RESET(_name) RSTMGR_##_name
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#endif /* _RESET_MANAGER_S10_ */
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38
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
Normal file
38
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
Normal file
@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
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*/
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#ifndef _RESET_MANAGER_SOC64_H_
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#define _RESET_MANAGER_SOC64_H_
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void reset_deassert_peripherals_handoff(void);
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int cpu_has_been_warmreset(void);
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void socfpga_bridges_reset(int enable);
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#define RSTMGR_SOC64_STATUS 0x00
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#define RSTMGR_SOC64_MPUMODRST 0x20
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#define RSTMGR_SOC64_PER0MODRST 0x24
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#define RSTMGR_SOC64_PER1MODRST 0x28
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#define RSTMGR_SOC64_BRGMODRST 0x2c
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#define RSTMGR_MPUMODRST_CORE0 0
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#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
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#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
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#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
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/* Watchdogs and MPU warm reset mask */
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#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
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/*
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* SocFPGA Stratix10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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*/
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#endif /* _RESET_MANAGER_SOC64_H_ */
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@ -18,13 +18,13 @@ void socfpga_per_reset(u32 reset, int set)
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unsigned long reg;
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if (RSTMGR_BANK(reset) == 0)
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reg = RSTMGR_S10_MPUMODRST;
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reg = RSTMGR_SOC64_MPUMODRST;
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else if (RSTMGR_BANK(reset) == 1)
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reg = RSTMGR_S10_PER0MODRST;
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reg = RSTMGR_SOC64_PER0MODRST;
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else if (RSTMGR_BANK(reset) == 2)
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reg = RSTMGR_S10_PER1MODRST;
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reg = RSTMGR_SOC64_PER1MODRST;
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else if (RSTMGR_BANK(reset) == 3)
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reg = RSTMGR_S10_BRGMODRST;
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reg = RSTMGR_SOC64_BRGMODRST;
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else /* Invalid reset register, do nothing */
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return;
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@ -47,9 +47,9 @@ void socfpga_per_reset_all(void)
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/* disable all except OCP and l4wd0. OCP disable later */
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writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
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socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
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writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
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writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST);
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socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
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writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
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writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
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}
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void socfpga_bridges_reset(int enable)
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@ -60,7 +60,7 @@ void socfpga_bridges_reset(int enable)
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SYSMGR_S10_NOC_IDLEREQ_CLR, ~0);
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/* Release all bridges from reset state */
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clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
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clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
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~0);
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/* Poll until all idleack to 0 */
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@ -86,7 +86,7 @@ void socfpga_bridges_reset(int enable)
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;
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/* Reset all bridges (except NOR DDR scheduler & F2S) */
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
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setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
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~(RSTMGR_BRGMODRST_DDRSCH_MASK |
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RSTMGR_BRGMODRST_FPGA2SOC_MASK));
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@ -100,6 +100,6 @@ void socfpga_bridges_reset(int enable)
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*/
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int cpu_has_been_warmreset(void)
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{
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return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) &
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return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
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RSTMGR_L4WD_MPU_WARMRESET_MASK;
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}
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