We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.
This adds the sgrf node to the rk3368.dtsi, so we can then bind a
syscon device onto it and access its memory ranges.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines. As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
In TPL we will need to configure security in the SGRF of the RK3368.
This change adds support for the SGRF as a syscon device, so we can
retrieve its address range through the syscon API in TPL (and can
avoid having to hard-code the address).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 has both a limited TPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for TPL (particularily when using the LP64 programming model). For
this reason we expect the RK3368 to always use OF_PLATDATA for its
TPL stage.
This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On the RK3368 we use a TPL-stage similar to Rockchip's DDR init
(i.e. it initialises DRAM, leaves some info for the next stage and
returns to the BootROM). To allow compatibility with Rockchip's DDR
init code, we use the same register os_reg2 in pmugrf for passing
this info (i.e. DRAM size and configuration) between stages.
This change adds the definitions for os_reg[0] through os_reg[3] to
the pmugrf structure for the RK3368.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
and had a few typos and unnecessarily used UTF-8 characters. While
fixing this, I also reformatted and further clarified the text
(e.g. made the grouping into a a big and little cluster of 4 cores
each explicit).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The utility functions in sdram_common.c will be useful both for some
SPL implementations (and if unused, the linked will discard these
anyway) and for the full U-Boot stage.
This changes selects sdram_common.o through the $(SPL_TPL_) macro to
allow better control of its inclusion through the CONFIG_ROM,
CONFIG_SPL_RAM or CONFIG_TPL_RAM options.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks. To do so, we introduce
CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
the initial stack pointer for TPL.
To provide backward compatibility for existing boards, this is added
as an optional configuration item and the normal search order (i.e.
SPL_STACK, then SYS_STACK) apply if not defined.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway. By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.
Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.
Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the finer-grained control over LIBCOMMON_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBCOMMON_SUPPORT and
SPL_LIBCOMMON_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up to use 'puts' and LIBCOMMON:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The back-to-bootrom option is rather unfortunately named
CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM
To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it. At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.
This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:]
[fixed inverted CONFIG_IS_ENABLED test for rk3288:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
include/configs/rock.h: undef
The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.
To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Some devices (e.g. the RK3368) have only limited SRAM, but provide
support for loading the next boot stage after our SPL performs basic
setup (e.g. DRAM).
For target systems like these, we add a boot device BOOTROM that will
invoke a board-specific hook to return to the bootrom (if supported).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x01)
is always false.
This does not match the comment
/*Wait till that bit clears*/
The problem was indicated by cppcheck.
I do not have the hardware to test if the code change below
leads to a correct system behavior.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixes: 00bbe96eba ("arm: omap: Unify get_device_type() function")
The control status register value is embedded in a structure somewhere
in SRAM, with the last refactoring effort. This patch allows OMAP3 EVM
(TMDSEVM3530) to boot again using the known control register base and
offset for 'readl', for the OMAP34XX case.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
[trini: Change to if/else, add comment about it.]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_NAND
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Sync up a few more, add imply's]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_CMD_ZBOOT
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_SPL
Note that trats does not actually use SPL, so this option can no-longer be
set.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_SH_ZIMAGEBOOT
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_SF_TEST
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_SAVES
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch converts CONFIG_CMD_REGINFO to Kconfig
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_PCI
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This converts the following to Kconfig:
CONFIG_CMD_PCA953X
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Synced ohci0 and ehci0 nodes from Linux for sun50i-a64.dtsi
Here is the Linux last merge tag details:
Merge: 0e91f43d e5770b7
Author: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Fri Jun 9 14:59:55 2017 +1000
Merge remote-tracking branch 'staging/staging-next'
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
the access to some clock/power related registers in PRCM.
Current Linux kernel will access the CPUS (AR100) clock in the PRCM
block, so the PRCM should be switched to non-secure.
Add code to switch the PRCM to non-secure.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header
file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one.
This makes the original node (mmc2_pins_a) scrapped out of the dtb and
result in a unusable eMMC if U-Boot didn't configured the pins to the
correct functions.
Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
When CONFIG_EFI_PARTITION is not set, the following build error is
seen in arch/x86/lib/acpi_s3.c:
error: expected declaration specifiers or '...' before '*' token
static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void*)WAKEUP_BASE;
This is actually caused by missing asmlinkage declaration, but with
CONFIG_EFI_PARTITION on, the declaration comes from part.h which
is included from common.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Neither new design uses ISA bus, nor does any U-Boot codes use these
codes. Remove them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
move to Kconfig:
CONFIG_BCM_SF2_ETH
CONFIG_BCM_SF2_ETH_DEFAULT_PORT
CONFIG_BCM_SF2_ETH_GMAC
Also modified defconfigs of all platforms that use these configs.
Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com>
Tested-by: Suji Velupillai <suji.velupillai@broadcom.com>
Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update the configuration files to support the device tree and driver
model. The peripheral clock and pins configuration are handled by
the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the changes to fdt_get_base_address() we need to modify the logic
in ft_verify_fdt() for how we check the validity of the CCSR address.
Tested-on: qemu-ppce500 -M mpc8544ds
Fixes: 336a44877a ("fdt: Correct fdt_get_base_address()")
Cc: York Sun <york.sun@nxp.com>
Cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6,
commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3
and H3 ULCB and Salvator-X boards.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add initial support for the R8A7795 and R8A7796 based ULCB board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add the PFC5 PUEN address and SSI SDATA4 bit offset into the
rcar-gen3-base.h .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add support for Phytec pfla02, equipped with NAND.
CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 31C
Reset cause: POR
I2C: ready
DRAM: 1 GiB
NAND: 2048 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total
16 MiB
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Christ <s.christ@phytec.de>
CC: Stefan Müller-Klieser <S.Mueller-Klieser@phytec.de>
CC: Christian Hemp <C.Hemp@phytec.de>
Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch makes chip_id() as a global routine so that
it can be used in other places as required.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch modifies the chip_id routine to get either idcode or
silicon version based on the argument received.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Not using board revision is causing confusion about which board is
supported and tested. Mark dts files exactly with board revision which
was tested. When new board revision arives it can be symlink if SW view
is the same. Also add -revX suffix to compatible string because user space
tools are parsing this string and can change behavior depends of board
revision.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Remove incorrect code of writing to system timestamp
counter registers. This register writes does nothing
and can be removed.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is a need to include psu_init also in mini u-boot configuration
that's why handle psu_init via Kconfig property.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
For some mini platforms there could be a need to include psu_init.
That's why move it to board file instead of spl only file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes ifdef around mmio read and write rotuines
and make them a single routine by checking the current el.
This patch helps to remove ifdef around invoke_smc as well.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
TCM on ZynqMP needs to be intialized in a sequence
and this patch provides a global routine to perform
this as per requirement.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch provides an option to include OCM and TCM memory
into MMU table with corresponding memory attributes.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Z-Turn board is a low cost development board based on the
Xilinx Zynq SoC. While it's powerful and quite versatile, it
so far lacked upstream support.
This patch adds basic support for the Z-Turn. It does however
for now miss enablement for MIO51 reset which means that USB
and ethernet don't work. For that either FSBL or SPL need to
be adjusted. The SPL part will follow later.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When using EFI_LOADER, we add a few special sections for runtime code and
data which get relocated on demand when executing a target OS.
These runtime structures need to get annotated properly in the linker script.
While we do that properly in the generic one, we missed out on the zynq
specific linker script.
This patch adds the EFI runtime section annotations into the zynq linker script
so that the efi loader code actually works on that platform.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed.
The definitions in <image.h> are used.
According to this modification, the comparison between os arch and cpu
arch is done in C programming instead of ASM programming.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
After MMC is converted to DM, convert to use DM SCSI as well for all
x86 boards and imply BLK for both MMC and SCSI drivers.
CONFIG_SCSI_DEV_LIST is no longer used. Clean them up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove DM_MMC from edison_defconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The value of uma_memory_size depends on an undefined value
from the stack. The value of uma_memory_size is changed but
never used.
So simply remove this superfluous code.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This converts Intel ICH6 GPIO driver to Kconfig, and add it to the
imply list of platform drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Like other peripheral drivers, move USB related drivers to platform
Kconfig as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Imply Tangier-specific drivers in the platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
U-Boot as coreboot payload can run on any x86 hardware ideally.
Let's imply some common drivers that are useful.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Imply drivers that are working with Ivybridge platform in the
platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
BayTrail integrates lots of peripherals that have U-Boot drivers.
Imply those in the platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that all x86 boards have been converted to use DM, we can imply
these uclass drivers (DM_ETH, DM_RTC, DM_USB, DM_VIDEO) from the
top level.
Previously DM_GPIO, DM_KEYBOARD, DM_SERIAL, DM_SPI, DM_SPI_FLASH
are selected. Change to use 'imply' to allow them to be removed.
Note with this change, chromebook_link64 build fails:
common/built-in.o:(.data.env_htab+0xc): undefined reference to 'env_flags_validate'
lib/built-in.o: In function `hsearch_r':
lib/hashtable.c:380: undefined reference to 'env_callback_init'
lib/hashtable.c:382: undefined reference to 'env_flags_init'
make[1]: *** [spl/u-boot-spl] Error 1
CONFIG_SPL_ENV_SUPPORT is required for chromebook_link64 to build
again. This is just a workaround as it is not needed at all. See
commit bda40d5 "x86: qemu: Add a config for 64-bit U-Boot" for
the same issue seen on QEMU 64-bit target.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is a must have for all x86 boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Platform knows whether MRC cache is implemented, but using it can
be a choice of a specific board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is architecture-dependent early initialization hence should
be put in the platform Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch_misc_init() is intended to do architecture-dependent stuff.
This is required by each platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes
and should be not 'default y' for all x86 boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Intel Management Engine is required by the platform, however it's
not a must have when building a U-Boot image. For example, during
development normally programming ME firmware is a one-time effort.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
PCI is the de facto interconnect bus in an x86 system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
x86 is using the built-in libgcc implementation and this cannot be
turned off.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Without a timer, U-Boot just doesn't boot. This is not something
we can turn off.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some firmwares might have another window for generated tables.
So, introduce two configuration options to select start address and
maximum length for the generated tables.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
64-bit U-Boot image is a combination of 32-bit U-Boot (SPL) plus
64-bit U-Boot (proper). For the U-Boot proper, it has be compiled
to 64-bit object codes. Attempting to use a toolchain to compile
64-bit U-Boot for qemu-x86_64, like kernel.org 4.9 i386-linux-gcc,
fails with the following errors:
arch/x86/cpu/intel_common/microcode.c:79:2: error: PIC register
clobbered by 'ebx' in 'asm'
The issue is because toolchain is preconfigured to generate code
for the 32-bit architecture (i386), and currently '-m64' is missing
in the makefile fragment. Using kernel.org 4.9 x86_64-linux-gcc
works out of the box, since it is preconfigured to generate 64-bit
codes.
When compiling U-Boot SPL, '-m32' is passed to the toolchain, no
mater 32-bit (i386-linux-) or 64-bit (x86_64-linux) the toolchain
is preconfigured to generate.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present U-Boot x86 build is using -mpreferred-stack-boundary=2
which is 4 bytes stack boundary alignment. With 64-bit U-Boot, the
minimal required stack boundary alignment is 16 bytes.
If -mpreferred-stack-boundary is not specified, the default is 4
(16 bytes). Switch to use the default one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is shown as active high in the schematics[1], so fix it.
[1] https://patchwork.ozlabs.org/patch/777890/
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com>
At present the AHCI SCSI driver only supports PCI with driver model.
Rename the existing function to indicate this and add support for adding
a non-PCI controller .
Signed-off-by: Simon Glass <sjg@chromium.org>
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS
CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the
defconfig files.
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The image address passed to secure_boot_verify_image() may not be
cacheline aligned, round the address down to the nearest cacheline.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
If ACPI HW reduced bit in FADT is set we should ignore any ACPI hardware
communications.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some platforms might require different approach when filling memory
mappings configuration table.
Allow them to override the common method.
At the same time export acpi_create_mcfg_mmconfig().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In Baytrail and Quark support code acpi_fill_madt() is identical.
Deduplicate its implementation by moving to lib/acpi_tables.c.
At the same time mark acpi_fill_madt() with __weak attribute to keep a
possibility to override it in platform code
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI specification defines FADT fields marked as reserved in U-Boot.
Name these fields in accordance with ACPI specification.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fill OEM revision field in the tables by U-Boot build date.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Change from EHCI to xHCI on the DFI BayTrail SoM.
The xHCI USB hub is connected to an GPIO on the DFI BayTrail SoM. For
correct operation, it needs to get reset upon power-up. Otherwise it
may happen that the hub is not detected after a software reboot. This
patch also configures this GPIO in the dts for correct operation.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add Intel Edison board which is using U-Boot.
The patch is based on work done by the following people (in alphabetical
order):
Aiden Park <aiden.park@intel.com>
Dukjoon Jeon <dukjoon.jeon@intel.com>
eric.park <eric.park@intel.com>
Fabien Chereau <fabien.chereau@intel.com>
Felipe Balbi <felipe.balbi@linux.intel.com>
Scott D Phillips <scott.d.phillips@intel.com>
Sebastien Colleur <sebastienx.colleur@intel.com>
Steve Sakoman <steve.sakoman@intel.com>
Vincent Tinelli <vincent.tinelli@intel.com>
In case we're building for Intel Edison, we must have 4096 bytes of
zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.
First run sets hardware_id environment variable which is read from
System Controller Unit (SCU).
Serial number (serial# environment variable) is generated based on eMMC
CID.
MAC address on USB network interface is unique to the board but kept the
same all over the time.
Set mac address from U-Boot using following scheme:
OUI = 02:00:86
next 3 bytes of MAC address set from eMMC serial number
This allows to have a unique mac address across reboot and flashing.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[bmeng: Add MAINTAINERS file for Intel Edison board]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add Intel Tangier SoC support.
Intel Tangier SoC is a core part of Intel Merrifield platform. For
example, Intel Edison board is based on such platform.
The patch is based on work done by the following people (in alphabetical
order):
Aiden Park <aiden.park@intel.com>
Dukjoon Jeon <dukjoon.jeon@intel.com>
eric.park <eric.park@intel.com>
Fabien Chereau <fabien.chereau@intel.com>
Scott D Phillips <scott.d.phillips@intel.com>
Sebastien Colleur <sebastienx.colleur@intel.com>
Steve Sakoman <steve.sakoman@intel.com>
Vincent Tinelli <vincent.tinelli@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Some cross-platform drivers rely on this header present.
Make it so for x86.
It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Kbuild complains if USB is not selected before any of host driver.
warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB)
warning: (X86) selects USB_EHCI_HCD which has unmet direct dependencies (USB)
Select it for X86.
Fixes: 64d6ac5bc4 ("Kconfig: USB: Migrate CONFIG_USB_EHCI_HCD users to Kconfig")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
[bmeng: Update all x86 boards' defconfig files to remove CONFIG_USB]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS,
remove it in all boards' config files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Convert this PMIC driver to driver model and fix up other users. The
regulator and GPIO functions are now handled by separate drivers.
Update nyan-big to work correct. Three boards will need to be updated by
the maintainers: apalis-tk1, cei-tk1-som. Also the TODO in the code re
as3722_sd_set_voltage() needs to be completed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
This property should be in the /chosen node, not /aliases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
Adjust this to take a device as a parameter instead of a node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
Adjust this code to support a live device tree. This should be implemented
as a PHY driver but that is left as an exercise for the maintainer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
The PMC can be modelled as a syscon peripheral. Add a driver for this
so that it can be accessed by drivers when needed. Enable it for tegra124
boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
Enable the debug UART in SPL to allow early serial output even if the
standard UART does not work (e.g. due to driver model problem).
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
They are unused since commit d8c6fb8ced ("sandbox: Drop special
case console code for sandbox").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add this dts to enable debug uart releated devices
before relocation.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
SPL and normal u-boot stage use different malloc pool size
configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN)
to fit different boot stage.
Signed-off-by: Andy Yan <andyshrk@gmail.com>
Changes in v3:
- use CONFIG_VAL(), which suggested by Simon
Changes in v2: None
arch/sandbox/cpu/start.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.
Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.
Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.
Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously
enabled through rk3399_common.h. This change implies these options
through Kconfig.
These need to always be active for the RK3399, as follows:
- SPL_SERIAL_SUPPORT is needed to pass the SPL build
- SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
When creating a EFI/GUID partition map for the RK3399-Q7 through
U-Boot, the partition entries should be places at a 1MB offset from
the start of the device to give us space for the environment (at 16KB
on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the
image payload (at 256KB on SD/MMC devices).
This change sets this up through the u-boot,efi-partition-entries-offset
/config property in the RK3399-Q7 DTSI.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
As our SPL stage can grow quite large (80KB+ are not unusual) on the
RK3399-Q7, the default setting for the environment location (in
include/configs/rockchip-common.h) can overlap our SPL.
This change finally makes use of the 'u-boot,mmc-env-offset' DTS
property to override the environment location and put it at 16KB into
the device, which is right before the SPL (located at 32KB).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This removes the unused 'rate' field from both rk3399_pmuclk_priv and
rk3399_clk_priv. I didn't bother to check where this came from (i.e.
what the historical context of these was), but only verified that
these are indeed unused across all code-paths.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When building for a TPL/SPL setup (e.g. on the RK3368), we need the
TPL stage to have the extra space for for the 'Rockchip SPL name'
(i.e. 'RK33' word). Yet, the SPL will start execution at its first
word (i.e. the first word in the SPL binary needs to be a valid
instruction). To make things a bit more involved, CONFIG_SPL_BUILD
is defined both for the SPL and the TPL stage.
To avoid having to explicitly test for the first stage (TPL, if and
only if TPL and SPL are built, SPL otherwise), this commit modifies
the sequence to repeat the 'b reset' (instead of reserving 4 bytes
of undefined space) at the start of the boot0 hook: if overwritten
(and execution starts at the second word), the first instruction is
still a 'b reset'... if not overwritten, we start on a 'b reset' as
well.
This solution wouldn't even require the check whether we are in the
SPL/TPL build (i.e. CONFIG_SPL_BUILD), but we leave this check in for
documentation purposes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use mask to clear old setting before direct set the new config,
or else there it will mess up the config when it's not the same
with default value.
Fixes: 3851059 rockchip: Setup default PWM flags
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add regulator-init-microvolt for driver to init the regulator,
and the min output value is not 800000mV for the PWM2 io domain has
changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to
correct it with the value measured when PWM2 output HIGH.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
According to my test, some of firefly-rk3399 hang after dram init
when using ddr3-1333 config, while using ddr3-1600 config works
for all the board I have test.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The Identification Page (32 byte) is an additional page which can be written
and (later) permanently locked in Read-only mode.
phyCORE-RK3288 SoMs are using this page to describe the module variant.
This page also contains a MAC.
Our boards can be equipped with a different amount of EEPROMs. To make
this more transparent let's add an alias for the eeprom which stores the
module variant.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
We are about to reuse the rockchip timer (header file) for 64bit ARMv8
chips, so it seems a good time to make the register sizes explicit by
changing from 'unsigned int' to 'u32'.
Reorders the header-includes in rk_timer.c to ensure that 'u32' is
definded before it is used by 'asm/arch/timer.h'.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
FMC driver is now able to discover the bank number by
parsing bank subnodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Migrate all FMC defines from arch/arm/include/asm/arch-stm32f7/fmc.h
to drivers/ram/stm32_sdram.c
This will avoid to add an additionnal arch-stm32xx/fmc.h file when
a new stm32 family soc will be introduced.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
clean the code by removing unused enums, structs and
defines related to clocks
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Add clock framework .get_rate callback.
This step will allow to convert all drivers which was using
proprietary clock_get() to use clock framework .get_rate().
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Also remove its declaration from stm32.h which
is no more needed.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Use the same clocks macro than the one used by kernel DT.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
The inline assembly functions in mon.c assume that the caller will
check for the return value in r0 according to regular ARM calling
conventions.
However, this assumption breaks down if the compiler inlines the
functions. The caller is then under no obligation to use r0 for the
result.
To fix this disconnect, we must explicitly move the return value
from the smc/bl call to the variable that the function returns.
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
On early K2 devices (eg. K2HK) the secure ROM code does not support
loading secure code to firewall protected memory, before decrypting,
authenticating and executing it.
To load the boot monitor on these devices, it is necessary to first
authenticate and run a copy loop from non-secure memory that copies
the boot monitor behind firewall protected memory, before decrypting
and executing it.
On K2G, the secure ROM does not allow secure code executing from
unprotected memory. Further, ROM first copies the signed and encrypted
image into firewall protected memory, then decrypts, authenticates
and executes it.
As a result of this, we cannot use the copy loop for K2G. The
mon_install has to be modified to pass the address the signed and
encrypted secure boot monitor image to the authentication API.
For backward compatibility with other K2 devices and K2G GP,
the mon_install API still supports a single argument. In this case
the second argument is set to 0 by u-boot and is ignored by ROM
Signed-off-by: Thanh Tran <thanh-tran@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit adds GPIO support to the Amlogic Meson pin controller
driver, based on code from Linux kernel.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Import Amlogic Meson DTS files from Linux kernel version 4.12
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As is often the case with SoC development, slightly different
products (i.e. different part number) are developed based on the
same silicon-die. Such fine grained information is unmaintainable.
Also, "SoC:" is a better fit that "CPU:".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
It has been a while since ARM Trusted Firmware supported UniPhier SoC
family. U-Boot SPL was intended as a temporary loader that runs in
secure world. It is a maintenance headache to support two different
boot mechanisms. Secure firmware is realm of ARM Trusted Firmware
and now U-Boot only serves as a non-secure boot loader for UniPhier
ARMv8 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
This converts the following to Kconfig:
CONFIG_ENV_IS_IN_MMC
CONFIG_ENV_IS_IN_NAND
CONFIG_ENV_IS_IN_UBI
CONFIG_ENV_IS_NOWHERE
In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.
In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.
There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with
./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC
And then manual updates. This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch fixes 2 bugs introduced by the following commit
2bb5b63 MIPS: bootm: rework and fix broken bootm code
The CONFIG_IS_ENABLED macro prepends 'CONFIG_' Hence, remove CONFIG_
from CONFIG_MIPS_BOOT_ENV_LEGACY usage.
Also, 2bb5b63 reworks bootm so that linux_env_legacy runs before
linux_cmdline_legacy. However, linux_env_legacy depends on
linux_cmdline_legacy running first as linux_cmdline_init initialilzes
linux_argp which linux_env_legacy later depends on during its
initialization.
Reorder the code so that linux_cmdline_legacy runs before
linux_env_legacy.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
U-Boot has up until now built with -fpic for the MIPS architecture,
producing position independent code which uses indirection through a
global offset table, making relocation fairly straightforward as it
simply involves patching up GOT entries.
Using -fpic does however have some downsides. The biggest of these is
that generated code is bloated in various ways. For example, function
calls are indirected through the GOT & the t9 register:
8f998064 lw t9,-32668(gp)
0320f809 jalr t9
Without -fpic the call is simply:
0f803f01 jal be00fc04 <puts>
This is more compact & faster (due to the lack of the load & the
dependency the jump has on its result). It is also easier to read &
debug because the disassembly shows what function is being called,
rather than just an offset from gp which would then have to be looked up
in the ELF to discover the target function.
Another disadvantage of -fpic is that each function begins with a
sequence to calculate the value of the gp register, for example:
3c1c0004 lui gp,0x4
279c3384 addiu gp,gp,13188
0399e021 addu gp,gp,t9
Without using -fpic this sequence no longer appears at the start of each
function, reducing code size considerably.
This patch switches U-Boot from building with -fpic to building with
-fno-pic, in order to gain the benefits described above. The cost of
this is an extra step during the build process to extract relocation
data from the ELF & write it into a new .rel section in a compact
format, plus the added complexity of dealing with multiple types of
relocation rather than the single type that applied to the GOT. The
benefit is smaller, cleaner, more debuggable code. The relocate_code()
function is reimplemented in C to handle the new relocation scheme,
which also makes it easier to read & debug.
Taking maltael_defconfig as an example the size of u-boot.bin built
using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils
2.24.90) shrinks from 254KiB to 224KiB.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The above CONFIG options are in Kconfig, and now have correct depends and
inter-dependencies. Migrate these to configs/ from include/configs/. In the
case of CMD_UBIFS also change it to be a default y if CMD_UBI.
Signed-off-by: Tom Rini <trini@konsulko.com>
Fixes 4bd754d8ab ("arm: omap: Detect boot mode very early") where
the intent was to store the boot params information in a known
location and pass it to SPL very early. Unfortunately it didn't
account for OMAP3 boards.
This patch adds adds this functionality back into OMAP3 boards.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
commit 2eb48ff7a2 ("powerpc, 8260: remove support for mpc8260")
removed support for 8260 CPU.
This patch remove some remainders.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Add missing .h and add missing declarations in .h
Declare local functions as static. Make interrupt_init_cpu function
signatures consistent with how decrementer_count is declared.
Based on warnings reported by 'make C=2'
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[trini: drop cpu_init_f as 8xx/83xx are different from the rest, rework
interrupt_init_cpu/decrementer_count]
Signed-off-by: Tom Rini <trini@konsulko.com>
Avoid unnecessary assembly functions when they can easily be written
in C.
Also remove dc_read() as it is nowhere referenced
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
All complex case have been removed and we now only support
MPC866 and MPC885 families.
So check_CPU() can be made a lot simpler.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
reginfo command is calling mpc8xx_reginfo(), mpc85xx_reginfo()
or mpc86xx_reginfo() based on CONFIG_ symbol.
As those 3 functions can't me defined at the same time, let's
rename them print_reginfo() to avoid the #ifdefs
The name is kept generic as it is not at all dependent on
powerpc arch and any other arch could want to also print
such information.
In addition, as the Makefile compiles cmd/reginfo.c only when
CONFIG_CMD_REGINFO is set, there is no need to enclose the U_BOOT_CMD
definition inside a #ifdef CONFIG_CMD_REGINFO
Lets all remove the #ifdefs around the U_BOOT_CMD as this
file is only compiled when CONFIG_CMD_REGINFO is defined
Finally, this is a PowerPC-only command, disable it on a number of
non-PowerPC platforms.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
In order to avoid TBU increment due to TBL reaching its max
and wrapping, reset TBL before resetting TBU
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
The actions inside #ifdef CONFIG_8xx in arch/powerpc/lib/time.c
can be performed before, in a 8xx dedicated function.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Similar to what is done with OMAP5 class boards we need to
perform fixups common to this SoC class, add support for this here
and add HS fixups.
Signed-off-by: Andrew F. Davis <afd@ti.com>
If a firmware node is already present in the FDT we will fail to create
one and so fail to add our OP-TEE node, make this fixup first check for
a firmware node and then only try to add one if it is not found.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Some of the fixups currently done for OMAP5 class boards are common to
other OMAP family devices, move these to fdt-common.c.
Signed-off-by: Andrew F. Davis <afd@ti.com>
TEE loading and firewall setup are common to all omap2 devices, move
these function out of omap5 and into mach-omap2. This allows us
to use these functions from other omap class devices.
Signed-off-by: Andrew F. Davis <afd@ti.com>
The Odroid C2 has two GiB of memory with two reserved regions.
reg = <0x0 0x0 0x0 0x1000000>;
reg = <0x0 0x10000000 0x0 0x200000>;
Patch
bfcef28ae4 (arm: add initial support for Amlogic Meson and
ODROID-C2) provided function dram_init_banksize to reserve the
first 16 MiB of RAM for firmware in function dram_init_banksize
in arch/arm/mach-meson/board.c and defined
CONFIG_NR_DRAM_BANKS = 1.
With this patch dram_init_banksize is changed to additionally
reserve the 2MiB region for the ARM Trusted Firmware (BL31).
CONFIG_NR_DRAM_BANKS is set to 2.
Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.
This change is also coherent with the structure in kernel.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
As mx6sabreauto supports SPL now, all variants can boot using the same
defconfig.
This patch:
- Removes non-SPL targets.
- Renames target to mx6sabreauto_defconfig.
- Renames folder and board files to mx6sabreauto.
- Updates MAINTAINERS, Makefile and Kconfig accordingly.
- Removes .cfg files.
- Adds a README with instructions to build and flash SPL and u-boot.img.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Add support for mx6q, mx6dl and mx6qp sabreauto boards in SPL.
Retrieved the mx6q DCD table from:
board/freescale/mx6qsabreauto/imximage.cfg
Retrieved the mx6dl DCD table from:
board/freescale/mx6qsabreauto/mx6dl.cfg
Retrieved the mx6qp DCD table from:
board/freescale/mx6qsabreauto/mx6qp.cfg
Flashed SPL and u-boot.img to an SD card and could successfully boot it
on mx6q, mx6qp and mx6dl sabreauto boards.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Currently the following build error is seen when a board using MMC SPL
is built and the MXS nand driver is also selected:
arch/arm/cpu/armv7/built-in.o: In function `arch_cpu_init':
arch/arm/cpu/armv7/mx6/soc.c:432: undefined reference to 'mxs_dma_init'
On mx6 the only user of mxs_dma_init() is the mxs nand driver, so
move it there.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
i.MX 6UL and 6ULL have different boot device capabilities and
use therefor use a different boot device selection table than
other i.MX 6 devices. Particularly, the value which has been
used so far (b0001) is assigned to QSPI boot for these two
devices.
There is no common reserved value for all i.MX 6devices. Use
b0010 for i.MX 6UL and 6ULL via compile time ifdef.
Reported-by: Joël Esponde <joel.esponde@honeywell.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Joël Esponde <joel.esponde@honeywell.com>
The Turris Omnia is a open-source router created by CZ.NIC.
The code is based on the Marvell/db-88f6820-gp by Stefan Roese
with modifications from Tomas Hlavacek in the CZ.NIC turris-omnia-uboot
repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot
By default, the Turris Omnia uses btrfs as the main and only filesystem,
and also loads kernel and device tree from this filesystem. Since U-Boot
does not yet support btrfs, you should not flash your Turris Omnia board
with this unless you know what you are doing.
Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz>
Signed-off-by: Marek Behun <marek.behun@nic.cz>
create mode 100644 board/CZ.NIC/turris_omnia/Makefile
create mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg
create mode 100644 board/CZ.NIC/turris_omnia/turris_omnia.c
create mode 100644 configs/turris_omnia_defconfig
create mode 100644 include/configs/turris_omnia.h
Signed-off-by: Stefan Roese <sr@denx.de>
This device tree is taken from mainline Linux kernel commit
7b7db5ab. Added is also a -u-boot.dtsi file with these additions:
- aliases for I2C and SPI devices are added, because i2cmux and
SPI flash doesn't work otherwise
- spi_flash node has been added so that the new DM API works
- the ATSHA204A node is added in the i2c@5 node
- "u-boot,dm-pre-reloc"s are added in needed nodes for SPL
build to work correctly
Signed-off-by: Marek Behun <marek.behun@nic.cz>
create mode 100644 arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
create mode 100644 arch/arm/dts/armada-385-turris-omnia.dts
Signed-off-by: Stefan Roese <sr@denx.de>
The declaration of otg*_plat and otg*_board_data is guarded by
CONFIG_USB_MUSB_*, but their use in arch_misc_init is not. The
ifdef flow goes something like:
if (CONFIG_USB_MUSB_* && other_conditions)
declare usb_data
if (other_conditions)
use usb_data
Thus when CONFIG_USB_MUSB_* is not declared, we try to use the
data structures, but these structures aren't defined.
To fix this, move the USB initialization code into the same #ifdef
which guards the declaration of the data structures. Since the DM_USB
vs legacy cases are completely different, use two versions of
arch_misc_init(), for readability.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The TI816x has 2 GPIO banks. For bank 0 we had been clearing the enable
bit when setting BIT(8). Correct this by setting it to BIT(1) | BIT(8)
after we set and wait for BIT(1) (aka PRCM_MOD_EN). Enable GPIO1 as
well so that when CMD_GPIO is enabled it won't crash probing the second
bank. Enable CMD_GPIO on ti816x_evm.
Signed-off-by: Tom Rini <trini@konsulko.com>
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Many tegra boards have the console UART node disabled. With livetree this
prevents serial from working since it does not 'force' the console to be
bound. Updates the affected boards to fix this error.
The boards were checked with:
for b in $(grep tegra boards.cfg |grep -v integrator | \
awk '{print $7}' | sort); do
echo $b;
fdtgrep -c nvidia,tegra20-uart b/$b/u-boot.dtb |grep okay;
done
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
This error condition should have a debug() message. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Update these two files so include files in the right order.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Currently we have code which prints out platform data at the start of SPL.
Now that we have tests for dtoc this is probably not necessary. Drop it.
Update test_ofplatdata to check for empty output since it is useful to
check that sandbox_spl works as expected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable the pre-console buffer, displaying the model and post-relocation
console announce on sandbox. Also add a model name to the device tree.
This allows testing of these features.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
As a demonstration of how to use SCSI with driver model, move link over
to use this. This patch needs more work, but illustrates the concept.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The 'mode' parameter is actually a flag to determine whether to display
a list of devices found during the scan. Rename it to reflect this, add a
function comment and adjust callers to use a boolean.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With driver model these functions need a device pointer. Add one even
when CONFIG_DM_SCSI is not defined. This avoids having ugly conditional
function prototypes, When CONFIG_DM_SCSI is not defined we can just ignore
the pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we have the SATA and PATA drivers mixed up in the drivers/block
directory. It is better to split them out into their own place. Use
drivers/ata which is what Linux does.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present CONFIG_CMD_SATA enables the 'sata' command which also brings
in SATA support. Some boards may wish to enable SATA without the command.
Add a separate CONFIG to permit this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add aliases for mmc controller to get a fixed order with
emmc at index 0 and sdmmc at index 1.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add some tests which check the behaviour of uclass_first_device() and
uclass_next_device() when probing of a device fails.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for the gmac ethernet interface to pinctrl. This hardcodes
the setup to match that of the firefly and Radxa Rock2 boards, using the
RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Use fixed regulator for sdmmc-pwren for sdmmc power.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:
- 1 GB DDR3 RAM (2 Banks)
- 1x 4 KB EEPROM
- DP83867 Gigabit Ethernet PHY
- 16 MB SPI Flash
- 4 GB eMMC Flash
Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add fixed regulator for the port of typec0 and typec1 to control vbus
instead of gpio.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable dwc2 controller and add fixed regulator for dwc2 controller to
control vbus.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The driver changes gpio to fixed regulator to control vbus, so add
fixed regulator node in DTS for xhci driver.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
According to rk3288 spec, the pwm register order is:
PWM_PWM0_CNT,
PWM_PWM0_PERIOD_HPR,
PWM_PWM0_DUTY_LPR,
PWM_PWM0_CTRL
but the source code's order is:
struct rk3288_pwm {
u32 cnt;
u32 duty_lpr;
u32 period_hpr;
u32 ctrl;
};
So, correct it here. It is the same as RK3399.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Edited the commit message:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable sdmmc device and add the spl boot device sequence.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable soc support for SPL and U-boot skeleton.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The dts files are from kernel and with modify to adapt U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add dmc node to enable sdram driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add a dmc node for sdram driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
fixup: 3036 fix for sdram_common
According to rk3328 TRM:
0~0xff000000 is ddr space;
0xff000000~0xffffffff is device space.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This covers the DRAM controller initialisation for the RK3188, RK3288
and RK3399... all of these read some of the tuning/setup/timing
parameters from the device-tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The size of the secure image does not include the size of the
header, subtract this out before we move the image or we grab
extra data after the image.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
gpio2 is used to detect lcd based on which pin mux is done in SPL.
gpio7 is used to enable vtt regulator. Enable these two gpio nodes
in SPL.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable spl_early_init() so that spl can use
DT very early during boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
ROM stores the boot params information in a known location
and passes it to SPL. This information needs to be copied
very early during boot or else there is a chance of getting
corrupted by SPL. So move this boot device detection very early
during boot.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This port adds support for:
1) Serial
2) eMMC
3) USB
It has been tested with ARM TRUSTED FIRMWARE running u-boot as the
BL33 executable [see board's README]
eMMC has been tested for reading and booting the loader and linux
kernels as well as saving the u-boot environment.
USB has been tested with ASIX networking adapter and SanDisk 7.4GB
drive.
PSCI has been tested via the reset call (PSCI executes from DDR)
The firwmare upgrade process has been tested via TFTP and USB FAT
filesystem containing the fastboot.bin image in one of the partitions.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Add basic DT support for K2G ICE evm. Only minimal peripherals are
supported to allow console output and MMC boot.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Disable netcp by default like all other peripherals in the dtsi file.
Enable the peripheral explicitly in the board specific dts file.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Upstream Linux has the unit address being added to the various 66AK2Gx
boards dts. Therefore, update the dts to mimic this change.
Also remove memory node from the base K2G dtsi file.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
