mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
power, timer: reset TBL before TBU
In order to avoid TBU increment due to TBL reaching its max and wrapping, reset TBL before resetting TBU Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
This commit is contained in:
parent
93e85d02b2
commit
f0eda3cb89
|
@ -66,7 +66,7 @@ int timer_init(void)
|
|||
unsigned long temp;
|
||||
|
||||
/* reset */
|
||||
asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
|
||||
asm volatile("li %0,0 ; mttbl %0 ; mttbu %0;"
|
||||
: "=&r"(temp) );
|
||||
|
||||
return (0);
|
||||
|
|
Loading…
Reference in New Issue
Block a user