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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini 2017-08-11 07:10:18 -04:00
commit 7f513e8196
29 changed files with 88 additions and 61 deletions
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2
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -307,7 +307,7 @@ config SYS_FSL_DSPI_CLK_DIV
default 2
help
This is the divider that is used to derive DSPI clock from Platform
PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
clock, in another word DSPI_clk = Platform_clk / this_divider.
config SYS_FSL_DUART_CLK_DIV
int "DUART clock divider"

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -35,6 +35,7 @@
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)

20
board/freescale/common/ns_access.c
View File

@ -10,15 +10,15 @@
#include <asm/arch/ns_access.h>
#include <asm/arch/fsl_serdes.h>
void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
void set_devices_ns_access(unsigned long index, u16 val)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
u32 *reg;
uint32_t tmp;
reg = base + ns_dev->ind / 2;
reg = base + index / 2;
tmp = in_be32(reg);
if (ns_dev->ind % 2 == 0) {
if (index % 2 == 0) {
tmp &= 0x0000ffff;
tmp |= val << 16;
} else {
@ -34,7 +34,7 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
int i;
for (i = 0; i < num; i++)
set_devices_ns_access(ns_dev + i, ns_dev[i].val);
set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
}
void enable_layerscape_ns_access(void)
@ -50,20 +50,20 @@ void set_pcie_ns_access(int pcie, u16 val)
switch (pcie) {
#ifdef CONFIG_PCIE1
case PCIE1:
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
set_devices_ns_access(CSU_CSLX_PCIE1, val);
set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
return;
#endif
#ifdef CONFIG_PCIE2
case PCIE2:
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
set_devices_ns_access(CSU_CSLX_PCIE2, val);
set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
return;
#endif
#ifdef CONFIG_PCIE3
case PCIE3:
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
set_devices_ns_access(CSU_CSLX_PCIE3, val);
set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
return;
#endif
default:

4
board/freescale/ls1021aiot/ls1021aiot.c
View File

@ -201,10 +201,6 @@ int board_init(void)
ls102xa_smmu_stream_id_init();
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
return 0;
}

1
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -435,7 +435,6 @@ void board_init_f(ulong dummy)
/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
enable_layerscape_ns_access();
#endif
/*

4
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -261,10 +261,6 @@ int board_init(void)
config_serdes_mux();
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");

4
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -69,10 +69,6 @@ int board_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_SECURE_BOOT
/*
* In case of Secure Boot, the IBR configures the SMMU

2
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
View File

@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
0c150010 0e000000 00000000 00000000
0c150012 0e000000 00000000 00000000
11335559 40000012 60040000 c1000000
00000000 00000000 00000000 00238800
20124000 00003000 00000096 00000001

2
board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
View File

@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
0c150010 0e000000 00000000 00000000
0c150012 0e000000 00000000 00000000
11335559 40005012 60040000 c1000000
00000000 00000000 00000000 00238800
20124000 00003101 00000096 00000001

71
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -204,25 +204,12 @@ int config_board_mux(int ctrl_type)
int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#ifdef CONFIG_FSL_MC_ENET
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
u32 val;
init_final_memctl_regs();
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
env_hwconfig = getenv("hwconfig");
if (hwconfig_f("dspi", env_hwconfig) &&
DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
config_board_mux(MUX_TYPE_DSPI);
else
config_board_mux(MUX_TYPE_SDHC);
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
@ -257,31 +244,31 @@ int board_early_init_f(void)
int misc_init_r(void)
{
#ifdef CONFIG_FSL_QIXIS
/*
* LS2081ARDB has smart voltage translator which needs
* to be programmed as below
*/
#ifndef CONFIG_TARGET_LS2081ARDB
u8 sw;
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 val;
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
env_hwconfig = getenv("hwconfig");
if (hwconfig_f("dspi", env_hwconfig) &&
DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
config_board_mux(MUX_TYPE_DSPI);
else
config_board_mux(MUX_TYPE_SDHC);
sw = QIXIS_READ(arch);
/*
* LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
* LS2081ARDB RevF board has smart voltage translator
* which needs to be programmed to enable high speed SD interface
* by setting GPIO4_10 output to zero
*/
if ((sw & 0xf) == 0x5) {
#endif
#ifdef CONFIG_TARGET_LS2081ARDB
out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
in_le32(GPIO4_GPDIR_ADDR)));
out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
in_le32(GPIO4_GPDAT_ADDR)));
#ifndef CONFIG_TARGET_LS2081ARDB
}
#endif
#endif
if (hwconfig("sdhc"))
config_board_mux(MUX_TYPE_SDHC);
@ -341,6 +328,32 @@ void board_quiesce_devices(void)
#endif
#ifdef CONFIG_OF_BOARD_SETUP
void fsl_fdt_fixup_flash(void *fdt)
{
int offset;
/*
* IFC and QSPI are muxed on board.
* So disable IFC node in dts if QSPI is enabled or
* disable QSPI node in dts in case QSPI is not enabled.
*/
#ifdef CONFIG_FSL_QSPI
offset = fdt_path_offset(fdt, "/soc/ifc");
if (offset < 0)
offset = fdt_path_offset(fdt, "/ifc");
#else
offset = fdt_path_offset(fdt, "/soc/quadspi");
if (offset < 0)
offset = fdt_path_offset(fdt, "/quadspi");
#endif
if (offset < 0)
return;
fdt_status_disabled(fdt, offset);
}
int ft_board_setup(void *blob, bd_t *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
@ -368,6 +381,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
fsl_fdt_fixup_flash(blob);
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
#endif

1
configs/ls1021aqds_nand_defconfig
View File

@ -58,6 +58,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021aqds_qspi_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021aqds_sdcard_ifc_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021aqds_sdcard_qspi_defconfig
View File

@ -61,6 +61,7 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_nor_defconfig
View File

@ -42,6 +42,7 @@ CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_qspi_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -54,6 +54,7 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

1
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -61,6 +61,7 @@ CONFIG_DM_SPI=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y

4
drivers/mmc/fsl_esdhc.c
View File

@ -930,8 +930,6 @@ __weak int esdhc_status_fixup(void *blob, const char *compat)
return 1;
}
#endif
do_fixup_by_compat(blob, compat, "status", "okay",
sizeof("okay"), 1);
return 0;
}
@ -968,7 +966,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
fdt_addr_t addr;
unsigned int val;
int ret;

11
drivers/net/fsl-mc/mc.c
View File

@ -1336,14 +1336,18 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
{
int err = 0;
bool is_dpl_apply_status = false;
bool mc_boot_status = false;
if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
mc_apply_dpl(mc_lazy_dpl_addr);
mc_lazy_dpl_addr = 0;
}
if (!get_mc_boot_status())
mc_boot_status = true;
/* MC is not loaded intentionally, So return success. */
if (bd && get_mc_boot_status() != 0)
if (bd && !mc_boot_status)
return 0;
/* If DPL is deployed, set is_dpl_apply_status as TRUE. */
@ -1354,11 +1358,14 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
* For case MC is loaded but DPL is not deployed, return success and
* print message on console. Else FDT fix-up code execution hanged.
*/
if (bd && !get_mc_boot_status() && !is_dpl_apply_status) {
if (bd && mc_boot_status && !is_dpl_apply_status) {
printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
return 0;
}
if (bd && mc_boot_status && is_dpl_apply_status)
return 0;
err = dpbp_exit();
if (err < 0) {
printf("dpbp_exit() failed: %d\n", err);

3
drivers/pci/pcie_layerscape.c
View File

@ -478,6 +478,7 @@ static int ls_pcie_probe(struct udevice *dev)
bool ep_mode;
uint svr;
int ret;
fdt_size_t cfg_size;
pcie->bus = dev;
@ -539,8 +540,10 @@ static int ls_pcie_probe(struct udevice *dev)
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
cfg_size = fdt_resource_size(&pcie->cfg_res);
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
pcie->ctrl = pcie->lut + 0x40000;
}

2
include/configs/ls1012aqds.h
View File

@ -115,6 +115,8 @@
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

2
include/configs/ls2080a_common.h
View File

@ -33,7 +33,7 @@
#define CONFIG_SYS_TEXT_BASE 0x20100000
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
#define CONFIG_SUPPORT_RAW_INITRD

2
include/fsl_csu.h
View File

@ -30,7 +30,7 @@ struct csu_ns_dev {
};
void enable_layerscape_ns_access(void);
void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
void set_devices_ns_access(unsigned long, u16 val);
void set_pcie_ns_access(int pcie, u16 val);
#endif

2
include/usb/ehci-ci.h
View File

@ -156,7 +156,7 @@
#elif defined(CONFIG_MPC85xx)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
#elif defined(CONFIG_ARCH_LS1021A)
#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0
#endif